1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/FormattedStream.h"
34 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
35 cl::desc("Disable Post Regalloc"));
36 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
37 cl::desc("Disable branch folding"));
38 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
39 cl::desc("Disable code placement"));
40 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
41 cl::desc("Disable Stack Slot Coloring"));
42 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
43 cl::desc("Disable Machine LICM"));
44 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
45 cl::desc("Disable Machine Sinking"));
46 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
47 cl::desc("Disable Loop Strength Reduction Pass"));
48 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
49 cl::desc("Disable Codegen Prepare"));
50 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
51 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
52 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
53 cl::desc("Print LLVM IR input to isel pass"));
54 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
55 cl::desc("Dump emitter generated instructions as assembly"));
56 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
57 cl::desc("Dump garbage collector data"));
58 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
59 cl::desc("Verify generated machine code"),
60 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
62 // Enable or disable FastISel. Both options are needed, because
63 // FastISel is enabled by default with -fast, and we wish to be
64 // able to enable or disable fast-isel independently from -O0.
65 static cl::opt<cl::boolOrDefault>
66 EnableFastISelOption("fast-isel", cl::Hidden,
67 cl::desc("Enable the \"fast\" instruction selector"));
70 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
71 const std::string &TargetTriple)
73 AsmInfo = T.createAsmInfo(TargetTriple);
79 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
80 formatted_raw_ostream &Out,
81 CodeGenFileType FileType,
82 CodeGenOpt::Level OptLevel) {
83 // Add common CodeGen passes.
84 if (addCommonCodeGenPasses(PM, OptLevel))
85 return FileModel::Error;
90 case TargetMachine::AssemblyFile:
91 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
92 return FileModel::Error;
93 return FileModel::AsmFile;
94 case TargetMachine::ObjectFile:
95 if (getMachOWriterInfo())
96 return FileModel::MachOFile;
97 else if (getELFWriterInfo())
98 return FileModel::ElfFile;
101 return FileModel::Error;
104 bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
105 CodeGenOpt::Level OptLevel,
107 formatted_raw_ostream &Out) {
108 FunctionPass *Printer =
109 getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
117 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
118 /// be split up (e.g., to add an object writer pass), this method can be used to
119 /// finish up adding passes to emit the file, if necessary.
120 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
121 MachineCodeEmitter *MCE,
122 CodeGenOpt::Level OptLevel) {
124 addSimpleCodeEmitter(PM, OptLevel, *MCE);
126 addAssemblyEmitter(PM, OptLevel, true, ferrs());
128 PM.add(createGCInfoDeleter());
130 return false; // success!
133 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
134 /// be split up (e.g., to add an object writer pass), this method can be used to
135 /// finish up adding passes to emit the file, if necessary.
136 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
138 CodeGenOpt::Level OptLevel) {
140 addSimpleCodeEmitter(PM, OptLevel, *JCE);
142 addAssemblyEmitter(PM, OptLevel, true, ferrs());
144 PM.add(createGCInfoDeleter());
146 return false; // success!
149 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
150 /// be split up (e.g., to add an object writer pass), this method can be used to
151 /// finish up adding passes to emit the file, if necessary.
152 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
153 ObjectCodeEmitter *OCE,
154 CodeGenOpt::Level OptLevel) {
156 addSimpleCodeEmitter(PM, OptLevel, *OCE);
158 addAssemblyEmitter(PM, OptLevel, true, ferrs());
160 PM.add(createGCInfoDeleter());
162 return false; // success!
165 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
166 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
167 /// actually outputting the machine code and resolving things like the address
168 /// of functions. This method should returns true if machine code emission is
171 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
172 MachineCodeEmitter &MCE,
173 CodeGenOpt::Level OptLevel) {
174 // Add common CodeGen passes.
175 if (addCommonCodeGenPasses(PM, OptLevel))
178 addCodeEmitter(PM, OptLevel, MCE);
180 addAssemblyEmitter(PM, OptLevel, true, ferrs());
182 PM.add(createGCInfoDeleter());
184 return false; // success!
187 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
188 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
189 /// actually outputting the machine code and resolving things like the address
190 /// of functions. This method should returns true if machine code emission is
193 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
195 CodeGenOpt::Level OptLevel) {
196 // Add common CodeGen passes.
197 if (addCommonCodeGenPasses(PM, OptLevel))
200 addCodeEmitter(PM, OptLevel, JCE);
202 addAssemblyEmitter(PM, OptLevel, true, ferrs());
204 PM.add(createGCInfoDeleter());
206 return false; // success!
209 static void printAndVerify(PassManagerBase &PM,
211 bool allowDoubleDefs = false) {
212 if (PrintMachineCode)
213 PM.add(createMachineFunctionPrinterPass(errs(), Banner));
215 if (VerifyMachineCode)
216 PM.add(createMachineVerifierPass(allowDoubleDefs));
219 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
220 /// emitting to assembly files or machine code output.
222 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
223 CodeGenOpt::Level OptLevel) {
224 // Standard LLVM-Level Passes.
226 // Run loop strength reduction before anything else.
227 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
228 PM.add(createLoopStrengthReducePass(getTargetLowering()));
230 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
233 // Turn exception handling constructs into something the code generators can
235 switch (getMCAsmInfo()->getExceptionHandlingType())
237 case ExceptionHandling::SjLj:
238 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
239 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
240 PM.add(createSjLjEHPass(getTargetLowering()));
242 case ExceptionHandling::Dwarf:
243 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
245 case ExceptionHandling::None:
246 PM.add(createLowerInvokePass(getTargetLowering()));
250 PM.add(createGCLoweringPass());
252 // Make sure that no unreachable blocks are instruction selected.
253 PM.add(createUnreachableBlockEliminationPass());
255 if (OptLevel != CodeGenOpt::None && !DisableCGP)
256 PM.add(createCodeGenPreparePass(getTargetLowering()));
258 PM.add(createStackProtectorPass(getTargetLowering()));
261 PM.add(createPrintFunctionPass("\n\n"
262 "*** Final LLVM Code input to ISel ***\n",
265 // Standard Lower-Level Passes.
267 // Set up a MachineFunction for the rest of CodeGen to work on.
268 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
270 // Enable FastISel with -fast, but allow that to be overridden.
271 if (EnableFastISelOption == cl::BOU_TRUE ||
272 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
273 EnableFastISel = true;
275 // Ask the target for an isel.
276 if (addInstSelector(PM, OptLevel))
279 // Print the instruction selected machine code...
280 printAndVerify(PM, "After Instruction Selection",
281 /* allowDoubleDefs= */ true);
283 if (OptLevel != CodeGenOpt::None) {
284 if (!DisableMachineLICM)
285 PM.add(createMachineLICMPass());
286 if (!DisableMachineSink)
287 PM.add(createMachineSinkingPass());
288 printAndVerify(PM, "After MachineLICM and MachineSinking",
289 /* allowDoubleDefs= */ true);
292 // Run pre-ra passes.
293 if (addPreRegAlloc(PM, OptLevel))
294 printAndVerify(PM, "After PreRegAlloc passes",
295 /* allowDoubleDefs= */ true);
297 // Perform register allocation.
298 PM.add(createRegisterAllocator());
299 printAndVerify(PM, "After Register Allocation");
301 // Perform stack slot coloring.
302 if (OptLevel != CodeGenOpt::None && !DisableSSC) {
303 // FIXME: Re-enable coloring with register when it's capable of adding
305 PM.add(createStackSlotColoringPass(false));
306 printAndVerify(PM, "After StackSlotColoring");
309 // Run post-ra passes.
310 if (addPostRegAlloc(PM, OptLevel))
311 printAndVerify(PM, "After PostRegAlloc passes");
313 PM.add(createLowerSubregsPass());
314 printAndVerify(PM, "After LowerSubregs");
316 // Insert prolog/epilog code. Eliminate abstract frame index references...
317 PM.add(createPrologEpilogCodeInserter());
318 printAndVerify(PM, "After PrologEpilogCodeInserter");
320 // Run pre-sched2 passes.
321 if (addPreSched2(PM, OptLevel))
322 printAndVerify(PM, "After PreSched2 passes");
324 // Second pass scheduler.
325 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
326 PM.add(createPostRAScheduler(OptLevel));
327 printAndVerify(PM, "After PostRAScheduler");
330 // Branch folding must be run after regalloc and prolog/epilog insertion.
331 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
332 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
333 printAndVerify(PM, "After BranchFolding");
336 PM.add(createGCMachineCodeAnalysisPass());
339 PM.add(createGCInfoPrinter(errs()));
341 // Fold redundant debug labels.
342 PM.add(createDebugLabelFoldingPass());
343 printAndVerify(PM, "After DebugLabelFolding");
345 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
346 PM.add(createCodePlacementOptPass());
347 printAndVerify(PM, "After CodePlacementOpt");
350 if (addPreEmitPass(PM, OptLevel))
351 printAndVerify(PM, "After PreEmit passes");