1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/DenseSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
41 // Hidden options for help debugging.
42 static cl::opt<bool> DisableReMat("disable-rematerialization",
43 cl::init(false), cl::Hidden);
45 STATISTIC(numIntervals , "Number of original intervals");
47 char LiveIntervals::ID = 0;
48 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
50 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
53 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
54 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
55 "Live Interval Analysis", false, false)
57 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<AliasAnalysis>();
60 AU.addPreserved<AliasAnalysis>();
61 AU.addRequired<LiveVariables>();
62 AU.addPreserved<LiveVariables>();
63 AU.addPreservedID(MachineLoopInfoID);
64 AU.addPreservedID(MachineDominatorsID);
65 AU.addPreserved<SlotIndexes>();
66 AU.addRequiredTransitive<SlotIndexes>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 void LiveIntervals::releaseMemory() {
71 // Free the live intervals themselves.
72 for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
73 E = r2iMap_.end(); I != E; ++I)
79 RegMaskBlocks.clear();
81 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
82 VNInfoAllocator.Reset();
85 /// runOnMachineFunction - Register allocate the whole function
87 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
89 mri_ = &mf_->getRegInfo();
90 tm_ = &fn.getTarget();
91 tri_ = tm_->getRegisterInfo();
92 tii_ = tm_->getInstrInfo();
93 aa_ = &getAnalysis<AliasAnalysis>();
94 lv_ = &getAnalysis<LiveVariables>();
95 indexes_ = &getAnalysis<SlotIndexes>();
96 allocatableRegs_ = tri_->getAllocatableSet(fn);
97 reservedRegs_ = tri_->getReservedRegs(fn);
101 numIntervals += getNumIntervals();
107 /// print - Implement the dump method.
108 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
109 OS << "********** INTERVALS **********\n";
111 // Dump the physregs.
112 for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
113 if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
118 // Dump the virtregs.
119 for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
120 if (const LiveInterval *LI =
121 r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
129 void LiveIntervals::printInstrs(raw_ostream &OS) const {
130 OS << "********** MACHINEINSTRS **********\n";
131 mf_->print(OS, indexes_);
134 void LiveIntervals::dumpInstrs() const {
139 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
140 unsigned Reg = MI.getOperand(MOIdx).getReg();
141 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
142 const MachineOperand &MO = MI.getOperand(i);
145 if (MO.getReg() == Reg && MO.isDef()) {
146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
147 MI.getOperand(MOIdx).getSubReg() &&
148 (MO.getSubReg() || MO.isImplicit()));
155 /// isPartialRedef - Return true if the specified def at the specific index is
156 /// partially re-defining the specified live interval. A common case of this is
157 /// a definition of the sub-register.
158 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
159 LiveInterval &interval) {
160 if (!MO.getSubReg() || MO.isEarlyClobber())
163 SlotIndex RedefIndex = MIIdx.getRegSlot();
164 const LiveRange *OldLR =
165 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
173 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
174 MachineBasicBlock::iterator mi,
178 LiveInterval &interval) {
179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
181 // Virtual registers may be defined multiple times (due to phi
182 // elimination and 2-addr elimination). Much of what we do only has to be
183 // done once for the vreg. We use an empty interval to detect the first
184 // time we see a vreg.
185 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
186 if (interval.empty()) {
187 // Get the Idx of the defining instructions.
188 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
190 // Make sure the first definition is not a partial redefinition. Add an
191 // <imp-def> of the full register.
192 // FIXME: LiveIntervals shouldn't modify the code like this. Whoever
193 // created the machine instruction should annotate it with <undef> flags
194 // as needed. Then we can simply assert here. The REG_SEQUENCE lowering
195 // is the main suspect.
196 if (MO.getSubReg()) {
197 mi->addRegisterDefined(interval.reg);
198 // Mark all defs of interval.reg on this instruction as reading <undef>.
199 for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
200 MachineOperand &MO2 = mi->getOperand(i);
201 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
206 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
207 assert(ValNo->id == 0 && "First value in interval is not 0?");
209 // Loop over all of the blocks that the vreg is defined in. There are
210 // two cases we have to handle here. The most common case is a vreg
211 // whose lifetime is contained within a basic block. In this case there
212 // will be a single kill, in MBB, which comes after the definition.
213 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
214 // FIXME: what about dead vars?
216 if (vi.Kills[0] != mi)
217 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
219 killIdx = defIndex.getDeadSlot();
221 // If the kill happens after the definition, we have an intra-block
223 if (killIdx > defIndex) {
224 assert(vi.AliveBlocks.empty() &&
225 "Shouldn't be alive across any blocks!");
226 LiveRange LR(defIndex, killIdx, ValNo);
227 interval.addRange(LR);
228 DEBUG(dbgs() << " +" << LR << "\n");
233 // The other case we handle is when a virtual register lives to the end
234 // of the defining block, potentially live across some blocks, then is
235 // live into some number of blocks, but gets killed. Start by adding a
236 // range that goes from this definition to the end of the defining block.
237 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
238 DEBUG(dbgs() << " +" << NewLR);
239 interval.addRange(NewLR);
241 bool PHIJoin = lv_->isPHIJoin(interval.reg);
244 // A phi join register is killed at the end of the MBB and revived as a new
245 // valno in the killing blocks.
246 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
247 DEBUG(dbgs() << " phi-join");
248 ValNo->setHasPHIKill(true);
250 // Iterate over all of the blocks that the variable is completely
251 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
253 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
254 E = vi.AliveBlocks.end(); I != E; ++I) {
255 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
256 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
257 interval.addRange(LR);
258 DEBUG(dbgs() << " +" << LR);
262 // Finally, this virtual register is live from the start of any killing
263 // block to the 'use' slot of the killing instruction.
264 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
265 MachineInstr *Kill = vi.Kills[i];
266 SlotIndex Start = getMBBStartIdx(Kill->getParent());
267 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
269 // Create interval with one of a NEW value number. Note that this value
270 // number isn't actually defined by an instruction, weird huh? :)
272 assert(getInstructionFromIndex(Start) == 0 &&
273 "PHI def index points at actual instruction.");
274 ValNo = interval.getNextValue(Start, VNInfoAllocator);
275 ValNo->setIsPHIDef(true);
277 LiveRange LR(Start, killIdx, ValNo);
278 interval.addRange(LR);
279 DEBUG(dbgs() << " +" << LR);
283 if (MultipleDefsBySameMI(*mi, MOIdx))
284 // Multiple defs of the same virtual register by the same instruction.
285 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
286 // This is likely due to elimination of REG_SEQUENCE instructions. Return
287 // here since there is nothing to do.
290 // If this is the second time we see a virtual register definition, it
291 // must be due to phi elimination or two addr elimination. If this is
292 // the result of two address elimination, then the vreg is one of the
293 // def-and-use register operand.
295 // It may also be partial redef like this:
296 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
297 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
298 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
299 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
300 // If this is a two-address definition, then we have already processed
301 // the live range. The only problem is that we didn't realize there
302 // are actually two values in the live interval. Because of this we
303 // need to take the LiveRegion that defines this register and split it
305 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
307 const LiveRange *OldLR =
308 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
309 VNInfo *OldValNo = OldLR->valno;
310 SlotIndex DefIndex = OldValNo->def.getRegSlot();
312 // Delete the previous value, which should be short and continuous,
313 // because the 2-addr copy must be in the same MBB as the redef.
314 interval.removeRange(DefIndex, RedefIndex);
316 // The new value number (#1) is defined by the instruction we claimed
318 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
320 // Value#0 is now defined by the 2-addr instruction.
321 OldValNo->def = RedefIndex;
323 // Add the new live interval which replaces the range for the input copy.
324 LiveRange LR(DefIndex, RedefIndex, ValNo);
325 DEBUG(dbgs() << " replace range with " << LR);
326 interval.addRange(LR);
328 // If this redefinition is dead, we need to add a dummy unit live
329 // range covering the def slot.
331 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
335 dbgs() << " RESULT: ";
336 interval.print(dbgs(), tri_);
338 } else if (lv_->isPHIJoin(interval.reg)) {
339 // In the case of PHI elimination, each variable definition is only
340 // live until the end of the block. We've already taken care of the
341 // rest of the live range.
343 SlotIndex defIndex = MIIdx.getRegSlot();
344 if (MO.isEarlyClobber())
345 defIndex = MIIdx.getRegSlot(true);
347 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
349 SlotIndex killIndex = getMBBEndIdx(mbb);
350 LiveRange LR(defIndex, killIndex, ValNo);
351 interval.addRange(LR);
352 ValNo->setHasPHIKill(true);
353 DEBUG(dbgs() << " phi-join +" << LR);
355 llvm_unreachable("Multiply defined register");
359 DEBUG(dbgs() << '\n');
363 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
364 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
365 SE = MBB->succ_end();
367 const MachineBasicBlock* succ = *SI;
368 if (succ->isLiveIn(Reg))
375 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
376 MachineBasicBlock::iterator mi,
379 LiveInterval &interval) {
380 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
382 SlotIndex baseIndex = MIIdx;
383 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
384 SlotIndex end = start;
386 // If it is not used after definition, it is considered dead at
387 // the instruction defining it. Hence its interval is:
388 // [defSlot(def), defSlot(def)+1)
389 // For earlyclobbers, the defSlot was pushed back one; the extra
390 // advance below compensates.
392 DEBUG(dbgs() << " dead");
393 end = start.getDeadSlot();
397 // If it is not dead on definition, it must be killed by a
398 // subsequent instruction. Hence its interval is:
399 // [defSlot(def), useSlot(kill)+1)
400 baseIndex = baseIndex.getNextIndex();
401 while (++mi != MBB->end()) {
403 if (mi->isDebugValue())
405 if (getInstructionFromIndex(baseIndex) == 0)
406 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
408 if (mi->killsRegister(interval.reg, tri_)) {
409 DEBUG(dbgs() << " killed");
410 end = baseIndex.getRegSlot();
413 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
415 if (mi->isRegTiedToUseOperand(DefIdx)) {
416 // Two-address instruction.
417 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
419 // Another instruction redefines the register before it is ever read.
420 // Then the register is essentially dead at the instruction that
421 // defines it. Hence its interval is:
422 // [defSlot(def), defSlot(def)+1)
423 DEBUG(dbgs() << " dead");
424 end = start.getDeadSlot();
430 baseIndex = baseIndex.getNextIndex();
433 // If we get here the register *should* be live out.
434 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
436 // FIXME: We need saner rules for reserved regs.
437 if (isReserved(interval.reg)) {
438 end = start.getDeadSlot();
440 // Unreserved, unallocable registers like EFLAGS can be live across basic
442 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
443 "Unreserved reg not live-out?");
444 end = getMBBEndIdx(MBB);
447 assert(start < end && "did not find end of interval?");
449 // Already exists? Extend old live interval.
450 VNInfo *ValNo = interval.getVNInfoAt(start);
451 bool Extend = ValNo != 0;
453 ValNo = interval.getNextValue(start, VNInfoAllocator);
454 LiveRange LR(start, end, ValNo);
455 interval.addRange(LR);
456 DEBUG(dbgs() << " +" << LR << '\n');
459 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
460 MachineBasicBlock::iterator MI,
464 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
465 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
466 getOrCreateInterval(MO.getReg()));
468 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
469 getOrCreateInterval(MO.getReg()));
472 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
474 LiveInterval &interval) {
475 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
476 "Only physical registers can be live in.");
477 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
478 MBB->isLandingPad()) &&
479 "Allocatable live-ins only valid for entry blocks and landing pads.");
481 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
483 // Look for kills, if it reaches a def before it's killed, then it shouldn't
484 // be considered a livein.
485 MachineBasicBlock::iterator mi = MBB->begin();
486 MachineBasicBlock::iterator E = MBB->end();
487 // Skip over DBG_VALUE at the start of the MBB.
488 if (mi != E && mi->isDebugValue()) {
489 while (++mi != E && mi->isDebugValue())
492 // MBB is empty except for DBG_VALUE's.
496 SlotIndex baseIndex = MIIdx;
497 SlotIndex start = baseIndex;
498 if (getInstructionFromIndex(baseIndex) == 0)
499 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
501 SlotIndex end = baseIndex;
502 bool SeenDefUse = false;
505 if (mi->killsRegister(interval.reg, tri_)) {
506 DEBUG(dbgs() << " killed");
507 end = baseIndex.getRegSlot();
510 } else if (mi->modifiesRegister(interval.reg, tri_)) {
511 // Another instruction redefines the register before it is ever read.
512 // Then the register is essentially dead at the instruction that defines
513 // it. Hence its interval is:
514 // [defSlot(def), defSlot(def)+1)
515 DEBUG(dbgs() << " dead");
516 end = start.getDeadSlot();
521 while (++mi != E && mi->isDebugValue())
522 // Skip over DBG_VALUE.
525 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
528 // Live-in register might not be used at all.
530 if (isAllocatable(interval.reg) ||
531 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
532 // Allocatable registers are never live through.
533 // Non-allocatable registers that aren't live into any successors also
534 // aren't live through.
535 DEBUG(dbgs() << " dead");
538 // If we get here the register is non-allocatable and live into some
539 // successor. We'll conservatively assume it's live-through.
540 DEBUG(dbgs() << " live through");
541 end = getMBBEndIdx(MBB);
545 SlotIndex defIdx = getMBBStartIdx(MBB);
546 assert(getInstructionFromIndex(defIdx) == 0 &&
547 "PHI def index points at actual instruction.");
548 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
549 vni->setIsPHIDef(true);
550 LiveRange LR(start, end, vni);
552 interval.addRange(LR);
553 DEBUG(dbgs() << " +" << LR << '\n');
556 /// computeIntervals - computes the live intervals for virtual
557 /// registers. for some ordering of the machine instructions [1,N] a
558 /// live interval is an interval [i, j) where 1 <= i <= j < N for
559 /// which a variable is live
560 void LiveIntervals::computeIntervals() {
561 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
562 << "********** Function: "
563 << ((Value*)mf_->getFunction())->getName() << '\n');
565 RegMaskBlocks.resize(mf_->getNumBlockIDs());
567 SmallVector<unsigned, 8> UndefUses;
568 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
570 MachineBasicBlock *MBB = MBBI;
571 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
576 // Track the index of the current machine instr.
577 SlotIndex MIIndex = getMBBStartIdx(MBB);
578 DEBUG(dbgs() << "BB#" << MBB->getNumber()
579 << ":\t\t# derived from " << MBB->getName() << "\n");
581 // Create intervals for live-ins to this BB first.
582 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
583 LE = MBB->livein_end(); LI != LE; ++LI) {
584 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
587 // Skip over empty initial indices.
588 if (getInstructionFromIndex(MIIndex) == 0)
589 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
591 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
593 DEBUG(dbgs() << MIIndex << "\t" << *MI);
594 if (MI->isDebugValue())
596 assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
597 "Lost SlotIndex synchronization");
600 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
601 MachineOperand &MO = MI->getOperand(i);
603 // Collect register masks.
604 if (MO.isRegMask()) {
605 RegMaskSlots.push_back(MIIndex.getRegSlot());
606 RegMaskBits.push_back(MO.getRegMask());
610 if (!MO.isReg() || !MO.getReg())
613 // handle register defs - build intervals
615 handleRegisterDef(MBB, MI, MIIndex, MO, i);
616 else if (MO.isUndef())
617 UndefUses.push_back(MO.getReg());
620 // Move to the next instr slot.
621 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
624 // Compute the number of register mask instructions in this block.
625 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
626 RMB.second = RegMaskSlots.size() - RMB.first;;
629 // Create empty intervals for registers defined by implicit_def's (except
630 // for those implicit_def that define values which are liveout of their
632 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
633 unsigned UndefReg = UndefUses[i];
634 (void)getOrCreateInterval(UndefReg);
638 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
639 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
640 return new LiveInterval(reg, Weight);
643 /// dupInterval - Duplicate a live interval. The caller is responsible for
644 /// managing the allocated memory.
645 LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
646 LiveInterval *NewLI = createInterval(li->reg);
647 NewLI->Copy(*li, mri_, getVNInfoAllocator());
651 /// shrinkToUses - After removing some uses of a register, shrink its live
652 /// range to just the remaining uses. This method does not compute reaching
653 /// defs for new uses, and it doesn't remove dead defs.
654 bool LiveIntervals::shrinkToUses(LiveInterval *li,
655 SmallVectorImpl<MachineInstr*> *dead) {
656 DEBUG(dbgs() << "Shrink: " << *li << '\n');
657 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
658 && "Can only shrink virtual registers");
659 // Find all the values used, including PHI kills.
660 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
662 // Blocks that have already been added to WorkList as live-out.
663 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
665 // Visit all instructions reading li->reg.
666 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
667 MachineInstr *UseMI = I.skipInstruction();) {
668 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
670 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
671 // Note: This intentionally picks up the wrong VNI in case of an EC redef.
673 VNInfo *VNI = li->getVNInfoBefore(Idx);
675 // This shouldn't happen: readsVirtualRegister returns true, but there is
676 // no live value. It is likely caused by a target getting <undef> flags
678 DEBUG(dbgs() << Idx << '\t' << *UseMI
679 << "Warning: Instr claims to read non-existent value in "
683 // Special case: An early-clobber tied operand reads and writes the
684 // register one slot early. The getVNInfoBefore call above would have
685 // picked up the value defined by UseMI. Adjust the kill slot and value.
686 if (SlotIndex::isSameInstr(VNI->def, Idx)) {
688 VNI = li->getVNInfoBefore(Idx);
689 assert(VNI && "Early-clobber tied value not available");
691 WorkList.push_back(std::make_pair(Idx, VNI));
694 // Create a new live interval with only minimal live segments per def.
695 LiveInterval NewLI(li->reg, 0);
696 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
701 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
704 // Keep track of the PHIs that are in use.
705 SmallPtrSet<VNInfo*, 8> UsedPHIs;
707 // Extend intervals to reach all uses in WorkList.
708 while (!WorkList.empty()) {
709 SlotIndex Idx = WorkList.back().first;
710 VNInfo *VNI = WorkList.back().second;
712 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
713 SlotIndex BlockStart = getMBBStartIdx(MBB);
715 // Extend the live range for VNI to be live at Idx.
716 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
718 assert(ExtVNI == VNI && "Unexpected existing value number");
719 // Is this a PHIDef we haven't seen before?
720 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
722 // The PHI is live, make sure the predecessors are live-out.
723 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
724 PE = MBB->pred_end(); PI != PE; ++PI) {
725 if (!LiveOut.insert(*PI))
727 SlotIndex Stop = getMBBEndIdx(*PI);
728 // A predecessor is not required to have a live-out value for a PHI.
729 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
730 WorkList.push_back(std::make_pair(Stop, PVNI));
735 // VNI is live-in to MBB.
736 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
737 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
739 // Make sure VNI is live-out from the predecessors.
740 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
741 PE = MBB->pred_end(); PI != PE; ++PI) {
742 if (!LiveOut.insert(*PI))
744 SlotIndex Stop = getMBBEndIdx(*PI);
745 assert(li->getVNInfoBefore(Stop) == VNI &&
746 "Wrong value out of predecessor");
747 WorkList.push_back(std::make_pair(Stop, VNI));
751 // Handle dead values.
752 bool CanSeparate = false;
753 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
758 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
759 assert(LII != NewLI.end() && "Missing live range for PHI");
760 if (LII->end != VNI->def.getDeadSlot())
762 if (VNI->isPHIDef()) {
763 // This is a dead PHI. Remove it.
764 VNI->setIsUnused(true);
765 NewLI.removeRange(*LII);
766 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
769 // This is a dead def. Make sure the instruction knows.
770 MachineInstr *MI = getInstructionFromIndex(VNI->def);
771 assert(MI && "No instruction defining live value");
772 MI->addRegisterDead(li->reg, tri_);
773 if (dead && MI->allDefsAreDead()) {
774 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
780 // Move the trimmed ranges back.
781 li->ranges.swap(NewLI.ranges);
782 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
787 //===----------------------------------------------------------------------===//
788 // Register allocator hooks.
791 void LiveIntervals::addKillFlags() {
792 for (iterator I = begin(), E = end(); I != E; ++I) {
793 unsigned Reg = I->first;
794 if (TargetRegisterInfo::isPhysicalRegister(Reg))
796 if (mri_->reg_nodbg_empty(Reg))
798 LiveInterval *LI = I->second;
800 // Every instruction that kills Reg corresponds to a live range end point.
801 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
803 // A block index indicates an MBB edge.
804 if (RI->end.isBlock())
806 MachineInstr *MI = getInstructionFromIndex(RI->end);
809 MI->addRegisterKilled(Reg, NULL);
815 static bool intervalRangesSane(const LiveInterval& li) {
820 SlotIndex lastEnd = li.begin()->start;
821 for (LiveInterval::const_iterator lrItr = li.begin(), lrEnd = li.end();
822 lrItr != lrEnd; ++lrItr) {
823 const LiveRange& lr = *lrItr;
824 if (lastEnd > lr.start || lr.start >= lr.end)
833 template <typename DefSetT>
834 static void handleMoveDefs(LiveIntervals& lis, SlotIndex origIdx,
835 SlotIndex miIdx, const DefSetT& defs) {
836 for (typename DefSetT::const_iterator defItr = defs.begin(),
838 defItr != defEnd; ++defItr) {
839 unsigned def = *defItr;
840 LiveInterval& li = lis.getInterval(def);
841 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
842 assert(lr != 0 && "No range for def?");
843 lr->start = miIdx.getRegSlot();
844 lr->valno->def = miIdx.getRegSlot();
845 assert(intervalRangesSane(li) && "Broke live interval moving def.");
849 template <typename DeadDefSetT>
850 static void handleMoveDeadDefs(LiveIntervals& lis, SlotIndex origIdx,
851 SlotIndex miIdx, const DeadDefSetT& deadDefs) {
852 for (typename DeadDefSetT::const_iterator deadDefItr = deadDefs.begin(),
853 deadDefEnd = deadDefs.end();
854 deadDefItr != deadDefEnd; ++deadDefItr) {
855 unsigned deadDef = *deadDefItr;
856 LiveInterval& li = lis.getInterval(deadDef);
857 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
858 assert(lr != 0 && "No range for dead def?");
859 assert(lr->start == origIdx.getRegSlot() && "Bad dead range start?");
860 assert(lr->end == origIdx.getDeadSlot() && "Bad dead range end?");
861 assert(lr->valno->def == origIdx.getRegSlot() && "Bad dead valno def.");
863 t.start = miIdx.getRegSlot();
864 t.valno->def = miIdx.getRegSlot();
865 t.end = miIdx.getDeadSlot();
868 assert(intervalRangesSane(li) && "Broke live interval moving dead def.");
872 template <typename ECSetT>
873 static void handleMoveECs(LiveIntervals& lis, SlotIndex origIdx,
874 SlotIndex miIdx, const ECSetT& ecs) {
875 for (typename ECSetT::const_iterator ecItr = ecs.begin(), ecEnd = ecs.end();
876 ecItr != ecEnd; ++ecItr) {
877 unsigned ec = *ecItr;
878 LiveInterval& li = lis.getInterval(ec);
879 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot(true));
880 assert(lr != 0 && "No range for early clobber?");
881 assert(lr->start == origIdx.getRegSlot(true) && "Bad EC range start?");
882 assert(lr->end == origIdx.getRegSlot() && "Bad EC range end.");
883 assert(lr->valno->def == origIdx.getRegSlot(true) && "Bad EC valno def.");
885 t.start = miIdx.getRegSlot(true);
886 t.valno->def = miIdx.getRegSlot(true);
887 t.end = miIdx.getRegSlot();
890 assert(intervalRangesSane(li) && "Broke live interval moving EC.");
894 static void moveKillFlags(unsigned reg, SlotIndex oldIdx, SlotIndex newIdx,
896 const TargetRegisterInfo& tri) {
897 MachineInstr* oldKillMI = lis.getInstructionFromIndex(oldIdx);
898 MachineInstr* newKillMI = lis.getInstructionFromIndex(newIdx);
899 assert(oldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
900 assert(!newKillMI->killsRegister(reg) && "New kill instr is already a kill.");
901 oldKillMI->clearRegisterKills(reg, &tri);
902 newKillMI->addRegisterKilled(reg, &tri);
905 template <typename UseSetT>
906 static void handleMoveUses(const MachineBasicBlock *mbb,
907 const MachineRegisterInfo& mri,
908 const TargetRegisterInfo& tri,
909 const BitVector& reservedRegs, LiveIntervals &lis,
910 SlotIndex origIdx, SlotIndex miIdx,
911 const UseSetT &uses) {
912 bool movingUp = miIdx < origIdx;
913 for (typename UseSetT::const_iterator usesItr = uses.begin(),
914 usesEnd = uses.end();
915 usesItr != usesEnd; ++usesItr) {
916 unsigned use = *usesItr;
917 if (!lis.hasInterval(use))
919 if (TargetRegisterInfo::isPhysicalRegister(use) && reservedRegs.test(use))
921 LiveInterval& li = lis.getInterval(use);
922 LiveRange* lr = li.getLiveRangeBefore(origIdx.getRegSlot());
923 assert(lr != 0 && "No range for use?");
924 bool liveThrough = lr->end > origIdx.getRegSlot();
927 // If moving up and liveThrough - nothing to do.
928 // If not live through we need to extend the range to the last use
929 // between the old location and the new one.
931 SlotIndex lastUseInRange = miIdx.getRegSlot();
932 for (MachineRegisterInfo::use_iterator useI = mri.use_begin(use),
933 useE = mri.use_end();
934 useI != useE; ++useI) {
935 const MachineInstr* mopI = &*useI;
936 const MachineOperand& mop = useI.getOperand();
937 SlotIndex instSlot = lis.getSlotIndexes()->getInstructionIndex(mopI);
938 SlotIndex opSlot = instSlot.getRegSlot(mop.isEarlyClobber());
939 if (opSlot > lastUseInRange && opSlot < origIdx)
940 lastUseInRange = opSlot;
943 // If we found a new instr endpoint update the kill flags.
944 if (lastUseInRange != miIdx.getRegSlot())
945 moveKillFlags(use, miIdx, lastUseInRange, lis, tri);
947 // Fix up the range end.
948 lr->end = lastUseInRange;
951 // Moving down is easy - the existing live range end tells us where
954 // Easy fix - just update the range endpoint.
955 lr->end = miIdx.getRegSlot();
957 bool liveOut = lr->end >= lis.getSlotIndexes()->getMBBEndIdx(mbb);
958 if (!liveOut && miIdx.getRegSlot() > lr->end) {
959 moveKillFlags(use, lr->end, miIdx, lis, tri);
960 lr->end = miIdx.getRegSlot();
964 assert(intervalRangesSane(li) && "Broke live interval moving use.");
970 void LiveIntervals::handleMove(MachineInstr* mi) {
971 SlotIndex origIdx = indexes_->getInstructionIndex(mi);
972 indexes_->removeMachineInstrFromMaps(mi);
973 SlotIndex miIdx = mi->isInsideBundle() ?
974 indexes_->getInstructionIndex(mi->getBundleStart()) :
975 indexes_->insertMachineInstrInMaps(mi);
976 MachineBasicBlock* mbb = mi->getParent();
977 assert(getMBBStartIdx(mbb) <= origIdx && origIdx < getMBBEndIdx(mbb) &&
978 "Cannot handle moves across basic block boundaries.");
979 assert(!mi->isBundled() && "Can't handle bundled instructions yet.");
981 // Pick the direction.
982 bool movingUp = miIdx < origIdx;
984 // Collect the operands.
985 DenseSet<unsigned> uses, defs, deadDefs, ecs;
986 for (MachineInstr::mop_iterator mopItr = mi->operands_begin(),
987 mopEnd = mi->operands_end();
988 mopItr != mopEnd; ++mopItr) {
989 const MachineOperand& mop = *mopItr;
991 if (!mop.isReg() || mop.getReg() == 0)
993 unsigned reg = mop.getReg();
995 if (mop.readsReg() && !ecs.count(reg)) {
1000 assert(!defs.count(reg) && "Can't mix defs with dead-defs.");
1001 deadDefs.insert(reg);
1002 } else if (mop.isEarlyClobber()) {
1006 assert(!deadDefs.count(reg) && "Can't mix defs with dead-defs.");
1013 handleMoveUses(mbb, *mri_, *tri_, reservedRegs_, *this, origIdx, miIdx, uses);
1014 handleMoveECs(*this, origIdx, miIdx, ecs);
1015 handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
1016 handleMoveDefs(*this, origIdx, miIdx, defs);
1018 handleMoveDefs(*this, origIdx, miIdx, defs);
1019 handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
1020 handleMoveECs(*this, origIdx, miIdx, ecs);
1021 handleMoveUses(mbb, *mri_, *tri_, reservedRegs_, *this, origIdx, miIdx, uses);
1025 /// getReMatImplicitUse - If the remat definition MI has one (for now, we only
1026 /// allow one) virtual register operand, then its uses are implicitly using
1027 /// the register. Returns the virtual register.
1028 unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
1029 MachineInstr *MI) const {
1031 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1032 MachineOperand &MO = MI->getOperand(i);
1033 if (!MO.isReg() || !MO.isUse())
1035 unsigned Reg = MO.getReg();
1036 if (Reg == 0 || Reg == li.reg)
1039 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
1041 RegOp = MO.getReg();
1042 break; // Found vreg operand - leave the loop.
1047 /// isValNoAvailableAt - Return true if the val# of the specified interval
1048 /// which reaches the given instruction also reaches the specified use index.
1049 bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
1050 SlotIndex UseIdx) const {
1051 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
1052 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
1055 /// isReMaterializable - Returns true if the definition MI of the specified
1056 /// val# of the specified interval is re-materializable.
1058 LiveIntervals::isReMaterializable(const LiveInterval &li,
1059 const VNInfo *ValNo, MachineInstr *MI,
1060 const SmallVectorImpl<LiveInterval*> *SpillIs,
1065 if (!tii_->isTriviallyReMaterializable(MI, aa_))
1068 // Target-specific code can mark an instruction as being rematerializable
1069 // if it has one virtual reg use, though it had better be something like
1070 // a PIC base register which is likely to be live everywhere.
1071 unsigned ImpUse = getReMatImplicitUse(li, MI);
1073 const LiveInterval &ImpLi = getInterval(ImpUse);
1074 for (MachineRegisterInfo::use_nodbg_iterator
1075 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
1077 MachineInstr *UseMI = &*ri;
1078 SlotIndex UseIdx = getInstructionIndex(UseMI);
1079 if (li.getVNInfoAt(UseIdx) != ValNo)
1081 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
1085 // If a register operand of the re-materialized instruction is going to
1086 // be spilled next, then it's not legal to re-materialize this instruction.
1088 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
1089 if (ImpUse == (*SpillIs)[i]->reg)
1095 /// isReMaterializable - Returns true if every definition of MI of every
1096 /// val# of the specified interval is re-materializable.
1098 LiveIntervals::isReMaterializable(const LiveInterval &li,
1099 const SmallVectorImpl<LiveInterval*> *SpillIs,
1102 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
1104 const VNInfo *VNI = *i;
1105 if (VNI->isUnused())
1106 continue; // Dead val#.
1107 // Is the def for the val# rematerializable?
1108 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
1111 bool DefIsLoad = false;
1113 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
1115 isLoad |= DefIsLoad;
1121 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
1122 // A local live range must be fully contained inside the block, meaning it is
1123 // defined and killed at instructions, not at block boundaries. It is not
1124 // live in or or out of any block.
1126 // It is technically possible to have a PHI-defined live range identical to a
1127 // single block, but we are going to return false in that case.
1129 SlotIndex Start = LI.beginIndex();
1130 if (Start.isBlock())
1133 SlotIndex Stop = LI.endIndex();
1137 // getMBBFromIndex doesn't need to search the MBB table when both indexes
1138 // belong to proper instructions.
1139 MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
1140 MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
1141 return MBB1 == MBB2 ? MBB1 : NULL;
1145 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
1146 // Limit the loop depth ridiculousness.
1147 if (loopDepth > 200)
1150 // The loop depth is used to roughly estimate the number of times the
1151 // instruction is executed. Something like 10^d is simple, but will quickly
1152 // overflow a float. This expression behaves like 10^d for small d, but is
1153 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
1154 // headroom before overflow.
1155 // By the way, powf() might be unavailable here. For consistency,
1156 // We may take pow(double,double).
1157 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
1159 return (isDef + isUse) * lc;
1162 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
1163 MachineInstr* startInst) {
1164 LiveInterval& Interval = getOrCreateInterval(reg);
1165 VNInfo* VN = Interval.getNextValue(
1166 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
1167 getVNInfoAllocator());
1168 VN->setHasPHIKill(true);
1170 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
1171 getMBBEndIdx(startInst->getParent()), VN);
1172 Interval.addRange(LR);
1178 //===----------------------------------------------------------------------===//
1179 // Register mask functions
1180 //===----------------------------------------------------------------------===//
1182 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
1183 BitVector &UsableRegs) {
1186 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
1188 // Use a smaller arrays for local live ranges.
1189 ArrayRef<SlotIndex> Slots;
1190 ArrayRef<const uint32_t*> Bits;
1191 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
1192 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
1193 Bits = getRegMaskBitsInBlock(MBB->getNumber());
1195 Slots = getRegMaskSlots();
1196 Bits = getRegMaskBits();
1199 // We are going to enumerate all the register mask slots contained in LI.
1200 // Start with a binary search of RegMaskSlots to find a starting point.
1201 ArrayRef<SlotIndex>::iterator SlotI =
1202 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
1203 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
1205 // No slots in range, LI begins after the last call.
1211 assert(*SlotI >= LiveI->start);
1212 // Loop over all slots overlapping this segment.
1213 while (*SlotI < LiveI->end) {
1214 // *SlotI overlaps LI. Collect mask bits.
1216 // This is the first overlap. Initialize UsableRegs to all ones.
1218 UsableRegs.resize(tri_->getNumRegs(), true);
1221 // Remove usable registers clobbered by this mask.
1222 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1223 if (++SlotI == SlotE)
1226 // *SlotI is beyond the current LI segment.
1227 LiveI = LI.advanceTo(LiveI, *SlotI);
1230 // Advance SlotI until it overlaps.
1231 while (*SlotI < LiveI->start)
1232 if (++SlotI == SlotE)