1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
40 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
42 Statistic<> numIntervals
43 ("liveintervals", "Number of original intervals");
45 Statistic<> numIntervalsAfter
46 ("liveintervals", "Number of intervals after coalescing");
49 ("liveintervals", "Number of interval joins performed");
52 ("liveintervals", "Number of identity moves eliminated after coalescing");
55 ("liveintervals", "Number of loads/stores folded into instructions");
58 EnableJoining("join-liveintervals",
59 cl::desc("Join compatible live intervals"),
63 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
65 AU.addPreserved<LiveVariables>();
66 AU.addRequired<LiveVariables>();
67 AU.addPreservedID(PHIEliminationID);
68 AU.addRequiredID(PHIEliminationID);
69 AU.addRequiredID(TwoAddressInstructionPassID);
70 AU.addRequired<LoopInfo>();
71 MachineFunctionPass::getAnalysisUsage(AU);
74 void LiveIntervals::releaseMemory()
83 /// runOnMachineFunction - Register allocate the whole function
85 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
87 tm_ = &fn.getTarget();
88 mri_ = tm_->getRegisterInfo();
89 lv_ = &getAnalysis<LiveVariables>();
90 allocatableRegs_ = mri_->getAllocatableSet(fn);
91 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
93 // number MachineInstrs
95 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
97 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
99 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
100 assert(inserted && "multiple MachineInstr -> index mappings");
101 i2miMap_.push_back(mi);
102 miIndex += InstrSlots::NUM;
107 numIntervals += getNumIntervals();
110 DEBUG(std::cerr << "********** INTERVALS **********\n");
111 DEBUG(for (iterator I = begin(), E = end(); I != E; ++I)
112 std::cerr << I->second << "\n");
115 // join intervals if requested
116 if (EnableJoining) joinIntervals();
118 numIntervalsAfter += getNumIntervals();
120 // perform a final pass over the instructions and compute spill
121 // weights, coalesce virtual registers and remove identity moves
122 const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
123 const TargetInstrInfo& tii = *tm_->getInstrInfo();
125 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
126 mbbi != mbbe; ++mbbi) {
127 MachineBasicBlock* mbb = mbbi;
128 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
130 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
132 // if the move will be an identity move delete it
133 unsigned srcReg, dstReg, RegRep;
134 if (tii.isMoveInstr(*mii, srcReg, dstReg) &&
135 (RegRep = rep(srcReg)) == rep(dstReg)) {
136 // remove from def list
137 LiveInterval &interval = getOrCreateInterval(RegRep);
138 // remove index -> MachineInstr and
139 // MachineInstr -> index mappings
140 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
141 if (mi2i != mi2iMap_.end()) {
142 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
143 mi2iMap_.erase(mi2i);
145 mii = mbbi->erase(mii);
149 for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
150 const MachineOperand& mop = mii->getOperand(i);
151 if (mop.isRegister() && mop.getReg() &&
152 MRegisterInfo::isVirtualRegister(mop.getReg())) {
153 // replace register with representative register
154 unsigned reg = rep(mop.getReg());
155 mii->SetMachineOperandReg(i, reg);
157 LiveInterval &RegInt = getInterval(reg);
159 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
171 /// print - Implement the dump method.
172 void LiveIntervals::print(std::ostream &O, const Module* ) const {
173 O << "********** INTERVALS **********\n";
174 for (const_iterator I = begin(), E = end(); I != E; ++I)
175 O << " " << I->second << "\n";
177 O << "********** MACHINEINSTRS **********\n";
178 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
179 mbbi != mbbe; ++mbbi) {
180 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
181 for (MachineBasicBlock::iterator mii = mbbi->begin(),
182 mie = mbbi->end(); mii != mie; ++mii) {
183 O << getInstructionIndex(mii) << '\t' << *mii;
188 std::vector<LiveInterval*> LiveIntervals::
189 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
190 // since this is called after the analysis is done we don't know if
191 // LiveVariables is available
192 lv_ = getAnalysisToUpdate<LiveVariables>();
194 std::vector<LiveInterval*> added;
196 assert(li.weight != HUGE_VAL &&
197 "attempt to spill already spilled interval!");
199 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
202 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
204 for (LiveInterval::Ranges::const_iterator
205 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
206 unsigned index = getBaseIndex(i->start);
207 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
208 for (; index != end; index += InstrSlots::NUM) {
209 // skip deleted instructions
210 while (index != end && !getInstructionFromIndex(index))
211 index += InstrSlots::NUM;
212 if (index == end) break;
214 MachineBasicBlock::iterator mi = getInstructionFromIndex(index);
217 for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
218 MachineOperand& mop = mi->getOperand(i);
219 if (mop.isRegister() && mop.getReg() == li.reg) {
220 // First thing, attempt to fold the memory reference into the
221 // instruction. If we can do this, we don't need to insert spill
223 if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) {
225 lv_->instructionChanged(mi, fmi);
226 vrm.virtFolded(li.reg, mi, i, fmi);
228 i2miMap_[index/InstrSlots::NUM] = fmi;
229 mi2iMap_[fmi] = index;
230 MachineBasicBlock &MBB = *mi->getParent();
231 mi = MBB.insert(MBB.erase(mi), fmi);
234 // Folding the load/store can completely change the instruction in
235 // unpredictable ways, rescan it from the beginning.
238 // This is tricky. We need to add information in the interval about
239 // the spill code so we have to use our extra load/store slots.
241 // If we have a use we are going to have a load so we start the
242 // interval from the load slot onwards. Otherwise we start from the
244 unsigned start = (mop.isUse() ?
245 getLoadIndex(index) :
247 // If we have a def we are going to have a store right after it so
248 // we end the interval after the use of the next
249 // instruction. Otherwise we end after the use of this instruction.
250 unsigned end = 1 + (mop.isDef() ?
251 getStoreIndex(index) :
254 // create a new register for this spill
255 unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc);
256 mi->SetMachineOperandReg(i, nReg);
258 vrm.assignVirt2StackSlot(nReg, slot);
259 LiveInterval& nI = getOrCreateInterval(nReg);
262 // the spill weight is now infinity as it
263 // cannot be spilled again
264 nI.weight = float(HUGE_VAL);
265 LiveRange LR(start, end, nI.getNextValue());
266 DEBUG(std::cerr << " +" << LR);
268 added.push_back(&nI);
270 // update live variables if it is available
272 lv_->addVirtualRegisterKilled(nReg, mi);
273 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
283 void LiveIntervals::printRegName(unsigned reg) const
285 if (MRegisterInfo::isPhysicalRegister(reg))
286 std::cerr << mri_->getName(reg);
288 std::cerr << "%reg" << reg;
291 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
292 MachineBasicBlock::iterator mi,
293 LiveInterval& interval)
295 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
296 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
298 // Virtual registers may be defined multiple times (due to phi
299 // elimination and 2-addr elimination). Much of what we do only has to be
300 // done once for the vreg. We use an empty interval to detect the first
301 // time we see a vreg.
302 if (interval.empty()) {
303 // Get the Idx of the defining instructions.
304 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
306 unsigned ValNum = interval.getNextValue();
307 assert(ValNum == 0 && "First value in interval is not 0?");
308 ValNum = 0; // Clue in the optimizer.
310 // Loop over all of the blocks that the vreg is defined in. There are
311 // two cases we have to handle here. The most common case is a vreg
312 // whose lifetime is contained within a basic block. In this case there
313 // will be a single kill, in MBB, which comes after the definition.
314 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
315 // FIXME: what about dead vars?
317 if (vi.Kills[0] != mi)
318 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
320 killIdx = defIndex+1;
322 // If the kill happens after the definition, we have an intra-block
324 if (killIdx > defIndex) {
325 assert(vi.AliveBlocks.empty() &&
326 "Shouldn't be alive across any blocks!");
327 LiveRange LR(defIndex, killIdx, ValNum);
328 interval.addRange(LR);
329 DEBUG(std::cerr << " +" << LR << "\n");
334 // The other case we handle is when a virtual register lives to the end
335 // of the defining block, potentially live across some blocks, then is
336 // live into some number of blocks, but gets killed. Start by adding a
337 // range that goes from this definition to the end of the defining block.
338 LiveRange NewLR(defIndex,
339 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
341 DEBUG(std::cerr << " +" << NewLR);
342 interval.addRange(NewLR);
344 // Iterate over all of the blocks that the variable is completely
345 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
347 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
348 if (vi.AliveBlocks[i]) {
349 MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
351 LiveRange LR(getInstructionIndex(&mbb->front()),
352 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
354 interval.addRange(LR);
355 DEBUG(std::cerr << " +" << LR);
360 // Finally, this virtual register is live from the start of any killing
361 // block to the 'use' slot of the killing instruction.
362 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
363 MachineInstr *Kill = vi.Kills[i];
364 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
365 getUseIndex(getInstructionIndex(Kill))+1,
367 interval.addRange(LR);
368 DEBUG(std::cerr << " +" << LR);
372 // If this is the second time we see a virtual register definition, it
373 // must be due to phi elimination or two addr elimination. If this is
374 // the result of two address elimination, then the vreg is the first
375 // operand, and is a def-and-use.
376 if (mi->getOperand(0).isRegister() &&
377 mi->getOperand(0).getReg() == interval.reg &&
378 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
379 // If this is a two-address definition, then we have already processed
380 // the live range. The only problem is that we didn't realize there
381 // are actually two values in the live interval. Because of this we
382 // need to take the LiveRegion that defines this register and split it
384 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
385 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
387 // Delete the initial value, which should be short and continuous,
388 // becuase the 2-addr copy must be in the same MBB as the redef.
389 interval.removeRange(DefIndex, RedefIndex);
391 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue());
392 DEBUG(std::cerr << " replace range with " << LR);
393 interval.addRange(LR);
395 // If this redefinition is dead, we need to add a dummy unit live
396 // range covering the def slot.
397 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi),
398 E = lv_->dead_end(mi); KI != E; ++KI)
399 if (KI->second == interval.reg) {
400 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
404 DEBUG(std::cerr << "RESULT: " << interval);
407 // Otherwise, this must be because of phi elimination. If this is the
408 // first redefinition of the vreg that we have seen, go back and change
409 // the live range in the PHI block to be a different value number.
410 if (interval.containsOneValue()) {
411 assert(vi.Kills.size() == 1 &&
412 "PHI elimination vreg should have one kill, the PHI itself!");
414 // Remove the old range that we now know has an incorrect number.
415 MachineInstr *Killer = vi.Kills[0];
416 unsigned Start = getInstructionIndex(Killer->getParent()->begin());
417 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
418 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
419 << interval << "\n");
420 interval.removeRange(Start, End);
421 DEBUG(std::cerr << "RESULT: " << interval);
423 // Replace the interval with one of a NEW value number.
424 LiveRange LR(Start, End, interval.getNextValue());
425 DEBUG(std::cerr << " replace range with " << LR);
426 interval.addRange(LR);
427 DEBUG(std::cerr << "RESULT: " << interval);
430 // In the case of PHI elimination, each variable definition is only
431 // live until the end of the block. We've already taken care of the
432 // rest of the live range.
433 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
434 LiveRange LR(defIndex,
435 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
436 interval.getNextValue());
437 interval.addRange(LR);
438 DEBUG(std::cerr << " +" << LR);
442 DEBUG(std::cerr << '\n');
445 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
446 MachineBasicBlock::iterator mi,
447 LiveInterval& interval)
449 // A physical register cannot be live across basic block, so its
450 // lifetime must end somewhere in its defining basic block.
451 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
452 typedef LiveVariables::killed_iterator KillIter;
454 unsigned baseIndex = getInstructionIndex(mi);
455 unsigned start = getDefIndex(baseIndex);
456 unsigned end = start;
458 // If it is not used after definition, it is considered dead at
459 // the instruction defining it. Hence its interval is:
460 // [defSlot(def), defSlot(def)+1)
461 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
463 if (interval.reg == ki->second) {
464 DEBUG(std::cerr << " dead");
465 end = getDefIndex(start) + 1;
470 // If it is not dead on definition, it must be killed by a
471 // subsequent instruction. Hence its interval is:
472 // [defSlot(def), useSlot(kill)+1)
475 assert(mi != MBB->end() && "physreg was not killed in defining block!");
476 baseIndex += InstrSlots::NUM;
477 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
479 if (interval.reg == ki->second) {
480 DEBUG(std::cerr << " killed");
481 end = getUseIndex(baseIndex) + 1;
488 assert(start < end && "did not find end of interval?");
489 LiveRange LR(start, end, interval.getNextValue());
490 interval.addRange(LR);
491 DEBUG(std::cerr << " +" << LR << '\n');
494 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
495 MachineBasicBlock::iterator MI,
497 if (MRegisterInfo::isVirtualRegister(reg))
498 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
499 else if (allocatableRegs_[reg]) {
500 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
501 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
502 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
506 /// computeIntervals - computes the live intervals for virtual
507 /// registers. for some ordering of the machine instructions [1,N] a
508 /// live interval is an interval [i, j) where 1 <= i <= j < N for
509 /// which a variable is live
510 void LiveIntervals::computeIntervals()
512 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
513 DEBUG(std::cerr << "********** Function: "
514 << ((Value*)mf_->getFunction())->getName() << '\n');
516 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
518 MachineBasicBlock* mbb = I;
519 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
521 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
523 const TargetInstrDescriptor& tid =
524 tm_->getInstrInfo()->get(mi->getOpcode());
525 DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
527 // handle implicit defs
528 for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
529 handleRegisterDef(mbb, mi, *id);
531 // handle explicit defs
532 for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
533 MachineOperand& mop = mi->getOperand(i);
534 // handle register defs - build intervals
535 if (mop.isRegister() && mop.getReg() && mop.isDef())
536 handleRegisterDef(mbb, mi, mop.getReg());
542 void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
543 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
544 const TargetInstrInfo &TII = *tm_->getInstrInfo();
546 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
548 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
550 // we only join virtual registers with allocatable
551 // physical registers since we do not have liveness information
552 // on not allocatable physical registers
554 if (TII.isMoveInstr(*mi, regA, regB) &&
555 (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) &&
556 (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) {
558 // Get representative registers.
562 // If they are already joined we continue.
566 // If they are both physical registers, we cannot join them.
567 if (MRegisterInfo::isPhysicalRegister(regA) &&
568 MRegisterInfo::isPhysicalRegister(regB))
571 // If they are not of the same register class, we cannot join them.
572 if (differingRegisterClasses(regA, regB))
575 LiveInterval &IntA = getInterval(regA);
576 LiveInterval &IntB = getInterval(regB);
577 assert(IntA.reg == regA && IntB.reg == regB &&
578 "Register mapping is horribly broken!");
580 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": ");
582 // If two intervals contain a single value and are joined by a copy, it
583 // does not matter if the intervals overlap, they can always be joined.
584 bool TriviallyJoinable =
585 IntA.containsOneValue() && IntB.containsOneValue();
587 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
588 if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) &&
589 !overlapsAliases(&IntA, &IntB)) {
590 IntB.join(IntA, MIDefIdx);
592 if (!MRegisterInfo::isPhysicalRegister(regA)) {
594 r2rMap_[regA] = regB;
596 // Otherwise merge the data structures the other way so we don't lose
597 // the physreg information.
598 r2rMap_[regB] = regA;
603 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n");
606 DEBUG(std::cerr << "Interference!\n");
613 // DepthMBBCompare - Comparison predicate that sort first based on the loop
614 // depth of the basic block (the unsigned), and then on the MBB number.
615 struct DepthMBBCompare {
616 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
617 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
618 if (LHS.first > RHS.first) return true; // Deeper loops first
619 return LHS.first == RHS.first &&
620 LHS.second->getNumber() < RHS.second->getNumber();
625 void LiveIntervals::joinIntervals() {
626 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
628 const LoopInfo &LI = getAnalysis<LoopInfo>();
629 if (LI.begin() == LI.end()) {
630 // If there are no loops in the function, join intervals in function order.
631 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
633 joinIntervalsInMachineBB(I);
635 // Otherwise, join intervals in inner loops before other intervals.
636 // Unfortunately we can't just iterate over loop hierarchy here because
637 // there may be more MBB's than BB's. Collect MBB's for sorting.
638 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
639 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
641 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
643 // Sort by loop depth.
644 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
646 // Finally, join intervals in loop nest order.
647 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
648 joinIntervalsInMachineBB(MBBs[i].second);
651 DEBUG(std::cerr << "*** Register mapping ***\n");
652 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
654 std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n");
657 /// Return true if the two specified registers belong to different register
658 /// classes. The registers may be either phys or virt regs.
659 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
660 unsigned RegB) const {
662 // Get the register classes for the first reg.
663 if (MRegisterInfo::isPhysicalRegister(RegA)) {
664 assert(MRegisterInfo::isVirtualRegister(RegB) &&
665 "Shouldn't consider two physregs!");
666 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
669 // Compare against the regclass for the second reg.
670 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
671 if (MRegisterInfo::isVirtualRegister(RegB))
672 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
674 return !RegClass->contains(RegB);
677 bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
678 const LiveInterval *RHS) const {
679 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
680 if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
681 return false; // vreg-vreg merge has no aliases!
685 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
686 MRegisterInfo::isVirtualRegister(RHS->reg) &&
687 "first interval must describe a physical register");
689 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
690 if (RHS->overlaps(getInterval(*AS)))
696 LiveInterval LiveIntervals::createInterval(unsigned reg) {
697 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
698 (float)HUGE_VAL :0.0F;
699 return LiveInterval(reg, Weight);