1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<AliasAnalysis>();
69 AU.addPreserved<AliasAnalysis>();
70 // LiveVariables isn't really required by this analysis, it is only required
71 // here to make sure it is live during TwoAddressInstructionPass and
72 // PHIElimination. This is temporary.
73 AU.addRequired<LiveVariables>();
74 AU.addPreserved<LiveVariables>();
75 AU.addPreservedID(MachineLoopInfoID);
76 AU.addRequiredTransitiveID(MachineDominatorsID);
77 AU.addPreservedID(MachineDominatorsID);
78 AU.addPreserved<SlotIndexes>();
79 AU.addRequiredTransitive<SlotIndexes>();
80 MachineFunctionPass::getAnalysisUsage(AU);
83 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
84 DomTree(nullptr), LRCalc(nullptr) {
85 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
88 LiveIntervals::~LiveIntervals() {
92 void LiveIntervals::releaseMemory() {
93 // Free the live intervals themselves.
94 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
95 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
96 VirtRegIntervals.clear();
99 RegMaskBlocks.clear();
101 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
102 delete RegUnitRanges[i];
103 RegUnitRanges.clear();
105 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
106 VNInfoAllocator.Reset();
109 /// runOnMachineFunction - calculates LiveIntervals
111 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
113 MRI = &MF->getRegInfo();
114 TM = &fn.getTarget();
115 TRI = TM->getSubtargetImpl()->getRegisterInfo();
116 TII = TM->getSubtargetImpl()->getInstrInfo();
117 AA = &getAnalysis<AliasAnalysis>();
118 Indexes = &getAnalysis<SlotIndexes>();
119 DomTree = &getAnalysis<MachineDominatorTree>();
121 LRCalc = new LiveRangeCalc();
123 // Allocate space for all virtual registers.
124 VirtRegIntervals.resize(MRI->getNumVirtRegs());
128 computeLiveInRegUnits();
130 if (EnablePrecomputePhysRegs) {
131 // For stress testing, precompute live ranges of all physical register
132 // units, including reserved registers.
133 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
140 /// print - Implement the dump method.
141 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
142 OS << "********** INTERVALS **********\n";
144 // Dump the regunits.
145 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
146 if (LiveRange *LR = RegUnitRanges[i])
147 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
149 // Dump the virtregs.
150 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
151 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
152 if (hasInterval(Reg))
153 OS << getInterval(Reg) << '\n';
157 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
158 OS << ' ' << RegMaskSlots[i];
164 void LiveIntervals::printInstrs(raw_ostream &OS) const {
165 OS << "********** MACHINEINSTRS **********\n";
166 MF->print(OS, Indexes);
169 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
170 void LiveIntervals::dumpInstrs() const {
175 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
176 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
177 llvm::huge_valf : 0.0F;
178 return new LiveInterval(reg, Weight);
182 /// computeVirtRegInterval - Compute the live interval of a virtual register,
183 /// based on defs and uses.
184 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
185 assert(LRCalc && "LRCalc not initialized.");
186 assert(LI.empty() && "Should only compute empty intervals.");
187 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
188 LRCalc->createDeadDefs(LI);
189 LRCalc->extendToUses(LI);
190 computeDeadValues(&LI, LI, nullptr, nullptr);
193 void LiveIntervals::computeVirtRegs() {
194 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
195 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
196 if (MRI->reg_nodbg_empty(Reg))
198 createAndComputeVirtRegInterval(Reg);
202 void LiveIntervals::computeRegMasks() {
203 RegMaskBlocks.resize(MF->getNumBlockIDs());
205 // Find all instructions with regmask operands.
206 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
208 MachineBasicBlock *MBB = MBBI;
209 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
210 RMB.first = RegMaskSlots.size();
211 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
213 for (MIOperands MO(MI); MO.isValid(); ++MO) {
214 if (!MO->isRegMask())
216 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
217 RegMaskBits.push_back(MO->getRegMask());
219 // Compute the number of register mask instructions in this block.
220 RMB.second = RegMaskSlots.size() - RMB.first;
224 //===----------------------------------------------------------------------===//
225 // Register Unit Liveness
226 //===----------------------------------------------------------------------===//
228 // Fixed interference typically comes from ABI boundaries: Function arguments
229 // and return values are passed in fixed registers, and so are exception
230 // pointers entering landing pads. Certain instructions require values to be
231 // present in specific registers. That is also represented through fixed
235 /// computeRegUnitInterval - Compute the live range of a register unit, based
236 /// on the uses and defs of aliasing registers. The range should be empty,
237 /// or contain only dead phi-defs from ABI blocks.
238 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
239 assert(LRCalc && "LRCalc not initialized.");
240 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
242 // The physregs aliasing Unit are the roots and their super-registers.
243 // Create all values as dead defs before extending to uses. Note that roots
244 // may share super-registers. That's OK because createDeadDefs() is
245 // idempotent. It is very rare for a register unit to have multiple roots, so
246 // uniquing super-registers is probably not worthwhile.
247 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
248 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
249 Supers.isValid(); ++Supers) {
250 if (!MRI->reg_empty(*Supers))
251 LRCalc->createDeadDefs(LR, *Supers);
255 // Now extend LR to reach all uses.
256 // Ignore uses of reserved registers. We only track defs of those.
257 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
258 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
259 Supers.isValid(); ++Supers) {
260 unsigned Reg = *Supers;
261 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
262 LRCalc->extendToUses(LR, Reg);
268 /// computeLiveInRegUnits - Precompute the live ranges of any register units
269 /// that are live-in to an ABI block somewhere. Register values can appear
270 /// without a corresponding def when entering the entry block or a landing pad.
272 void LiveIntervals::computeLiveInRegUnits() {
273 RegUnitRanges.resize(TRI->getNumRegUnits());
274 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
276 // Keep track of the live range sets allocated.
277 SmallVector<unsigned, 8> NewRanges;
279 // Check all basic blocks for live-ins.
280 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
282 const MachineBasicBlock *MBB = MFI;
284 // We only care about ABI blocks: Entry + landing pads.
285 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
288 // Create phi-defs at Begin for all live-in registers.
289 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
290 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
291 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
292 LIE = MBB->livein_end(); LII != LIE; ++LII) {
293 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
294 unsigned Unit = *Units;
295 LiveRange *LR = RegUnitRanges[Unit];
297 LR = RegUnitRanges[Unit] = new LiveRange();
298 NewRanges.push_back(Unit);
300 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
302 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
305 DEBUG(dbgs() << '\n');
307 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
309 // Compute the 'normal' part of the ranges.
310 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
311 unsigned Unit = NewRanges[i];
312 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
317 /// shrinkToUses - After removing some uses of a register, shrink its live
318 /// range to just the remaining uses. This method does not compute reaching
319 /// defs for new uses, and it doesn't remove dead defs.
320 bool LiveIntervals::shrinkToUses(LiveInterval *li,
321 SmallVectorImpl<MachineInstr*> *dead) {
322 DEBUG(dbgs() << "Shrink: " << *li << '\n');
323 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
324 && "Can only shrink virtual registers");
325 // Find all the values used, including PHI kills.
326 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
328 // Blocks that have already been added to WorkList as live-out.
329 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
331 // Visit all instructions reading li->reg.
332 for (MachineRegisterInfo::reg_instr_iterator
333 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
335 MachineInstr *UseMI = &*(I++);
336 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
338 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
339 LiveQueryResult LRQ = li->Query(Idx);
340 VNInfo *VNI = LRQ.valueIn();
342 // This shouldn't happen: readsVirtualRegister returns true, but there is
343 // no live value. It is likely caused by a target getting <undef> flags
345 DEBUG(dbgs() << Idx << '\t' << *UseMI
346 << "Warning: Instr claims to read non-existent value in "
350 // Special case: An early-clobber tied operand reads and writes the
351 // register one slot early.
352 if (VNInfo *DefVNI = LRQ.valueDefined())
355 WorkList.push_back(std::make_pair(Idx, VNI));
358 // Create new live ranges with only minimal live segments per def.
360 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
365 NewLR.addSegment(LiveRange::Segment(VNI->def, VNI->def.getDeadSlot(), VNI));
368 // Keep track of the PHIs that are in use.
369 SmallPtrSet<VNInfo*, 8> UsedPHIs;
371 // Extend intervals to reach all uses in WorkList.
372 while (!WorkList.empty()) {
373 SlotIndex Idx = WorkList.back().first;
374 VNInfo *VNI = WorkList.back().second;
376 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
377 SlotIndex BlockStart = getMBBStartIdx(MBB);
379 // Extend the live range for VNI to be live at Idx.
380 if (VNInfo *ExtVNI = NewLR.extendInBlock(BlockStart, Idx)) {
382 assert(ExtVNI == VNI && "Unexpected existing value number");
383 // Is this a PHIDef we haven't seen before?
384 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
386 // The PHI is live, make sure the predecessors are live-out.
387 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
388 PE = MBB->pred_end(); PI != PE; ++PI) {
389 if (!LiveOut.insert(*PI))
391 SlotIndex Stop = getMBBEndIdx(*PI);
392 // A predecessor is not required to have a live-out value for a PHI.
393 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
394 WorkList.push_back(std::make_pair(Stop, PVNI));
399 // VNI is live-in to MBB.
400 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
401 NewLR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
403 // Make sure VNI is live-out from the predecessors.
404 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
405 PE = MBB->pred_end(); PI != PE; ++PI) {
406 if (!LiveOut.insert(*PI))
408 SlotIndex Stop = getMBBEndIdx(*PI);
409 assert(li->getVNInfoBefore(Stop) == VNI &&
410 "Wrong value out of predecessor");
411 WorkList.push_back(std::make_pair(Stop, VNI));
415 // Handle dead values.
416 bool CanSeparate = false;
417 computeDeadValues(li, NewLR, &CanSeparate, dead);
419 // Move the trimmed segments back.
420 li->segments.swap(NewLR.segments);
421 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
425 void LiveIntervals::computeDeadValues(LiveInterval *li,
428 SmallVectorImpl<MachineInstr*> *dead) {
429 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
434 LiveRange::iterator LRI = LR.FindSegmentContaining(VNI->def);
435 assert(LRI != LR.end() && "Missing segment for PHI");
436 if (LRI->end != VNI->def.getDeadSlot())
438 if (VNI->isPHIDef()) {
439 // This is a dead PHI. Remove it.
441 LR.removeSegment(LRI->start, LRI->end);
442 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
446 // This is a dead def. Make sure the instruction knows.
447 MachineInstr *MI = getInstructionFromIndex(VNI->def);
448 assert(MI && "No instruction defining live value");
449 MI->addRegisterDead(li->reg, TRI);
450 if (dead && MI->allDefsAreDead()) {
451 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
458 void LiveIntervals::extendToIndices(LiveRange &LR,
459 ArrayRef<SlotIndex> Indices) {
460 assert(LRCalc && "LRCalc not initialized.");
461 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
462 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
463 LRCalc->extend(LR, Indices[i]);
466 void LiveIntervals::pruneValue(LiveInterval *LI, SlotIndex Kill,
467 SmallVectorImpl<SlotIndex> *EndPoints) {
468 LiveQueryResult LRQ = LI->Query(Kill);
469 VNInfo *VNI = LRQ.valueOut();
473 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
474 SlotIndex MBBStart, MBBEnd;
475 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(KillMBB);
477 // If VNI isn't live out from KillMBB, the value is trivially pruned.
478 if (LRQ.endPoint() < MBBEnd) {
479 LI->removeSegment(Kill, LRQ.endPoint());
480 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
484 // VNI is live out of KillMBB.
485 LI->removeSegment(Kill, MBBEnd);
486 if (EndPoints) EndPoints->push_back(MBBEnd);
488 // Find all blocks that are reachable from KillMBB without leaving VNI's live
489 // range. It is possible that KillMBB itself is reachable, so start a DFS
490 // from each successor.
491 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
493 for (MachineBasicBlock::succ_iterator
494 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
495 SuccI != SuccE; ++SuccI) {
496 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
497 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
499 MachineBasicBlock *MBB = *I;
501 // Check if VNI is live in to MBB.
502 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
503 LiveQueryResult LRQ = LI->Query(MBBStart);
504 if (LRQ.valueIn() != VNI) {
505 // This block isn't part of the VNI segment. Prune the search.
510 // Prune the search if VNI is killed in MBB.
511 if (LRQ.endPoint() < MBBEnd) {
512 LI->removeSegment(MBBStart, LRQ.endPoint());
513 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
518 // VNI is live through MBB.
519 LI->removeSegment(MBBStart, MBBEnd);
520 if (EndPoints) EndPoints->push_back(MBBEnd);
526 //===----------------------------------------------------------------------===//
527 // Register allocator hooks.
530 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
531 // Keep track of regunit ranges.
532 SmallVector<std::pair<LiveRange*, LiveRange::iterator>, 8> RU;
534 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
535 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
536 if (MRI->reg_nodbg_empty(Reg))
538 LiveInterval *LI = &getInterval(Reg);
542 // Find the regunit intervals for the assigned register. They may overlap
543 // the virtual register live range, cancelling any kills.
545 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
547 LiveRange &RURanges = getRegUnit(*Units);
548 if (RURanges.empty())
550 RU.push_back(std::make_pair(&RURanges, RURanges.find(LI->begin()->end)));
553 // Every instruction that kills Reg corresponds to a segment range end
555 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
557 // A block index indicates an MBB edge.
558 if (RI->end.isBlock())
560 MachineInstr *MI = getInstructionFromIndex(RI->end);
564 // Check if any of the regunits are live beyond the end of RI. That could
565 // happen when a physreg is defined as a copy of a virtreg:
567 // %EAX = COPY %vreg5
568 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
571 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
572 bool CancelKill = false;
573 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
574 LiveRange &RRanges = *RU[u].first;
575 LiveRange::iterator &I = RU[u].second;
576 if (I == RRanges.end())
578 I = RRanges.advanceTo(I, RI->end);
579 if (I == RRanges.end() || I->start >= RI->end)
581 // I is overlapping RI.
586 MI->clearRegisterKills(Reg, nullptr);
588 MI->addRegisterKilled(Reg, nullptr);
594 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
595 // A local live range must be fully contained inside the block, meaning it is
596 // defined and killed at instructions, not at block boundaries. It is not
597 // live in or or out of any block.
599 // It is technically possible to have a PHI-defined live range identical to a
600 // single block, but we are going to return false in that case.
602 SlotIndex Start = LI.beginIndex();
606 SlotIndex Stop = LI.endIndex();
610 // getMBBFromIndex doesn't need to search the MBB table when both indexes
611 // belong to proper instructions.
612 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
613 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
614 return MBB1 == MBB2 ? MBB1 : nullptr;
618 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
619 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
621 const VNInfo *PHI = *I;
622 if (PHI->isUnused() || !PHI->isPHIDef())
624 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
625 // Conservatively return true instead of scanning huge predecessor lists.
626 if (PHIMBB->pred_size() > 100)
628 for (MachineBasicBlock::const_pred_iterator
629 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
630 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
637 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
638 const MachineBlockFrequencyInfo *MBFI,
639 const MachineInstr *MI) {
640 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
641 const float Scale = 1.0f / MBFI->getEntryFreq();
642 return (isDef + isUse) * (Freq.getFrequency() * Scale);
646 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
647 LiveInterval& Interval = createEmptyInterval(reg);
648 VNInfo* VN = Interval.getNextValue(
649 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
650 getVNInfoAllocator());
651 LiveRange::Segment S(
652 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
653 getMBBEndIdx(startInst->getParent()), VN);
654 Interval.addSegment(S);
660 //===----------------------------------------------------------------------===//
661 // Register mask functions
662 //===----------------------------------------------------------------------===//
664 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
665 BitVector &UsableRegs) {
668 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
670 // Use a smaller arrays for local live ranges.
671 ArrayRef<SlotIndex> Slots;
672 ArrayRef<const uint32_t*> Bits;
673 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
674 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
675 Bits = getRegMaskBitsInBlock(MBB->getNumber());
677 Slots = getRegMaskSlots();
678 Bits = getRegMaskBits();
681 // We are going to enumerate all the register mask slots contained in LI.
682 // Start with a binary search of RegMaskSlots to find a starting point.
683 ArrayRef<SlotIndex>::iterator SlotI =
684 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
685 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
687 // No slots in range, LI begins after the last call.
693 assert(*SlotI >= LiveI->start);
694 // Loop over all slots overlapping this segment.
695 while (*SlotI < LiveI->end) {
696 // *SlotI overlaps LI. Collect mask bits.
698 // This is the first overlap. Initialize UsableRegs to all ones.
700 UsableRegs.resize(TRI->getNumRegs(), true);
703 // Remove usable registers clobbered by this mask.
704 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
705 if (++SlotI == SlotE)
708 // *SlotI is beyond the current LI segment.
709 LiveI = LI.advanceTo(LiveI, *SlotI);
712 // Advance SlotI until it overlaps.
713 while (*SlotI < LiveI->start)
714 if (++SlotI == SlotE)
719 //===----------------------------------------------------------------------===//
720 // IntervalUpdate class.
721 //===----------------------------------------------------------------------===//
723 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
724 class LiveIntervals::HMEditor {
727 const MachineRegisterInfo& MRI;
728 const TargetRegisterInfo& TRI;
731 SmallPtrSet<LiveRange*, 8> Updated;
735 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
736 const TargetRegisterInfo& TRI,
737 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
738 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
739 UpdateFlags(UpdateFlags) {}
741 // FIXME: UpdateFlags is a workaround that creates live intervals for all
742 // physregs, even those that aren't needed for regalloc, in order to update
743 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
744 // flags, and postRA passes will use a live register utility instead.
745 LiveRange *getRegUnitLI(unsigned Unit) {
747 return &LIS.getRegUnit(Unit);
748 return LIS.getCachedRegUnit(Unit);
751 /// Update all live ranges touched by MI, assuming a move from OldIdx to
753 void updateAllRanges(MachineInstr *MI) {
754 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
755 bool hasRegMask = false;
756 for (MIOperands MO(MI); MO.isValid(); ++MO) {
761 // Aggressively clear all kill flags.
762 // They are reinserted by VirtRegRewriter.
764 MO->setIsKill(false);
766 unsigned Reg = MO->getReg();
769 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
770 LiveInterval &LI = LIS.getInterval(Reg);
771 updateRange(LI, Reg);
775 // For physregs, only update the regunits that actually have a
776 // precomputed live range.
777 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
778 if (LiveRange *LR = getRegUnitLI(*Units))
779 updateRange(*LR, *Units);
782 updateRegMaskSlots();
786 /// Update a single live range, assuming an instruction has been moved from
787 /// OldIdx to NewIdx.
788 void updateRange(LiveRange &LR, unsigned Reg) {
789 if (!Updated.insert(&LR))
793 if (TargetRegisterInfo::isVirtualRegister(Reg))
794 dbgs() << PrintReg(Reg);
796 dbgs() << PrintRegUnit(Reg, &TRI);
797 dbgs() << ":\t" << LR << '\n';
799 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
802 handleMoveUp(LR, Reg);
803 DEBUG(dbgs() << " -->\t" << LR << '\n');
807 /// Update LR to reflect an instruction has been moved downwards from OldIdx
810 /// 1. Live def at OldIdx:
811 /// Move def to NewIdx, assert endpoint after NewIdx.
813 /// 2. Live def at OldIdx, killed at NewIdx:
814 /// Change to dead def at NewIdx.
815 /// (Happens when bundling def+kill together).
817 /// 3. Dead def at OldIdx:
818 /// Move def to NewIdx, possibly across another live value.
820 /// 4. Def at OldIdx AND at NewIdx:
821 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
822 /// (Happens when bundling multiple defs together).
824 /// 5. Value read at OldIdx, killed before NewIdx:
825 /// Extend kill to NewIdx.
827 void handleMoveDown(LiveRange &LR) {
828 // First look for a kill at OldIdx.
829 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
830 LiveRange::iterator E = LR.end();
831 // Is LR even live at OldIdx?
832 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
835 // Handle a live-in value.
836 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
837 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
838 // If the live-in value already extends to NewIdx, there is nothing to do.
839 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
841 // Aggressively remove all kill flags from the old kill point.
842 // Kill flags shouldn't be used while live intervals exist, they will be
843 // reinserted by VirtRegRewriter.
844 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
845 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
846 if (MO->isReg() && MO->isUse())
847 MO->setIsKill(false);
848 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
849 // overlapping ranges. Case 5 above.
850 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
851 // If this was a kill, there may also be a def. Otherwise we're done.
857 // Check for a def at OldIdx.
858 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
860 // We have a def at OldIdx.
861 VNInfo *DefVNI = I->valno;
862 assert(DefVNI->def == I->start && "Inconsistent def");
863 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
864 // If the defined value extends beyond NewIdx, just move the def down.
865 // This is case 1 above.
866 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
867 I->start = DefVNI->def;
870 // The remaining possibilities are now:
871 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
872 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
873 // In either case, it is possible that there is an existing def at NewIdx.
874 assert((I->end == OldIdx.getDeadSlot() ||
875 SlotIndex::isSameInstr(I->end, NewIdx)) &&
876 "Cannot move def below kill");
877 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
878 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
879 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
880 // coalesced into that value.
881 assert(NewI->valno != DefVNI && "Multiple defs of value?");
882 LR.removeValNo(DefVNI);
885 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
886 // If the def at OldIdx was dead, we allow it to be moved across other LR
887 // values. The new range should be placed immediately before NewI, move any
888 // intermediate ranges up.
889 assert(NewI != I && "Inconsistent iterators");
890 std::copy(std::next(I), NewI, I);
892 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
895 /// Update LR to reflect an instruction has been moved upwards from OldIdx
898 /// 1. Live def at OldIdx:
899 /// Hoist def to NewIdx.
901 /// 2. Dead def at OldIdx:
902 /// Hoist def+end to NewIdx, possibly move across other values.
904 /// 3. Dead def at OldIdx AND existing def at NewIdx:
905 /// Remove value defined at OldIdx, coalescing it with existing value.
907 /// 4. Live def at OldIdx AND existing def at NewIdx:
908 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
909 /// (Happens when bundling multiple defs together).
911 /// 5. Value killed at OldIdx:
912 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
915 void handleMoveUp(LiveRange &LR, unsigned Reg) {
916 // First look for a kill at OldIdx.
917 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
918 LiveRange::iterator E = LR.end();
919 // Is LR even live at OldIdx?
920 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
923 // Handle a live-in value.
924 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
925 // If the live-in value isn't killed here, there is nothing to do.
926 if (!SlotIndex::isSameInstr(OldIdx, I->end))
928 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
929 // another use, we need to search for that use. Case 5 above.
930 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
932 // If OldIdx also defines a value, there couldn't have been another use.
933 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
934 // No def, search for the new kill.
935 // This can never be an early clobber kill since there is no def.
936 std::prev(I)->end = findLastUseBefore(Reg).getRegSlot();
941 // Now deal with the def at OldIdx.
942 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
943 VNInfo *DefVNI = I->valno;
944 assert(DefVNI->def == I->start && "Inconsistent def");
945 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
947 // Check for an existing def at NewIdx.
948 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
949 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
950 assert(NewI->valno != DefVNI && "Same value defined more than once?");
951 // There is an existing def at NewIdx.
952 if (I->end.isDead()) {
953 // Case 3: Remove the dead def at OldIdx.
954 LR.removeValNo(DefVNI);
957 // Case 4: Replace def at NewIdx with live def at OldIdx.
958 I->start = DefVNI->def;
959 LR.removeValNo(NewI->valno);
963 // There is no existing def at NewIdx. Hoist DefVNI.
964 if (!I->end.isDead()) {
965 // Leave the end point of a live def.
966 I->start = DefVNI->def;
970 // DefVNI is a dead def. It may have been moved across other values in LR,
971 // so move I up to NewI. Slide [NewI;I) down one position.
972 std::copy_backward(NewI, I, std::next(I));
973 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
976 void updateRegMaskSlots() {
977 SmallVectorImpl<SlotIndex>::iterator RI =
978 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
980 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
981 "No RegMask at OldIdx.");
982 *RI = NewIdx.getRegSlot();
983 assert((RI == LIS.RegMaskSlots.begin() ||
984 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
985 "Cannot move regmask instruction above another call");
986 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
987 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
988 "Cannot move regmask instruction below another call");
991 // Return the last use of reg between NewIdx and OldIdx.
992 SlotIndex findLastUseBefore(unsigned Reg) {
994 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
995 SlotIndex LastUse = NewIdx;
996 for (MachineRegisterInfo::use_instr_nodbg_iterator
997 UI = MRI.use_instr_nodbg_begin(Reg),
998 UE = MRI.use_instr_nodbg_end();
1000 const MachineInstr* MI = &*UI;
1001 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1002 if (InstSlot > LastUse && InstSlot < OldIdx)
1008 // This is a regunit interval, so scanning the use list could be very
1009 // expensive. Scan upwards from OldIdx instead.
1010 assert(NewIdx < OldIdx && "Expected upwards move");
1011 SlotIndexes *Indexes = LIS.getSlotIndexes();
1012 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1014 // OldIdx may not correspond to an instruction any longer, so set MII to
1015 // point to the next instruction after OldIdx, or MBB->end().
1016 MachineBasicBlock::iterator MII = MBB->end();
1017 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1018 Indexes->getNextNonNullIndex(OldIdx)))
1019 if (MI->getParent() == MBB)
1022 MachineBasicBlock::iterator Begin = MBB->begin();
1023 while (MII != Begin) {
1024 if ((--MII)->isDebugValue())
1026 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1028 // Stop searching when NewIdx is reached.
1029 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1032 // Check if MII uses Reg.
1033 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1035 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1036 TRI.hasRegUnit(MO->getReg(), Reg))
1039 // Didn't reach NewIdx. It must be the first instruction in the block.
1044 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1045 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1046 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1047 Indexes->removeMachineInstrFromMaps(MI);
1048 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1049 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1050 OldIndex < getMBBEndIdx(MI->getParent()) &&
1051 "Cannot handle moves across basic block boundaries.");
1053 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1054 HME.updateAllRanges(MI);
1057 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1058 MachineInstr* BundleStart,
1060 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1061 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1062 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1063 HME.updateAllRanges(MI);
1067 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1068 MachineBasicBlock::iterator Begin,
1069 MachineBasicBlock::iterator End,
1070 ArrayRef<unsigned> OrigRegs) {
1071 // Find anchor points, which are at the beginning/end of blocks or at
1072 // instructions that already have indexes.
1073 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1075 while (End != MBB->end() && !Indexes->hasIndex(End))
1079 if (End == MBB->end())
1080 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1082 endIdx = getInstructionIndex(End);
1084 Indexes->repairIndexesInRange(MBB, Begin, End);
1086 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1088 MachineInstr *MI = I;
1089 if (MI->isDebugValue())
1091 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1092 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1094 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1095 !hasInterval(MOI->getReg())) {
1096 createAndComputeVirtRegInterval(MOI->getReg());
1101 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1102 unsigned Reg = OrigRegs[i];
1103 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1106 LiveInterval &LI = getInterval(Reg);
1107 // FIXME: Should we support undefs that gain defs?
1108 if (!LI.hasAtLeastOneValue())
1111 LiveInterval::iterator LII = LI.find(endIdx);
1112 SlotIndex lastUseIdx;
1113 if (LII != LI.end() && LII->start < endIdx)
1114 lastUseIdx = LII->end;
1118 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1120 MachineInstr *MI = I;
1121 if (MI->isDebugValue())
1124 SlotIndex instrIdx = getInstructionIndex(MI);
1125 bool isStartValid = getInstructionFromIndex(LII->start);
1126 bool isEndValid = getInstructionFromIndex(LII->end);
1128 // FIXME: This doesn't currently handle early-clobber or multiple removed
1129 // defs inside of the region to repair.
1130 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1131 OE = MI->operands_end(); OI != OE; ++OI) {
1132 const MachineOperand &MO = *OI;
1133 if (!MO.isReg() || MO.getReg() != Reg)
1137 if (!isStartValid) {
1138 if (LII->end.isDead()) {
1139 SlotIndex prevStart;
1140 if (LII != LI.begin())
1141 prevStart = std::prev(LII)->start;
1143 // FIXME: This could be more efficient if there was a
1144 // removeSegment method that returned an iterator.
1145 LI.removeSegment(*LII, true);
1146 if (prevStart.isValid())
1147 LII = LI.find(prevStart);
1151 LII->start = instrIdx.getRegSlot();
1152 LII->valno->def = instrIdx.getRegSlot();
1153 if (MO.getSubReg() && !MO.isUndef())
1154 lastUseIdx = instrIdx.getRegSlot();
1156 lastUseIdx = SlotIndex();
1161 if (!lastUseIdx.isValid()) {
1162 VNInfo *VNI = LI.getNextValue(instrIdx.getRegSlot(),
1164 LiveRange::Segment S(instrIdx.getRegSlot(),
1165 instrIdx.getDeadSlot(), VNI);
1166 LII = LI.addSegment(S);
1167 } else if (LII->start != instrIdx.getRegSlot()) {
1168 VNInfo *VNI = LI.getNextValue(instrIdx.getRegSlot(),
1170 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1171 LII = LI.addSegment(S);
1174 if (MO.getSubReg() && !MO.isUndef())
1175 lastUseIdx = instrIdx.getRegSlot();
1177 lastUseIdx = SlotIndex();
1178 } else if (MO.isUse()) {
1179 // FIXME: This should probably be handled outside of this branch,
1180 // either as part of the def case (for defs inside of the region) or
1181 // after the loop over the region.
1182 if (!isEndValid && !LII->end.isBlock())
1183 LII->end = instrIdx.getRegSlot();
1184 if (!lastUseIdx.isValid())
1185 lastUseIdx = instrIdx.getRegSlot();