1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
41 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
43 static Statistic<> numIntervals
44 ("liveintervals", "Number of original intervals");
46 static Statistic<> numIntervalsAfter
47 ("liveintervals", "Number of intervals after coalescing");
49 static Statistic<> numJoins
50 ("liveintervals", "Number of interval joins performed");
52 static Statistic<> numPeep
53 ("liveintervals", "Number of identity moves eliminated after coalescing");
55 static Statistic<> numFolded
56 ("liveintervals", "Number of loads/stores folded into instructions");
59 EnableJoining("join-liveintervals",
60 cl::desc("Join compatible live intervals"),
64 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
65 AU.addRequired<LiveVariables>();
66 AU.addPreservedID(PHIEliminationID);
67 AU.addRequiredID(PHIEliminationID);
68 AU.addRequiredID(TwoAddressInstructionPassID);
69 AU.addRequired<LoopInfo>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 void LiveIntervals::releaseMemory() {
81 static bool isZeroLengthInterval(LiveInterval *li) {
82 for (LiveInterval::Ranges::const_iterator
83 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
84 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
90 /// runOnMachineFunction - Register allocate the whole function
92 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
94 tm_ = &fn.getTarget();
95 mri_ = tm_->getRegisterInfo();
96 tii_ = tm_->getInstrInfo();
97 lv_ = &getAnalysis<LiveVariables>();
98 allocatableRegs_ = mri_->getAllocatableSet(fn);
99 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
101 // If this function has any live ins, insert a dummy instruction at the
102 // beginning of the function that we will pretend "defines" the values. This
103 // is to make the interval analysis simpler by providing a number.
104 if (fn.livein_begin() != fn.livein_end()) {
105 unsigned FirstLiveIn = fn.livein_begin()->first;
107 // Find a reg class that contains this live in.
108 const TargetRegisterClass *RC = 0;
109 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
110 E = mri_->regclass_end(); RCI != E; ++RCI)
111 if ((*RCI)->contains(FirstLiveIn)) {
116 MachineInstr *OldFirstMI = fn.begin()->begin();
117 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
118 FirstLiveIn, FirstLiveIn, RC);
119 assert(OldFirstMI != fn.begin()->begin() &&
120 "copyRetToReg didn't insert anything!");
123 // number MachineInstrs
124 unsigned miIndex = 0;
125 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
126 mbb != mbbEnd; ++mbb)
127 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
129 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
130 assert(inserted && "multiple MachineInstr -> index mappings");
131 i2miMap_.push_back(mi);
132 miIndex += InstrSlots::NUM;
135 // Note intervals due to live-in values.
136 if (fn.livein_begin() != fn.livein_end()) {
137 MachineBasicBlock *Entry = fn.begin();
138 for (MachineFunction::livein_iterator I = fn.livein_begin(),
139 E = fn.livein_end(); I != E; ++I) {
140 handlePhysicalRegisterDef(Entry, Entry->begin(),
141 getOrCreateInterval(I->first), true);
142 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
143 handlePhysicalRegisterDef(Entry, Entry->begin(),
144 getOrCreateInterval(*AS), true);
150 numIntervals += getNumIntervals();
152 DEBUG(std::cerr << "********** INTERVALS **********\n";
153 for (iterator I = begin(), E = end(); I != E; ++I) {
154 I->second.print(std::cerr, mri_);
158 // join intervals if requested
159 if (EnableJoining) joinIntervals();
161 numIntervalsAfter += getNumIntervals();
163 // perform a final pass over the instructions and compute spill
164 // weights, coalesce virtual registers and remove identity moves
165 const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
167 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
168 mbbi != mbbe; ++mbbi) {
169 MachineBasicBlock* mbb = mbbi;
170 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
172 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
174 // if the move will be an identity move delete it
175 unsigned srcReg, dstReg, RegRep;
176 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
177 (RegRep = rep(srcReg)) == rep(dstReg)) {
178 // remove from def list
179 LiveInterval &interval = getOrCreateInterval(RegRep);
180 RemoveMachineInstrFromMaps(mii);
181 mii = mbbi->erase(mii);
185 for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
186 const MachineOperand& mop = mii->getOperand(i);
187 if (mop.isRegister() && mop.getReg() &&
188 MRegisterInfo::isVirtualRegister(mop.getReg())) {
189 // replace register with representative register
190 unsigned reg = rep(mop.getReg());
191 mii->getOperand(i).setReg(reg);
193 LiveInterval &RegInt = getInterval(reg);
195 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
203 for (iterator I = begin(), E = end(); I != E; ++I) {
204 LiveInterval &li = I->second;
205 if (MRegisterInfo::isVirtualRegister(li.reg)) {
206 // If the live interval length is essentially zero, i.e. in every live
207 // range the use follows def immediately, it doesn't make sense to spill
208 // it and hope it will be easier to allocate for this li.
209 if (isZeroLengthInterval(&li))
210 li.weight = float(HUGE_VAL);
218 /// print - Implement the dump method.
219 void LiveIntervals::print(std::ostream &O, const Module* ) const {
220 O << "********** INTERVALS **********\n";
221 for (const_iterator I = begin(), E = end(); I != E; ++I) {
222 I->second.print(std::cerr, mri_);
226 O << "********** MACHINEINSTRS **********\n";
227 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
228 mbbi != mbbe; ++mbbi) {
229 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
230 for (MachineBasicBlock::iterator mii = mbbi->begin(),
231 mie = mbbi->end(); mii != mie; ++mii) {
232 O << getInstructionIndex(mii) << '\t' << *mii;
237 std::vector<LiveInterval*> LiveIntervals::
238 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
239 // since this is called after the analysis is done we don't know if
240 // LiveVariables is available
241 lv_ = getAnalysisToUpdate<LiveVariables>();
243 std::vector<LiveInterval*> added;
245 assert(li.weight != HUGE_VAL &&
246 "attempt to spill already spilled interval!");
248 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: ";
249 li.print(std::cerr, mri_); std::cerr << '\n');
251 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
253 for (LiveInterval::Ranges::const_iterator
254 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
255 unsigned index = getBaseIndex(i->start);
256 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
257 for (; index != end; index += InstrSlots::NUM) {
258 // skip deleted instructions
259 while (index != end && !getInstructionFromIndex(index))
260 index += InstrSlots::NUM;
261 if (index == end) break;
263 MachineInstr *MI = getInstructionFromIndex(index);
265 // NewRegLiveIn - This instruction might have multiple uses of the spilled
266 // register. In this case, for the first use, keep track of the new vreg
267 // that we reload it into. If we see a second use, reuse this vreg
268 // instead of creating live ranges for two reloads.
269 unsigned NewRegLiveIn = 0;
272 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
273 MachineOperand& mop = MI->getOperand(i);
274 if (mop.isRegister() && mop.getReg() == li.reg) {
275 if (NewRegLiveIn && mop.isUse()) {
276 // We already emitted a reload of this value, reuse it for
277 // subsequent operands.
278 MI->getOperand(i).setReg(NewRegLiveIn);
279 DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
280 << " for operand #" << i << '\n');
281 } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
282 // Attempt to fold the memory reference into the instruction. If we
283 // can do this, we don't need to insert spill code.
285 lv_->instructionChanged(MI, fmi);
286 MachineBasicBlock &MBB = *MI->getParent();
287 vrm.virtFolded(li.reg, MI, i, fmi);
289 i2miMap_[index/InstrSlots::NUM] = fmi;
290 mi2iMap_[fmi] = index;
291 MI = MBB.insert(MBB.erase(MI), fmi);
293 // Folding the load/store can completely change the instruction in
294 // unpredictable ways, rescan it from the beginning.
297 // This is tricky. We need to add information in the interval about
298 // the spill code so we have to use our extra load/store slots.
300 // If we have a use we are going to have a load so we start the
301 // interval from the load slot onwards. Otherwise we start from the
303 unsigned start = (mop.isUse() ?
304 getLoadIndex(index) :
306 // If we have a def we are going to have a store right after it so
307 // we end the interval after the use of the next
308 // instruction. Otherwise we end after the use of this instruction.
309 unsigned end = 1 + (mop.isDef() ?
310 getStoreIndex(index) :
313 // create a new register for this spill
314 NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
315 MI->getOperand(i).setReg(NewRegLiveIn);
317 vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
318 LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
321 // the spill weight is now infinity as it
322 // cannot be spilled again
323 nI.weight = float(HUGE_VAL);
324 LiveRange LR(start, end, nI.getNextValue(~0U));
325 DEBUG(std::cerr << " +" << LR);
327 added.push_back(&nI);
329 // update live variables if it is available
331 lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
333 // If this is a live in, reuse it for subsequent live-ins. If it's
334 // a def, we can't do this.
335 if (!mop.isUse()) NewRegLiveIn = 0;
337 DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
338 nI.print(std::cerr, mri_); std::cerr << '\n');
348 void LiveIntervals::printRegName(unsigned reg) const {
349 if (MRegisterInfo::isPhysicalRegister(reg))
350 std::cerr << mri_->getName(reg);
352 std::cerr << "%reg" << reg;
355 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
356 MachineBasicBlock::iterator mi,
357 LiveInterval &interval) {
358 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
359 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
361 // Virtual registers may be defined multiple times (due to phi
362 // elimination and 2-addr elimination). Much of what we do only has to be
363 // done once for the vreg. We use an empty interval to detect the first
364 // time we see a vreg.
365 if (interval.empty()) {
366 // Get the Idx of the defining instructions.
367 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
369 unsigned ValNum = interval.getNextValue(defIndex);
370 assert(ValNum == 0 && "First value in interval is not 0?");
371 ValNum = 0; // Clue in the optimizer.
373 // Loop over all of the blocks that the vreg is defined in. There are
374 // two cases we have to handle here. The most common case is a vreg
375 // whose lifetime is contained within a basic block. In this case there
376 // will be a single kill, in MBB, which comes after the definition.
377 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
378 // FIXME: what about dead vars?
380 if (vi.Kills[0] != mi)
381 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
383 killIdx = defIndex+1;
385 // If the kill happens after the definition, we have an intra-block
387 if (killIdx > defIndex) {
388 assert(vi.AliveBlocks.empty() &&
389 "Shouldn't be alive across any blocks!");
390 LiveRange LR(defIndex, killIdx, ValNum);
391 interval.addRange(LR);
392 DEBUG(std::cerr << " +" << LR << "\n");
397 // The other case we handle is when a virtual register lives to the end
398 // of the defining block, potentially live across some blocks, then is
399 // live into some number of blocks, but gets killed. Start by adding a
400 // range that goes from this definition to the end of the defining block.
401 LiveRange NewLR(defIndex,
402 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
404 DEBUG(std::cerr << " +" << NewLR);
405 interval.addRange(NewLR);
407 // Iterate over all of the blocks that the variable is completely
408 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
410 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
411 if (vi.AliveBlocks[i]) {
412 MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
414 LiveRange LR(getInstructionIndex(&mbb->front()),
415 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
417 interval.addRange(LR);
418 DEBUG(std::cerr << " +" << LR);
423 // Finally, this virtual register is live from the start of any killing
424 // block to the 'use' slot of the killing instruction.
425 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
426 MachineInstr *Kill = vi.Kills[i];
427 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
428 getUseIndex(getInstructionIndex(Kill))+1,
430 interval.addRange(LR);
431 DEBUG(std::cerr << " +" << LR);
435 // If this is the second time we see a virtual register definition, it
436 // must be due to phi elimination or two addr elimination. If this is
437 // the result of two address elimination, then the vreg is the first
438 // operand, and is a def-and-use.
439 if (mi->getOperand(0).isRegister() &&
440 mi->getOperand(0).getReg() == interval.reg &&
441 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
442 // If this is a two-address definition, then we have already processed
443 // the live range. The only problem is that we didn't realize there
444 // are actually two values in the live interval. Because of this we
445 // need to take the LiveRegion that defines this register and split it
447 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
448 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
450 // Delete the initial value, which should be short and continuous,
451 // because the 2-addr copy must be in the same MBB as the redef.
452 interval.removeRange(DefIndex, RedefIndex);
454 // Two-address vregs should always only be redefined once. This means
455 // that at this point, there should be exactly one value number in it.
456 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
458 // The new value number is defined by the instruction we claimed defined
460 unsigned ValNo = interval.getNextValue(DefIndex);
462 // Value#1 is now defined by the 2-addr instruction.
463 interval.setInstDefiningValNum(0, RedefIndex);
465 // Add the new live interval which replaces the range for the input copy.
466 LiveRange LR(DefIndex, RedefIndex, ValNo);
467 DEBUG(std::cerr << " replace range with " << LR);
468 interval.addRange(LR);
470 // If this redefinition is dead, we need to add a dummy unit live
471 // range covering the def slot.
472 if (lv_->RegisterDefIsDead(mi, interval.reg))
473 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
475 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
478 // Otherwise, this must be because of phi elimination. If this is the
479 // first redefinition of the vreg that we have seen, go back and change
480 // the live range in the PHI block to be a different value number.
481 if (interval.containsOneValue()) {
482 assert(vi.Kills.size() == 1 &&
483 "PHI elimination vreg should have one kill, the PHI itself!");
485 // Remove the old range that we now know has an incorrect number.
486 MachineInstr *Killer = vi.Kills[0];
487 unsigned Start = getInstructionIndex(Killer->getParent()->begin());
488 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
489 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: ";
490 interval.print(std::cerr, mri_); std::cerr << "\n");
491 interval.removeRange(Start, End);
492 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
494 // Replace the interval with one of a NEW value number. Note that this
495 // value number isn't actually defined by an instruction, weird huh? :)
496 LiveRange LR(Start, End, interval.getNextValue(~0U));
497 DEBUG(std::cerr << " replace range with " << LR);
498 interval.addRange(LR);
499 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
502 // In the case of PHI elimination, each variable definition is only
503 // live until the end of the block. We've already taken care of the
504 // rest of the live range.
505 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
506 LiveRange LR(defIndex,
507 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
508 interval.getNextValue(defIndex));
509 interval.addRange(LR);
510 DEBUG(std::cerr << " +" << LR);
514 DEBUG(std::cerr << '\n');
517 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
518 MachineBasicBlock::iterator mi,
519 LiveInterval& interval,
521 // A physical register cannot be live across basic block, so its
522 // lifetime must end somewhere in its defining basic block.
523 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
524 typedef LiveVariables::killed_iterator KillIter;
526 unsigned baseIndex = getInstructionIndex(mi);
527 unsigned start = getDefIndex(baseIndex);
528 unsigned end = start;
530 // If it is not used after definition, it is considered dead at
531 // the instruction defining it. Hence its interval is:
532 // [defSlot(def), defSlot(def)+1)
533 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
534 DEBUG(std::cerr << " dead");
535 end = getDefIndex(start) + 1;
539 // If it is not dead on definition, it must be killed by a
540 // subsequent instruction. Hence its interval is:
541 // [defSlot(def), useSlot(kill)+1)
542 while (++mi != MBB->end()) {
543 baseIndex += InstrSlots::NUM;
544 if (lv_->KillsRegister(mi, interval.reg)) {
545 DEBUG(std::cerr << " killed");
546 end = getUseIndex(baseIndex) + 1;
551 // The only case we should have a dead physreg here without a killing or
552 // instruction where we know it's dead is if it is live-in to the function
554 assert(isLiveIn && "physreg was not killed in defining block!");
555 end = getDefIndex(start) + 1; // It's dead.
558 assert(start < end && "did not find end of interval?");
560 LiveRange LR(start, end, interval.getNextValue(isLiveIn ? ~0U : start));
561 interval.addRange(LR);
562 DEBUG(std::cerr << " +" << LR << '\n');
565 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
566 MachineBasicBlock::iterator MI,
568 if (MRegisterInfo::isVirtualRegister(reg))
569 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
570 else if (allocatableRegs_[reg]) {
571 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
572 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
573 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
577 /// computeIntervals - computes the live intervals for virtual
578 /// registers. for some ordering of the machine instructions [1,N] a
579 /// live interval is an interval [i, j) where 1 <= i <= j < N for
580 /// which a variable is live
581 void LiveIntervals::computeIntervals() {
582 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
583 DEBUG(std::cerr << "********** Function: "
584 << ((Value*)mf_->getFunction())->getName() << '\n');
585 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
587 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
589 MachineBasicBlock* mbb = I;
590 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
592 MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
593 if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; }
594 for (; mi != miEnd; ++mi) {
595 const TargetInstrDescriptor& tid =
596 tm_->getInstrInfo()->get(mi->getOpcode());
597 DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
599 // handle implicit defs
600 if (tid.ImplicitDefs) {
601 for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
602 handleRegisterDef(mbb, mi, *id);
605 // handle explicit defs
606 for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
607 MachineOperand& mop = mi->getOperand(i);
608 // handle register defs - build intervals
609 if (mop.isRegister() && mop.getReg() && mop.isDef())
610 handleRegisterDef(mbb, mi, mop.getReg());
616 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
617 /// being the source and IntB being the dest, thus this defines a value number
618 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
619 /// see if we can merge these two pieces of B into a single value number,
620 /// eliminating a copy. For example:
624 /// B1 = A3 <- this copy
626 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
627 /// value number to be replaced with B0 (which simplifies the B liveinterval).
629 /// This returns true if an interval was modified.
631 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
632 MachineInstr *CopyMI,
634 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
635 // the example above.
636 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
637 unsigned BValNo = BLR->ValId;
639 // Get the location that B is defined at. Two options: either this value has
640 // an unknown definition point or it is defined at CopyIdx. If unknown, we
642 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
643 if (BValNoDefIdx == ~0U) return false;
644 assert(BValNoDefIdx == CopyIdx &&
645 "Copy doesn't define the value?");
647 // AValNo is the value number in A that defines the copy, A0 in the example.
648 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
649 unsigned AValNo = AValLR->ValId;
651 // If AValNo is defined as a copy from IntB, we can potentially process this.
653 // Get the instruction that defines this value number.
654 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
656 // If it's unknown, ignore it.
657 if (AValNoInstIdx == ~0U || AValNoInstIdx == ~1U) return false;
658 // Otherwise, get the instruction for it.
659 MachineInstr *AValNoInstMI = getInstructionFromIndex(AValNoInstIdx);
661 // If the value number is not defined by a copy instruction, ignore it.
662 unsigned SrcReg, DstReg;
663 if (!tii_->isMoveInstr(*AValNoInstMI, SrcReg, DstReg))
666 // If the source register comes from an interval other than IntB, we can't
668 assert(rep(DstReg) == IntA.reg && "Not defining a reg in IntA?");
669 if (rep(SrcReg) != IntB.reg) return false;
671 // Get the LiveRange in IntB that this value number starts with.
672 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
674 // Make sure that the end of the live range is inside the same block as
676 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
678 ValLREndInst->getParent() != CopyMI->getParent()) return false;
680 // Okay, we now know that ValLR ends in the same block that the CopyMI
681 // live-range starts. If there are no intervening live ranges between them in
682 // IntB, we can merge them.
683 if (ValLR+1 != BLR) return false;
685 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_));
687 // Okay, we can merge them. We need to insert a new liverange:
688 // [ValLR.end, BLR.begin) of either value number, then we merge the
689 // two value numbers.
690 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
691 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
693 // If the IntB live range is assigned to a physical register, and if that
694 // physreg has aliases,
695 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
696 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
697 LiveInterval &AliasLI = getInterval(*AS);
698 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
699 AliasLI.getNextValue(~0U)));
703 // Okay, merge "B1" into the same value number as "B0".
704 if (BValNo != ValLR->ValId)
705 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
706 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_);
709 // Finally, delete the copy instruction.
710 RemoveMachineInstrFromMaps(CopyMI);
711 CopyMI->eraseFromParent();
717 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
718 /// which are the src/dst of the copy instruction CopyMI. This returns true
719 /// if the copy was successfully coallesced away, or if it is never possible
720 /// to coallesce these this copy, due to register constraints. It returns
721 /// false if it is not currently possible to coallesce this interval, but
722 /// it may be possible if other things get coallesced.
723 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
724 unsigned SrcReg, unsigned DstReg) {
727 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI);
729 // Get representative registers.
730 SrcReg = rep(SrcReg);
731 DstReg = rep(DstReg);
733 // If they are already joined we continue.
734 if (SrcReg == DstReg) {
735 DEBUG(std::cerr << "\tCopy already coallesced.\n");
736 return true; // Not coallescable.
739 // If they are both physical registers, we cannot join them.
740 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
741 MRegisterInfo::isPhysicalRegister(DstReg)) {
742 DEBUG(std::cerr << "\tCan not coallesce physregs.\n");
743 return true; // Not coallescable.
746 // We only join virtual registers with allocatable physical registers.
747 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
748 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n");
749 return true; // Not coallescable.
751 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
752 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n");
753 return true; // Not coallescable.
756 // If they are not of the same register class, we cannot join them.
757 if (differingRegisterClasses(SrcReg, DstReg)) {
758 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n");
759 return true; // Not coallescable.
762 LiveInterval &SrcInt = getInterval(SrcReg);
763 LiveInterval &DestInt = getInterval(DstReg);
764 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
765 "Register mapping is horribly broken!");
767 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
768 std::cerr << " and "; DestInt.print(std::cerr, mri_);
771 // If two intervals contain a single value and are joined by a copy, it
772 // does not matter if the intervals overlap, they can always be joined.
774 bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
776 unsigned MIDefIdx = getDefIndex(getInstructionIndex(CopyMI));
778 // If the intervals think that this is joinable, do so now.
779 if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
782 // If DestInt is actually a copy from SrcInt (which we know) that is used
783 // to define another value of SrcInt, we can change the other range of
784 // SrcInt to be the value of the range that defines DestInt, simplying the
785 // interval an promoting coallescing.
786 if (!Joinable && AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI, MIDefIdx))
790 DEBUG(std::cerr << "Interference!\n");
794 // Okay, we can join these two intervals. If one of the intervals being
795 // joined is a physreg, this method always canonicalizes DestInt to be it.
796 // The output "SrcInt" will not have been modified.
797 DestInt.join(SrcInt, MIDefIdx);
799 bool Swapped = SrcReg == DestInt.reg;
801 std::swap(SrcReg, DstReg);
802 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
803 "LiveInterval::join didn't work right!");
805 // If we're about to merge live ranges into a physical register live range,
806 // we have to update any aliased register's live ranges to indicate that they
807 // have clobbered values for this range.
808 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
809 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
810 getInterval(*AS).MergeInClobberRanges(SrcInt);
813 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_);
816 // If the intervals were swapped by Join, swap them back so that the register
817 // mapping (in the r2i map) is correct.
818 if (Swapped) SrcInt.swap(DestInt);
819 r2iMap_.erase(SrcReg);
820 r2rMap_[SrcReg] = DstReg;
829 // DepthMBBCompare - Comparison predicate that sort first based on the loop
830 // depth of the basic block (the unsigned), and then on the MBB number.
831 struct DepthMBBCompare {
832 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
833 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
834 if (LHS.first > RHS.first) return true; // Deeper loops first
835 return LHS.first == RHS.first &&
836 LHS.second->getNumber() < RHS.second->getNumber();
842 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
843 std::vector<CopyRec> &TryAgain) {
844 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
846 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
848 MachineInstr *Inst = MII++;
850 // If this isn't a copy, we can't join intervals.
851 unsigned SrcReg, DstReg;
852 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
854 if (!JoinCopy(Inst, SrcReg, DstReg))
855 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
860 void LiveIntervals::joinIntervals() {
861 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
863 std::vector<CopyRec> TryAgainList;
865 const LoopInfo &LI = getAnalysis<LoopInfo>();
866 if (LI.begin() == LI.end()) {
867 // If there are no loops in the function, join intervals in function order.
868 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
870 CopyCoallesceInMBB(I, TryAgainList);
872 // Otherwise, join intervals in inner loops before other intervals.
873 // Unfortunately we can't just iterate over loop hierarchy here because
874 // there may be more MBB's than BB's. Collect MBB's for sorting.
875 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
876 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
878 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
880 // Sort by loop depth.
881 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
883 // Finally, join intervals in loop nest order.
884 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
885 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
888 // Joining intervals can allow other intervals to be joined. Iteratively join
889 // until we make no progress.
890 bool ProgressMade = true;
891 while (ProgressMade) {
892 ProgressMade = false;
894 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
895 CopyRec &TheCopy = TryAgainList[i];
897 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
898 TheCopy.MI = 0; // Mark this one as done.
904 DEBUG(std::cerr << "*** Register mapping ***\n");
905 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
907 std::cerr << " reg " << i << " -> ";
908 printRegName(r2rMap_[i]);
913 /// Return true if the two specified registers belong to different register
914 /// classes. The registers may be either phys or virt regs.
915 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
916 unsigned RegB) const {
918 // Get the register classes for the first reg.
919 if (MRegisterInfo::isPhysicalRegister(RegA)) {
920 assert(MRegisterInfo::isVirtualRegister(RegB) &&
921 "Shouldn't consider two physregs!");
922 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
925 // Compare against the regclass for the second reg.
926 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
927 if (MRegisterInfo::isVirtualRegister(RegB))
928 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
930 return !RegClass->contains(RegB);
933 LiveInterval LiveIntervals::createInterval(unsigned reg) {
934 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
935 (float)HUGE_VAL : 0.0F;
936 return LiveInterval(reg, Weight);