1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "LiveRangeCalc.h"
37 #include "VirtRegMap.h"
43 // Switch to the new experimental algorithm for computing live intervals.
45 NewLiveIntervals("new-live-intervals", cl::Hidden,
46 cl::desc("Use new algorithm forcomputing live intervals"));
48 char LiveIntervals::ID = 0;
49 char &llvm::LiveIntervalsID = LiveIntervals::ID;
50 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
51 "Live Interval Analysis", false, false)
52 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
53 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
54 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
55 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
56 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
57 "Live Interval Analysis", false, false)
59 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<AliasAnalysis>();
62 AU.addPreserved<AliasAnalysis>();
63 AU.addRequired<LiveVariables>();
64 AU.addPreserved<LiveVariables>();
65 AU.addPreservedID(MachineLoopInfoID);
66 AU.addRequiredTransitiveID(MachineDominatorsID);
67 AU.addPreservedID(MachineDominatorsID);
68 AU.addPreserved<SlotIndexes>();
69 AU.addRequiredTransitive<SlotIndexes>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
74 DomTree(0), LRCalc(0) {
75 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
78 LiveIntervals::~LiveIntervals() {
82 void LiveIntervals::releaseMemory() {
83 // Free the live intervals themselves.
84 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
85 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
86 VirtRegIntervals.clear();
89 RegMaskBlocks.clear();
91 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
92 delete RegUnitIntervals[i];
93 RegUnitIntervals.clear();
95 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
96 VNInfoAllocator.Reset();
99 /// runOnMachineFunction - Register allocate the whole function
101 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
103 MRI = &MF->getRegInfo();
104 TM = &fn.getTarget();
105 TRI = TM->getRegisterInfo();
106 TII = TM->getInstrInfo();
107 AA = &getAnalysis<AliasAnalysis>();
108 LV = &getAnalysis<LiveVariables>();
109 Indexes = &getAnalysis<SlotIndexes>();
110 DomTree = &getAnalysis<MachineDominatorTree>();
112 LRCalc = new LiveRangeCalc();
113 AllocatableRegs = TRI->getAllocatableSet(fn);
114 ReservedRegs = TRI->getReservedRegs(fn);
116 // Allocate space for all virtual registers.
117 VirtRegIntervals.resize(MRI->getNumVirtRegs());
119 if (NewLiveIntervals) {
120 // This is the new way of computing live intervals.
121 // It is independent of LiveVariables, and it can run at any time.
125 // This is the old way of computing live intervals.
126 // It depends on LiveVariables.
129 computeLiveInRegUnits();
135 /// print - Implement the dump method.
136 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
137 OS << "********** INTERVALS **********\n";
139 // Dump the regunits.
140 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
141 if (LiveInterval *LI = RegUnitIntervals[i])
142 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
144 // Dump the virtregs.
145 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
146 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
147 if (hasInterval(Reg))
148 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
154 void LiveIntervals::printInstrs(raw_ostream &OS) const {
155 OS << "********** MACHINEINSTRS **********\n";
156 MF->print(OS, Indexes);
159 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
160 void LiveIntervals::dumpInstrs() const {
166 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
167 unsigned Reg = MI.getOperand(MOIdx).getReg();
168 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
169 const MachineOperand &MO = MI.getOperand(i);
172 if (MO.getReg() == Reg && MO.isDef()) {
173 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
174 MI.getOperand(MOIdx).getSubReg() &&
175 (MO.getSubReg() || MO.isImplicit()));
182 /// isPartialRedef - Return true if the specified def at the specific index is
183 /// partially re-defining the specified live interval. A common case of this is
184 /// a definition of the sub-register.
185 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
186 LiveInterval &interval) {
187 if (!MO.getSubReg() || MO.isEarlyClobber())
190 SlotIndex RedefIndex = MIIdx.getRegSlot();
191 const LiveRange *OldLR =
192 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
193 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
195 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
200 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
201 MachineBasicBlock::iterator mi,
205 LiveInterval &interval) {
206 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
208 // Virtual registers may be defined multiple times (due to phi
209 // elimination and 2-addr elimination). Much of what we do only has to be
210 // done once for the vreg. We use an empty interval to detect the first
211 // time we see a vreg.
212 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
213 if (interval.empty()) {
214 // Get the Idx of the defining instructions.
215 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
217 // Make sure the first definition is not a partial redefinition.
218 assert(!MO.readsReg() && "First def cannot also read virtual register "
219 "missing <undef> flag?");
221 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
222 assert(ValNo->id == 0 && "First value in interval is not 0?");
224 // Loop over all of the blocks that the vreg is defined in. There are
225 // two cases we have to handle here. The most common case is a vreg
226 // whose lifetime is contained within a basic block. In this case there
227 // will be a single kill, in MBB, which comes after the definition.
228 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
229 // FIXME: what about dead vars?
231 if (vi.Kills[0] != mi)
232 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
234 killIdx = defIndex.getDeadSlot();
236 // If the kill happens after the definition, we have an intra-block
238 if (killIdx > defIndex) {
239 assert(vi.AliveBlocks.empty() &&
240 "Shouldn't be alive across any blocks!");
241 LiveRange LR(defIndex, killIdx, ValNo);
242 interval.addRange(LR);
243 DEBUG(dbgs() << " +" << LR << "\n");
248 // The other case we handle is when a virtual register lives to the end
249 // of the defining block, potentially live across some blocks, then is
250 // live into some number of blocks, but gets killed. Start by adding a
251 // range that goes from this definition to the end of the defining block.
252 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
253 DEBUG(dbgs() << " +" << NewLR);
254 interval.addRange(NewLR);
256 bool PHIJoin = LV->isPHIJoin(interval.reg);
259 // A phi join register is killed at the end of the MBB and revived as a
260 // new valno in the killing blocks.
261 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
262 DEBUG(dbgs() << " phi-join");
264 // Iterate over all of the blocks that the variable is completely
265 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
267 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
268 E = vi.AliveBlocks.end(); I != E; ++I) {
269 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
270 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
272 interval.addRange(LR);
273 DEBUG(dbgs() << " +" << LR);
277 // Finally, this virtual register is live from the start of any killing
278 // block to the 'use' slot of the killing instruction.
279 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
280 MachineInstr *Kill = vi.Kills[i];
281 SlotIndex Start = getMBBStartIdx(Kill->getParent());
282 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
284 // Create interval with one of a NEW value number. Note that this value
285 // number isn't actually defined by an instruction, weird huh? :)
287 assert(getInstructionFromIndex(Start) == 0 &&
288 "PHI def index points at actual instruction.");
289 ValNo = interval.getNextValue(Start, VNInfoAllocator);
291 LiveRange LR(Start, killIdx, ValNo);
292 interval.addRange(LR);
293 DEBUG(dbgs() << " +" << LR);
297 if (MultipleDefsBySameMI(*mi, MOIdx))
298 // Multiple defs of the same virtual register by the same instruction.
299 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
300 // This is likely due to elimination of REG_SEQUENCE instructions. Return
301 // here since there is nothing to do.
304 // If this is the second time we see a virtual register definition, it
305 // must be due to phi elimination or two addr elimination. If this is
306 // the result of two address elimination, then the vreg is one of the
307 // def-and-use register operand.
309 // It may also be partial redef like this:
310 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
311 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
312 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
313 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
314 // If this is a two-address definition, then we have already processed
315 // the live range. The only problem is that we didn't realize there
316 // are actually two values in the live interval. Because of this we
317 // need to take the LiveRegion that defines this register and split it
319 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
321 const LiveRange *OldLR =
322 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
323 VNInfo *OldValNo = OldLR->valno;
324 SlotIndex DefIndex = OldValNo->def.getRegSlot();
326 // Delete the previous value, which should be short and continuous,
327 // because the 2-addr copy must be in the same MBB as the redef.
328 interval.removeRange(DefIndex, RedefIndex);
330 // The new value number (#1) is defined by the instruction we claimed
332 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
334 // Value#0 is now defined by the 2-addr instruction.
335 OldValNo->def = RedefIndex;
337 // Add the new live interval which replaces the range for the input copy.
338 LiveRange LR(DefIndex, RedefIndex, ValNo);
339 DEBUG(dbgs() << " replace range with " << LR);
340 interval.addRange(LR);
342 // If this redefinition is dead, we need to add a dummy unit live
343 // range covering the def slot.
345 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
348 DEBUG(dbgs() << " RESULT: " << interval);
349 } else if (LV->isPHIJoin(interval.reg)) {
350 // In the case of PHI elimination, each variable definition is only
351 // live until the end of the block. We've already taken care of the
352 // rest of the live range.
354 SlotIndex defIndex = MIIdx.getRegSlot();
355 if (MO.isEarlyClobber())
356 defIndex = MIIdx.getRegSlot(true);
358 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
360 SlotIndex killIndex = getMBBEndIdx(mbb);
361 LiveRange LR(defIndex, killIndex, ValNo);
362 interval.addRange(LR);
363 DEBUG(dbgs() << " phi-join +" << LR);
365 llvm_unreachable("Multiply defined register");
369 DEBUG(dbgs() << '\n');
372 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
373 MachineBasicBlock::iterator MI,
377 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
378 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
379 getOrCreateInterval(MO.getReg()));
382 /// computeIntervals - computes the live intervals for virtual
383 /// registers. for some ordering of the machine instructions [1,N] a
384 /// live interval is an interval [i, j) where 1 <= i <= j < N for
385 /// which a variable is live
386 void LiveIntervals::computeIntervals() {
387 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
388 << "********** Function: " << MF->getName() << '\n');
390 RegMaskBlocks.resize(MF->getNumBlockIDs());
392 SmallVector<unsigned, 8> UndefUses;
393 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
395 MachineBasicBlock *MBB = MBBI;
396 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
401 // Track the index of the current machine instr.
402 SlotIndex MIIndex = getMBBStartIdx(MBB);
403 DEBUG(dbgs() << "BB#" << MBB->getNumber()
404 << ":\t\t# derived from " << MBB->getName() << "\n");
406 // Skip over empty initial indices.
407 if (getInstructionFromIndex(MIIndex) == 0)
408 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
410 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
412 DEBUG(dbgs() << MIIndex << "\t" << *MI);
413 if (MI->isDebugValue())
415 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
416 "Lost SlotIndex synchronization");
419 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
420 MachineOperand &MO = MI->getOperand(i);
422 // Collect register masks.
423 if (MO.isRegMask()) {
424 RegMaskSlots.push_back(MIIndex.getRegSlot());
425 RegMaskBits.push_back(MO.getRegMask());
429 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
432 // handle register defs - build intervals
434 handleRegisterDef(MBB, MI, MIIndex, MO, i);
435 else if (MO.isUndef())
436 UndefUses.push_back(MO.getReg());
439 // Move to the next instr slot.
440 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
443 // Compute the number of register mask instructions in this block.
444 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
445 RMB.second = RegMaskSlots.size() - RMB.first;
448 // Create empty intervals for registers defined by implicit_def's (except
449 // for those implicit_def that define values which are liveout of their
451 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
452 unsigned UndefReg = UndefUses[i];
453 (void)getOrCreateInterval(UndefReg);
457 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
458 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
459 return new LiveInterval(reg, Weight);
463 /// computeVirtRegInterval - Compute the live interval of a virtual register,
464 /// based on defs and uses.
465 void LiveIntervals::computeVirtRegInterval(LiveInterval *LI) {
466 assert(LRCalc && "LRCalc not initialized.");
467 assert(LI->empty() && "Should only compute empty intervals.");
468 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
469 LRCalc->createDeadDefs(LI);
470 LRCalc->extendToUses(LI);
473 void LiveIntervals::computeVirtRegs() {
474 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
475 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
476 if (MRI->reg_nodbg_empty(Reg))
478 LiveInterval *LI = createInterval(Reg);
479 VirtRegIntervals[Reg] = LI;
480 computeVirtRegInterval(LI);
484 void LiveIntervals::computeRegMasks() {
485 RegMaskBlocks.resize(MF->getNumBlockIDs());
487 // Find all instructions with regmask operands.
488 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
490 MachineBasicBlock *MBB = MBBI;
491 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
492 RMB.first = RegMaskSlots.size();
493 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
495 for (MIOperands MO(MI); MO.isValid(); ++MO) {
496 if (!MO->isRegMask())
498 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
499 RegMaskBits.push_back(MO->getRegMask());
501 // Compute the number of register mask instructions in this block.
502 RMB.second = RegMaskSlots.size() - RMB.first;
506 //===----------------------------------------------------------------------===//
507 // Register Unit Liveness
508 //===----------------------------------------------------------------------===//
510 // Fixed interference typically comes from ABI boundaries: Function arguments
511 // and return values are passed in fixed registers, and so are exception
512 // pointers entering landing pads. Certain instructions require values to be
513 // present in specific registers. That is also represented through fixed
517 /// computeRegUnitInterval - Compute the live interval of a register unit, based
518 /// on the uses and defs of aliasing registers. The interval should be empty,
519 /// or contain only dead phi-defs from ABI blocks.
520 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
521 unsigned Unit = LI->reg;
523 assert(LRCalc && "LRCalc not initialized.");
524 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
526 // The physregs aliasing Unit are the roots and their super-registers.
527 // Create all values as dead defs before extending to uses. Note that roots
528 // may share super-registers. That's OK because createDeadDefs() is
529 // idempotent. It is very rare for a register unit to have multiple roots, so
530 // uniquing super-registers is probably not worthwhile.
531 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
532 unsigned Root = *Roots;
533 if (!MRI->reg_empty(Root))
534 LRCalc->createDeadDefs(LI, Root);
535 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
536 if (!MRI->reg_empty(*Supers))
537 LRCalc->createDeadDefs(LI, *Supers);
541 // Now extend LI to reach all uses.
542 // Ignore uses of reserved registers. We only track defs of those.
543 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
544 unsigned Root = *Roots;
545 if (!isReserved(Root) && !MRI->reg_empty(Root))
546 LRCalc->extendToUses(LI, Root);
547 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
548 unsigned Reg = *Supers;
549 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
550 LRCalc->extendToUses(LI, Reg);
556 /// computeLiveInRegUnits - Precompute the live ranges of any register units
557 /// that are live-in to an ABI block somewhere. Register values can appear
558 /// without a corresponding def when entering the entry block or a landing pad.
560 void LiveIntervals::computeLiveInRegUnits() {
561 RegUnitIntervals.resize(TRI->getNumRegUnits());
562 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
564 // Keep track of the intervals allocated.
565 SmallVector<LiveInterval*, 8> NewIntvs;
567 // Check all basic blocks for live-ins.
568 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
570 const MachineBasicBlock *MBB = MFI;
572 // We only care about ABI blocks: Entry + landing pads.
573 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
576 // Create phi-defs at Begin for all live-in registers.
577 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
578 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
579 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
580 LIE = MBB->livein_end(); LII != LIE; ++LII) {
581 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
582 unsigned Unit = *Units;
583 LiveInterval *Intv = RegUnitIntervals[Unit];
585 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
586 NewIntvs.push_back(Intv);
588 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
590 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
593 DEBUG(dbgs() << '\n');
595 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
597 // Compute the 'normal' part of the intervals.
598 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
599 computeRegUnitInterval(NewIntvs[i]);
603 /// shrinkToUses - After removing some uses of a register, shrink its live
604 /// range to just the remaining uses. This method does not compute reaching
605 /// defs for new uses, and it doesn't remove dead defs.
606 bool LiveIntervals::shrinkToUses(LiveInterval *li,
607 SmallVectorImpl<MachineInstr*> *dead) {
608 DEBUG(dbgs() << "Shrink: " << *li << '\n');
609 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
610 && "Can only shrink virtual registers");
611 // Find all the values used, including PHI kills.
612 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
614 // Blocks that have already been added to WorkList as live-out.
615 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
617 // Visit all instructions reading li->reg.
618 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
619 MachineInstr *UseMI = I.skipInstruction();) {
620 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
622 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
623 LiveRangeQuery LRQ(*li, Idx);
624 VNInfo *VNI = LRQ.valueIn();
626 // This shouldn't happen: readsVirtualRegister returns true, but there is
627 // no live value. It is likely caused by a target getting <undef> flags
629 DEBUG(dbgs() << Idx << '\t' << *UseMI
630 << "Warning: Instr claims to read non-existent value in "
634 // Special case: An early-clobber tied operand reads and writes the
635 // register one slot early.
636 if (VNInfo *DefVNI = LRQ.valueDefined())
639 WorkList.push_back(std::make_pair(Idx, VNI));
642 // Create a new live interval with only minimal live segments per def.
643 LiveInterval NewLI(li->reg, 0);
644 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
649 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
652 // Keep track of the PHIs that are in use.
653 SmallPtrSet<VNInfo*, 8> UsedPHIs;
655 // Extend intervals to reach all uses in WorkList.
656 while (!WorkList.empty()) {
657 SlotIndex Idx = WorkList.back().first;
658 VNInfo *VNI = WorkList.back().second;
660 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
661 SlotIndex BlockStart = getMBBStartIdx(MBB);
663 // Extend the live range for VNI to be live at Idx.
664 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
666 assert(ExtVNI == VNI && "Unexpected existing value number");
667 // Is this a PHIDef we haven't seen before?
668 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
670 // The PHI is live, make sure the predecessors are live-out.
671 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
672 PE = MBB->pred_end(); PI != PE; ++PI) {
673 if (!LiveOut.insert(*PI))
675 SlotIndex Stop = getMBBEndIdx(*PI);
676 // A predecessor is not required to have a live-out value for a PHI.
677 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
678 WorkList.push_back(std::make_pair(Stop, PVNI));
683 // VNI is live-in to MBB.
684 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
685 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
687 // Make sure VNI is live-out from the predecessors.
688 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
689 PE = MBB->pred_end(); PI != PE; ++PI) {
690 if (!LiveOut.insert(*PI))
692 SlotIndex Stop = getMBBEndIdx(*PI);
693 assert(li->getVNInfoBefore(Stop) == VNI &&
694 "Wrong value out of predecessor");
695 WorkList.push_back(std::make_pair(Stop, VNI));
699 // Handle dead values.
700 bool CanSeparate = false;
701 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
706 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
707 assert(LII != NewLI.end() && "Missing live range for PHI");
708 if (LII->end != VNI->def.getDeadSlot())
710 if (VNI->isPHIDef()) {
711 // This is a dead PHI. Remove it.
713 NewLI.removeRange(*LII);
714 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
717 // This is a dead def. Make sure the instruction knows.
718 MachineInstr *MI = getInstructionFromIndex(VNI->def);
719 assert(MI && "No instruction defining live value");
720 MI->addRegisterDead(li->reg, TRI);
721 if (dead && MI->allDefsAreDead()) {
722 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
728 // Move the trimmed ranges back.
729 li->ranges.swap(NewLI.ranges);
730 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
734 void LiveIntervals::extendToIndices(LiveInterval *LI,
735 ArrayRef<SlotIndex> Indices) {
736 assert(LRCalc && "LRCalc not initialized.");
737 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
738 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
739 LRCalc->extend(LI, Indices[i]);
742 void LiveIntervals::pruneValue(LiveInterval *LI, SlotIndex Kill,
743 SmallVectorImpl<SlotIndex> *EndPoints) {
744 LiveRangeQuery LRQ(*LI, Kill);
745 VNInfo *VNI = LRQ.valueOut();
749 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
750 SlotIndex MBBStart, MBBEnd;
751 tie(MBBStart, MBBEnd) = Indexes->getMBBRange(KillMBB);
753 // If VNI isn't live out from KillMBB, the value is trivially pruned.
754 if (LRQ.endPoint() < MBBEnd) {
755 LI->removeRange(Kill, LRQ.endPoint());
756 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
760 // VNI is live out of KillMBB.
761 LI->removeRange(Kill, MBBEnd);
762 if (EndPoints) EndPoints->push_back(MBBEnd);
764 // Find all blocks that are reachable from KillMBB without leaving VNI's live
765 // range. It is possible that KillMBB itself is reachable, so start a DFS
766 // from each successor.
767 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
769 for (MachineBasicBlock::succ_iterator
770 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
771 SuccI != SuccE; ++SuccI) {
772 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
773 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
775 MachineBasicBlock *MBB = *I;
777 // Check if VNI is live in to MBB.
778 tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
779 LiveRangeQuery LRQ(*LI, MBBStart);
780 if (LRQ.valueIn() != VNI) {
781 // This block isn't part of the VNI live range. Prune the search.
786 // Prune the search if VNI is killed in MBB.
787 if (LRQ.endPoint() < MBBEnd) {
788 LI->removeRange(MBBStart, LRQ.endPoint());
789 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
794 // VNI is live through MBB.
795 LI->removeRange(MBBStart, MBBEnd);
796 if (EndPoints) EndPoints->push_back(MBBEnd);
802 //===----------------------------------------------------------------------===//
803 // Register allocator hooks.
806 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
807 // Keep track of regunit ranges.
808 SmallVector<std::pair<LiveInterval*, LiveInterval::iterator>, 8> RU;
810 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
811 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
812 if (MRI->reg_nodbg_empty(Reg))
814 LiveInterval *LI = &getInterval(Reg);
818 // Find the regunit intervals for the assigned register. They may overlap
819 // the virtual register live range, cancelling any kills.
821 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
823 LiveInterval *RUInt = &getRegUnit(*Units);
826 RU.push_back(std::make_pair(RUInt, RUInt->find(LI->begin()->end)));
829 // Every instruction that kills Reg corresponds to a live range end point.
830 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
832 // A block index indicates an MBB edge.
833 if (RI->end.isBlock())
835 MachineInstr *MI = getInstructionFromIndex(RI->end);
839 // Check if any of the reguints are live beyond the end of RI. That could
840 // happen when a physreg is defined as a copy of a virtreg:
842 // %EAX = COPY %vreg5
843 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
846 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
847 bool CancelKill = false;
848 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
849 LiveInterval *RInt = RU[u].first;
850 LiveInterval::iterator &I = RU[u].second;
851 if (I == RInt->end())
853 I = RInt->advanceTo(I, RI->end);
854 if (I == RInt->end() || I->start >= RI->end)
856 // I is overlapping RI.
861 MI->clearRegisterKills(Reg, NULL);
863 MI->addRegisterKilled(Reg, NULL);
869 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
870 // A local live range must be fully contained inside the block, meaning it is
871 // defined and killed at instructions, not at block boundaries. It is not
872 // live in or or out of any block.
874 // It is technically possible to have a PHI-defined live range identical to a
875 // single block, but we are going to return false in that case.
877 SlotIndex Start = LI.beginIndex();
881 SlotIndex Stop = LI.endIndex();
885 // getMBBFromIndex doesn't need to search the MBB table when both indexes
886 // belong to proper instructions.
887 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
888 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
889 return MBB1 == MBB2 ? MBB1 : NULL;
893 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
894 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
896 const VNInfo *PHI = *I;
897 if (PHI->isUnused() || !PHI->isPHIDef())
899 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
900 // Conservatively return true instead of scanning huge predecessor lists.
901 if (PHIMBB->pred_size() > 100)
903 for (MachineBasicBlock::const_pred_iterator
904 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
905 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
912 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
913 // Limit the loop depth ridiculousness.
917 // The loop depth is used to roughly estimate the number of times the
918 // instruction is executed. Something like 10^d is simple, but will quickly
919 // overflow a float. This expression behaves like 10^d for small d, but is
920 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
921 // headroom before overflow.
922 // By the way, powf() might be unavailable here. For consistency,
923 // We may take pow(double,double).
924 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
926 return (isDef + isUse) * lc;
929 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
930 MachineInstr* startInst) {
931 LiveInterval& Interval = getOrCreateInterval(reg);
932 VNInfo* VN = Interval.getNextValue(
933 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
934 getVNInfoAllocator());
936 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
937 getMBBEndIdx(startInst->getParent()), VN);
938 Interval.addRange(LR);
944 //===----------------------------------------------------------------------===//
945 // Register mask functions
946 //===----------------------------------------------------------------------===//
948 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
949 BitVector &UsableRegs) {
952 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
954 // Use a smaller arrays for local live ranges.
955 ArrayRef<SlotIndex> Slots;
956 ArrayRef<const uint32_t*> Bits;
957 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
958 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
959 Bits = getRegMaskBitsInBlock(MBB->getNumber());
961 Slots = getRegMaskSlots();
962 Bits = getRegMaskBits();
965 // We are going to enumerate all the register mask slots contained in LI.
966 // Start with a binary search of RegMaskSlots to find a starting point.
967 ArrayRef<SlotIndex>::iterator SlotI =
968 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
969 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
971 // No slots in range, LI begins after the last call.
977 assert(*SlotI >= LiveI->start);
978 // Loop over all slots overlapping this segment.
979 while (*SlotI < LiveI->end) {
980 // *SlotI overlaps LI. Collect mask bits.
982 // This is the first overlap. Initialize UsableRegs to all ones.
984 UsableRegs.resize(TRI->getNumRegs(), true);
987 // Remove usable registers clobbered by this mask.
988 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
989 if (++SlotI == SlotE)
992 // *SlotI is beyond the current LI segment.
993 LiveI = LI.advanceTo(LiveI, *SlotI);
996 // Advance SlotI until it overlaps.
997 while (*SlotI < LiveI->start)
998 if (++SlotI == SlotE)
1003 //===----------------------------------------------------------------------===//
1004 // IntervalUpdate class.
1005 //===----------------------------------------------------------------------===//
1007 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1008 class LiveIntervals::HMEditor {
1011 const MachineRegisterInfo& MRI;
1012 const TargetRegisterInfo& TRI;
1015 SmallPtrSet<LiveInterval*, 8> Updated;
1018 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1019 const TargetRegisterInfo& TRI,
1020 SlotIndex OldIdx, SlotIndex NewIdx)
1021 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx) {}
1023 /// Update all live ranges touched by MI, assuming a move from OldIdx to
1025 void updateAllRanges(MachineInstr *MI) {
1026 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
1027 bool hasRegMask = false;
1028 for (MIOperands MO(MI); MO.isValid(); ++MO) {
1029 if (MO->isRegMask())
1033 // Aggressively clear all kill flags.
1034 // They are reinserted by VirtRegRewriter.
1036 MO->setIsKill(false);
1038 unsigned Reg = MO->getReg();
1041 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1042 updateRange(LIS.getInterval(Reg));
1046 // For physregs, only update the regunits that actually have a
1047 // precomputed live range.
1048 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1049 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1053 updateRegMaskSlots();
1057 /// Update a single live range, assuming an instruction has been moved from
1058 /// OldIdx to NewIdx.
1059 void updateRange(LiveInterval &LI) {
1060 if (!Updated.insert(&LI))
1064 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
1065 dbgs() << PrintReg(LI.reg);
1067 dbgs() << PrintRegUnit(LI.reg, &TRI);
1068 dbgs() << ":\t" << LI << '\n';
1070 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
1074 DEBUG(dbgs() << " -->\t" << LI << '\n');
1078 /// Update LI to reflect an instruction has been moved downwards from OldIdx
1081 /// 1. Live def at OldIdx:
1082 /// Move def to NewIdx, assert endpoint after NewIdx.
1084 /// 2. Live def at OldIdx, killed at NewIdx:
1085 /// Change to dead def at NewIdx.
1086 /// (Happens when bundling def+kill together).
1088 /// 3. Dead def at OldIdx:
1089 /// Move def to NewIdx, possibly across another live value.
1091 /// 4. Def at OldIdx AND at NewIdx:
1092 /// Remove live range [OldIdx;NewIdx) and value defined at OldIdx.
1093 /// (Happens when bundling multiple defs together).
1095 /// 5. Value read at OldIdx, killed before NewIdx:
1096 /// Extend kill to NewIdx.
1098 void handleMoveDown(LiveInterval &LI) {
1099 // First look for a kill at OldIdx.
1100 LiveInterval::iterator I = LI.find(OldIdx.getBaseIndex());
1101 LiveInterval::iterator E = LI.end();
1102 // Is LI even live at OldIdx?
1103 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1106 // Handle a live-in value.
1107 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1108 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1109 // If the live-in value already extends to NewIdx, there is nothing to do.
1110 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1112 // Aggressively remove all kill flags from the old kill point.
1113 // Kill flags shouldn't be used while live intervals exist, they will be
1114 // reinserted by VirtRegRewriter.
1115 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1116 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1117 if (MO->isReg() && MO->isUse())
1118 MO->setIsKill(false);
1119 // Adjust I->end to reach NewIdx. This may temporarily make LI invalid by
1120 // overlapping ranges. Case 5 above.
1121 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1122 // If this was a kill, there may also be a def. Otherwise we're done.
1128 // Check for a def at OldIdx.
1129 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1131 // We have a def at OldIdx.
1132 VNInfo *DefVNI = I->valno;
1133 assert(DefVNI->def == I->start && "Inconsistent def");
1134 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1135 // If the defined value extends beyond NewIdx, just move the def down.
1136 // This is case 1 above.
1137 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1138 I->start = DefVNI->def;
1141 // The remaining possibilities are now:
1142 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1143 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1144 // In either case, it is possible that there is an existing def at NewIdx.
1145 assert((I->end == OldIdx.getDeadSlot() ||
1146 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1147 "Cannot move def below kill");
1148 LiveInterval::iterator NewI = LI.advanceTo(I, NewIdx.getRegSlot());
1149 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1150 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1151 // coalesced into that value.
1152 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1153 LI.removeValNo(DefVNI);
1156 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1157 // If the def at OldIdx was dead, we allow it to be moved across other LI
1158 // values. The new range should be placed immediately before NewI, move any
1159 // intermediate ranges up.
1160 assert(NewI != I && "Inconsistent iterators");
1161 std::copy(llvm::next(I), NewI, I);
1162 *llvm::prior(NewI) = LiveRange(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1165 /// Update LI to reflect an instruction has been moved upwards from OldIdx
1168 /// 1. Live def at OldIdx:
1169 /// Hoist def to NewIdx.
1171 /// 2. Dead def at OldIdx:
1172 /// Hoist def+end to NewIdx, possibly move across other values.
1174 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1175 /// Remove value defined at OldIdx, coalescing it with existing value.
1177 /// 4. Live def at OldIdx AND existing def at NewIdx:
1178 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1179 /// (Happens when bundling multiple defs together).
1181 /// 5. Value killed at OldIdx:
1182 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1185 void handleMoveUp(LiveInterval &LI) {
1186 // First look for a kill at OldIdx.
1187 LiveInterval::iterator I = LI.find(OldIdx.getBaseIndex());
1188 LiveInterval::iterator E = LI.end();
1189 // Is LI even live at OldIdx?
1190 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1193 // Handle a live-in value.
1194 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1195 // If the live-in value isn't killed here, there is nothing to do.
1196 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1198 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1199 // another use, we need to search for that use. Case 5 above.
1200 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1202 // If OldIdx also defines a value, there couldn't have been another use.
1203 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1204 // No def, search for the new kill.
1205 // This can never be an early clobber kill since there is no def.
1206 llvm::prior(I)->end = findLastUseBefore(LI.reg).getRegSlot();
1211 // Now deal with the def at OldIdx.
1212 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1213 VNInfo *DefVNI = I->valno;
1214 assert(DefVNI->def == I->start && "Inconsistent def");
1215 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1217 // Check for an existing def at NewIdx.
1218 LiveInterval::iterator NewI = LI.find(NewIdx.getRegSlot());
1219 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1220 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1221 // There is an existing def at NewIdx.
1222 if (I->end.isDead()) {
1223 // Case 3: Remove the dead def at OldIdx.
1224 LI.removeValNo(DefVNI);
1227 // Case 4: Replace def at NewIdx with live def at OldIdx.
1228 I->start = DefVNI->def;
1229 LI.removeValNo(NewI->valno);
1233 // There is no existing def at NewIdx. Hoist DefVNI.
1234 if (!I->end.isDead()) {
1235 // Leave the end point of a live def.
1236 I->start = DefVNI->def;
1240 // DefVNI is a dead def. It may have been moved across other values in LI,
1241 // so move I up to NewI. Slide [NewI;I) down one position.
1242 std::copy_backward(NewI, I, llvm::next(I));
1243 *NewI = LiveRange(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1246 void updateRegMaskSlots() {
1247 SmallVectorImpl<SlotIndex>::iterator RI =
1248 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1250 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1252 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1253 "RegSlots out of order. Did you move one call across another?");
1256 // Return the last use of reg between NewIdx and OldIdx.
1257 SlotIndex findLastUseBefore(unsigned Reg) {
1258 SlotIndex LastUse = NewIdx;
1260 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1261 for (MachineRegisterInfo::use_nodbg_iterator
1262 UI = MRI.use_nodbg_begin(Reg),
1263 UE = MRI.use_nodbg_end();
1264 UI != UE; UI.skipInstruction()) {
1265 const MachineInstr* MI = &*UI;
1266 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1267 if (InstSlot > LastUse && InstSlot < OldIdx)
1271 MachineInstr* MI = LIS.getSlotIndexes()->getInstructionFromIndex(NewIdx);
1272 MachineBasicBlock::iterator MII(MI);
1274 MachineBasicBlock* MBB = MI->getParent();
1275 for (; MII != MBB->end() && LIS.getInstructionIndex(MII) < OldIdx; ++MII){
1276 for (MachineInstr::mop_iterator MOI = MII->operands_begin(),
1277 MOE = MII->operands_end();
1278 MOI != MOE; ++MOI) {
1279 const MachineOperand& mop = *MOI;
1280 if (!mop.isReg() || mop.getReg() == 0 ||
1281 TargetRegisterInfo::isVirtualRegister(mop.getReg()))
1284 if (TRI.hasRegUnit(mop.getReg(), Reg))
1285 LastUse = LIS.getInstructionIndex(MII);
1293 void LiveIntervals::handleMove(MachineInstr* MI) {
1294 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1295 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1296 Indexes->removeMachineInstrFromMaps(MI);
1297 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1298 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1299 OldIndex < getMBBEndIdx(MI->getParent()) &&
1300 "Cannot handle moves across basic block boundaries.");
1302 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex);
1303 HME.updateAllRanges(MI);
1306 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1307 MachineInstr* BundleStart) {
1308 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1309 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1310 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex);
1311 HME.updateAllRanges(MI);