1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
71 cl::opt<bool> UseSegmentSetForPhysRegs(
72 "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
74 "Use segment set for the computation of the live ranges of physregs."));
77 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
79 AU.addRequired<AliasAnalysis>();
80 AU.addPreserved<AliasAnalysis>();
81 // LiveVariables isn't really required by this analysis, it is only required
82 // here to make sure it is live during TwoAddressInstructionPass and
83 // PHIElimination. This is temporary.
84 AU.addRequired<LiveVariables>();
85 AU.addPreserved<LiveVariables>();
86 AU.addPreservedID(MachineLoopInfoID);
87 AU.addRequiredTransitiveID(MachineDominatorsID);
88 AU.addPreservedID(MachineDominatorsID);
89 AU.addPreserved<SlotIndexes>();
90 AU.addRequiredTransitive<SlotIndexes>();
91 MachineFunctionPass::getAnalysisUsage(AU);
94 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
95 DomTree(nullptr), LRCalc(nullptr) {
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
99 LiveIntervals::~LiveIntervals() {
103 void LiveIntervals::releaseMemory() {
104 // Free the live intervals themselves.
105 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
106 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
107 VirtRegIntervals.clear();
108 RegMaskSlots.clear();
110 RegMaskBlocks.clear();
112 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
113 delete RegUnitRanges[i];
114 RegUnitRanges.clear();
116 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
117 VNInfoAllocator.Reset();
120 /// runOnMachineFunction - calculates LiveIntervals
122 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
124 MRI = &MF->getRegInfo();
125 TRI = MF->getSubtarget().getRegisterInfo();
126 TII = MF->getSubtarget().getInstrInfo();
127 AA = &getAnalysis<AliasAnalysis>();
128 Indexes = &getAnalysis<SlotIndexes>();
129 DomTree = &getAnalysis<MachineDominatorTree>();
131 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
132 MRI->enableSubRegLiveness(true);
135 LRCalc = new LiveRangeCalc();
137 // Allocate space for all virtual registers.
138 VirtRegIntervals.resize(MRI->getNumVirtRegs());
142 computeLiveInRegUnits();
144 if (EnablePrecomputePhysRegs) {
145 // For stress testing, precompute live ranges of all physical register
146 // units, including reserved registers.
147 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
154 /// print - Implement the dump method.
155 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
156 OS << "********** INTERVALS **********\n";
158 // Dump the regunits.
159 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
160 if (LiveRange *LR = RegUnitRanges[i])
161 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
163 // Dump the virtregs.
164 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
165 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
166 if (hasInterval(Reg))
167 OS << getInterval(Reg) << '\n';
171 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
172 OS << ' ' << RegMaskSlots[i];
178 void LiveIntervals::printInstrs(raw_ostream &OS) const {
179 OS << "********** MACHINEINSTRS **********\n";
180 MF->print(OS, Indexes);
183 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
184 void LiveIntervals::dumpInstrs() const {
189 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
190 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
191 llvm::huge_valf : 0.0F;
192 return new LiveInterval(reg, Weight);
196 /// computeVirtRegInterval - Compute the live interval of a virtual register,
197 /// based on defs and uses.
198 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
199 assert(LRCalc && "LRCalc not initialized.");
200 assert(LI.empty() && "Should only compute empty intervals.");
201 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
202 LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
203 computeDeadValues(LI, nullptr);
206 void LiveIntervals::computeVirtRegs() {
207 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
208 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
209 if (MRI->reg_nodbg_empty(Reg))
211 createAndComputeVirtRegInterval(Reg);
215 void LiveIntervals::computeRegMasks() {
216 RegMaskBlocks.resize(MF->getNumBlockIDs());
218 // Find all instructions with regmask operands.
219 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
221 MachineBasicBlock *MBB = MBBI;
222 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
223 RMB.first = RegMaskSlots.size();
224 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
226 for (const MachineOperand &MO : MI->operands()) {
229 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
230 RegMaskBits.push_back(MO.getRegMask());
232 // Compute the number of register mask instructions in this block.
233 RMB.second = RegMaskSlots.size() - RMB.first;
237 //===----------------------------------------------------------------------===//
238 // Register Unit Liveness
239 //===----------------------------------------------------------------------===//
241 // Fixed interference typically comes from ABI boundaries: Function arguments
242 // and return values are passed in fixed registers, and so are exception
243 // pointers entering landing pads. Certain instructions require values to be
244 // present in specific registers. That is also represented through fixed
248 /// computeRegUnitInterval - Compute the live range of a register unit, based
249 /// on the uses and defs of aliasing registers. The range should be empty,
250 /// or contain only dead phi-defs from ABI blocks.
251 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
252 assert(LRCalc && "LRCalc not initialized.");
253 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
255 // The physregs aliasing Unit are the roots and their super-registers.
256 // Create all values as dead defs before extending to uses. Note that roots
257 // may share super-registers. That's OK because createDeadDefs() is
258 // idempotent. It is very rare for a register unit to have multiple roots, so
259 // uniquing super-registers is probably not worthwhile.
260 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
261 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
262 Supers.isValid(); ++Supers) {
263 if (!MRI->reg_empty(*Supers))
264 LRCalc->createDeadDefs(LR, *Supers);
268 // Now extend LR to reach all uses.
269 // Ignore uses of reserved registers. We only track defs of those.
270 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
271 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
272 Supers.isValid(); ++Supers) {
273 unsigned Reg = *Supers;
274 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
275 LRCalc->extendToUses(LR, Reg);
279 // Flush the segment set to the segment vector.
280 if (UseSegmentSetForPhysRegs)
281 LR.flushSegmentSet();
285 /// computeLiveInRegUnits - Precompute the live ranges of any register units
286 /// that are live-in to an ABI block somewhere. Register values can appear
287 /// without a corresponding def when entering the entry block or a landing pad.
289 void LiveIntervals::computeLiveInRegUnits() {
290 RegUnitRanges.resize(TRI->getNumRegUnits());
291 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
293 // Keep track of the live range sets allocated.
294 SmallVector<unsigned, 8> NewRanges;
296 // Check all basic blocks for live-ins.
297 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
299 const MachineBasicBlock *MBB = MFI;
301 // We only care about ABI blocks: Entry + landing pads.
302 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
305 // Create phi-defs at Begin for all live-in registers.
306 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
307 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
308 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
309 LIE = MBB->livein_end(); LII != LIE; ++LII) {
310 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
311 unsigned Unit = *Units;
312 LiveRange *LR = RegUnitRanges[Unit];
314 // Use segment set to speed-up initial computation of the live range.
315 LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
316 NewRanges.push_back(Unit);
318 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
320 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
323 DEBUG(dbgs() << '\n');
325 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
327 // Compute the 'normal' part of the ranges.
328 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
329 unsigned Unit = NewRanges[i];
330 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
335 static void createSegmentsForValues(LiveRange &LR,
336 iterator_range<LiveInterval::vni_iterator> VNIs) {
337 for (auto VNI : VNIs) {
340 SlotIndex Def = VNI->def;
341 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
345 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
347 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
348 ShrinkToUsesWorkList &WorkList,
349 const LiveRange &OldRange) {
350 // Keep track of the PHIs that are in use.
351 SmallPtrSet<VNInfo*, 8> UsedPHIs;
352 // Blocks that have already been added to WorkList as live-out.
353 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
355 // Extend intervals to reach all uses in WorkList.
356 while (!WorkList.empty()) {
357 SlotIndex Idx = WorkList.back().first;
358 VNInfo *VNI = WorkList.back().second;
360 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
361 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
363 // Extend the live range for VNI to be live at Idx.
364 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
365 assert(ExtVNI == VNI && "Unexpected existing value number");
367 // Is this a PHIDef we haven't seen before?
368 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
369 !UsedPHIs.insert(VNI).second)
371 // The PHI is live, make sure the predecessors are live-out.
372 for (auto &Pred : MBB->predecessors()) {
373 if (!LiveOut.insert(Pred).second)
375 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
376 // A predecessor is not required to have a live-out value for a PHI.
377 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
378 WorkList.push_back(std::make_pair(Stop, PVNI));
383 // VNI is live-in to MBB.
384 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
385 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
387 // Make sure VNI is live-out from the predecessors.
388 for (auto &Pred : MBB->predecessors()) {
389 if (!LiveOut.insert(Pred).second)
391 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
392 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
393 "Wrong value out of predecessor");
394 WorkList.push_back(std::make_pair(Stop, VNI));
399 bool LiveIntervals::shrinkToUses(LiveInterval *li,
400 SmallVectorImpl<MachineInstr*> *dead) {
401 DEBUG(dbgs() << "Shrink: " << *li << '\n');
402 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
403 && "Can only shrink virtual registers");
405 // Shrink subregister live ranges.
406 bool NeedsCleanup = false;
407 for (LiveInterval::SubRange &S : li->subranges()) {
408 shrinkToUses(S, li->reg);
413 li->removeEmptySubRanges();
415 // Find all the values used, including PHI kills.
416 ShrinkToUsesWorkList WorkList;
418 // Visit all instructions reading li->reg.
419 for (MachineRegisterInfo::reg_instr_iterator
420 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
422 MachineInstr *UseMI = &*(I++);
423 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
425 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
426 LiveQueryResult LRQ = li->Query(Idx);
427 VNInfo *VNI = LRQ.valueIn();
429 // This shouldn't happen: readsVirtualRegister returns true, but there is
430 // no live value. It is likely caused by a target getting <undef> flags
432 DEBUG(dbgs() << Idx << '\t' << *UseMI
433 << "Warning: Instr claims to read non-existent value in "
437 // Special case: An early-clobber tied operand reads and writes the
438 // register one slot early.
439 if (VNInfo *DefVNI = LRQ.valueDefined())
442 WorkList.push_back(std::make_pair(Idx, VNI));
445 // Create new live ranges with only minimal live segments per def.
447 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
448 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
450 // Move the trimmed segments back.
451 li->segments.swap(NewLR.segments);
453 // Handle dead values.
454 bool CanSeparate = computeDeadValues(*li, dead);
455 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
459 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
460 SmallVectorImpl<MachineInstr*> *dead) {
461 bool PHIRemoved = false;
462 for (auto VNI : LI.valnos) {
465 SlotIndex Def = VNI->def;
466 LiveRange::iterator I = LI.FindSegmentContaining(Def);
467 assert(I != LI.end() && "Missing segment for VNI");
469 // Is the register live before? Otherwise we may have to add a read-undef
470 // flag for subregister defs.
471 if (MRI->shouldTrackSubRegLiveness(LI.reg)) {
472 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
473 MachineInstr *MI = getInstructionFromIndex(Def);
474 MI->addRegisterDefReadUndef(LI.reg);
478 if (I->end != Def.getDeadSlot())
480 if (VNI->isPHIDef()) {
481 // This is a dead PHI. Remove it.
484 DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
487 // This is a dead def. Make sure the instruction knows.
488 MachineInstr *MI = getInstructionFromIndex(Def);
489 assert(MI && "No instruction defining live value");
490 MI->addRegisterDead(LI.reg, TRI);
491 if (dead && MI->allDefsAreDead()) {
492 DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
500 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
502 DEBUG(dbgs() << "Shrink: " << SR << '\n');
503 assert(TargetRegisterInfo::isVirtualRegister(Reg)
504 && "Can only shrink virtual registers");
505 // Find all the values used, including PHI kills.
506 ShrinkToUsesWorkList WorkList;
508 // Visit all instructions reading Reg.
510 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
511 MachineInstr *UseMI = MO.getParent();
512 if (UseMI->isDebugValue())
514 // Maybe the operand is for a subregister we don't care about.
515 unsigned SubReg = MO.getSubReg();
517 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
518 if ((SubRegMask & SR.LaneMask) == 0)
521 // We only need to visit each instruction once.
522 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
527 LiveQueryResult LRQ = SR.Query(Idx);
528 VNInfo *VNI = LRQ.valueIn();
529 // For Subranges it is possible that only undef values are left in that
530 // part of the subregister, so there is no real liverange at the use
534 // Special case: An early-clobber tied operand reads and writes the
535 // register one slot early.
536 if (VNInfo *DefVNI = LRQ.valueDefined())
539 WorkList.push_back(std::make_pair(Idx, VNI));
542 // Create a new live ranges with only minimal live segments per def.
544 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
545 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
547 // Move the trimmed ranges back.
548 SR.segments.swap(NewLR.segments);
550 // Remove dead PHI value numbers
551 for (auto VNI : SR.valnos) {
554 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
555 assert(Segment != nullptr && "Missing segment for VNI");
556 if (Segment->end != VNI->def.getDeadSlot())
558 if (VNI->isPHIDef()) {
559 // This is a dead PHI. Remove it.
561 SR.removeSegment(*Segment);
562 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
566 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
569 void LiveIntervals::extendToIndices(LiveRange &LR,
570 ArrayRef<SlotIndex> Indices) {
571 assert(LRCalc && "LRCalc not initialized.");
572 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
573 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
574 LRCalc->extend(LR, Indices[i]);
577 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
578 SmallVectorImpl<SlotIndex> *EndPoints) {
579 LiveQueryResult LRQ = LR.Query(Kill);
580 VNInfo *VNI = LRQ.valueOutOrDead();
584 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
585 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
587 // If VNI isn't live out from KillMBB, the value is trivially pruned.
588 if (LRQ.endPoint() < MBBEnd) {
589 LR.removeSegment(Kill, LRQ.endPoint());
590 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
594 // VNI is live out of KillMBB.
595 LR.removeSegment(Kill, MBBEnd);
596 if (EndPoints) EndPoints->push_back(MBBEnd);
598 // Find all blocks that are reachable from KillMBB without leaving VNI's live
599 // range. It is possible that KillMBB itself is reachable, so start a DFS
600 // from each successor.
601 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
603 for (MachineBasicBlock::succ_iterator
604 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
605 SuccI != SuccE; ++SuccI) {
606 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
607 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
609 MachineBasicBlock *MBB = *I;
611 // Check if VNI is live in to MBB.
612 SlotIndex MBBStart, MBBEnd;
613 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
614 LiveQueryResult LRQ = LR.Query(MBBStart);
615 if (LRQ.valueIn() != VNI) {
616 // This block isn't part of the VNI segment. Prune the search.
621 // Prune the search if VNI is killed in MBB.
622 if (LRQ.endPoint() < MBBEnd) {
623 LR.removeSegment(MBBStart, LRQ.endPoint());
624 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
629 // VNI is live through MBB.
630 LR.removeSegment(MBBStart, MBBEnd);
631 if (EndPoints) EndPoints->push_back(MBBEnd);
637 //===----------------------------------------------------------------------===//
638 // Register allocator hooks.
641 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
642 // Keep track of regunit ranges.
643 SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
644 // Keep track of subregister ranges.
645 SmallVector<std::pair<const LiveInterval::SubRange*,
646 LiveRange::const_iterator>, 4> SRs;
648 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
649 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
650 if (MRI->reg_nodbg_empty(Reg))
652 const LiveInterval &LI = getInterval(Reg);
656 // Find the regunit intervals for the assigned register. They may overlap
657 // the virtual register live range, cancelling any kills.
659 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
661 const LiveRange &RURange = getRegUnit(*Units);
664 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
667 if (MRI->subRegLivenessEnabled()) {
669 for (const LiveInterval::SubRange &SR : LI.subranges()) {
670 SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
674 // Every instruction that kills Reg corresponds to a segment range end
676 for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
678 // A block index indicates an MBB edge.
679 if (RI->end.isBlock())
681 MachineInstr *MI = getInstructionFromIndex(RI->end);
685 // Check if any of the regunits are live beyond the end of RI. That could
686 // happen when a physreg is defined as a copy of a virtreg:
688 // %EAX = COPY %vreg5
689 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
692 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
693 for (auto &RUP : RU) {
694 const LiveRange &RURange = *RUP.first;
695 LiveRange::const_iterator &I = RUP.second;
696 if (I == RURange.end())
698 I = RURange.advanceTo(I, RI->end);
699 if (I == RURange.end() || I->start >= RI->end)
701 // I is overlapping RI.
705 if (MRI->subRegLivenessEnabled()) {
706 // When reading a partial undefined value we must not add a kill flag.
707 // The regalloc might have used the undef lane for something else.
709 // %vreg1 = ... ; R32: %vreg1
710 // %vreg2:high16 = ... ; R64: %vreg2
711 // = read %vreg2<kill> ; R64: %vreg2
712 // = read %vreg1 ; R32: %vreg1
713 // The <kill> flag is correct for %vreg2, but the register allocator may
714 // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
715 // are actually never written by %vreg2. After assignment the <kill>
716 // flag at the read instruction is invalid.
717 unsigned DefinedLanesMask;
719 // Compute a mask of lanes that are defined.
720 DefinedLanesMask = 0;
721 for (auto &SRP : SRs) {
722 const LiveInterval::SubRange &SR = *SRP.first;
723 LiveRange::const_iterator &I = SRP.second;
726 I = SR.advanceTo(I, RI->end);
727 if (I == SR.end() || I->start >= RI->end)
729 // I is overlapping RI
730 DefinedLanesMask |= SR.LaneMask;
733 DefinedLanesMask = ~0u;
735 bool IsFullWrite = false;
736 for (const MachineOperand &MO : MI->operands()) {
737 if (!MO.isReg() || MO.getReg() != Reg)
740 // Reading any undefined lanes?
741 unsigned UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
742 if ((UseMask & ~DefinedLanesMask) != 0)
744 } else if (MO.getSubReg() == 0) {
745 // Writing to the full register?
751 // If an instruction writes to a subregister, a new segment starts in
752 // the LiveInterval. But as this is only overriding part of the register
753 // adding kill-flags is not correct here after registers have been
756 // Next segment has to be adjacent in the subregister write case.
757 LiveRange::const_iterator N = std::next(RI);
758 if (N != LI.end() && N->start == RI->end)
763 MI->addRegisterKilled(Reg, nullptr);
766 MI->clearRegisterKills(Reg, nullptr);
772 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
773 // A local live range must be fully contained inside the block, meaning it is
774 // defined and killed at instructions, not at block boundaries. It is not
775 // live in or or out of any block.
777 // It is technically possible to have a PHI-defined live range identical to a
778 // single block, but we are going to return false in that case.
780 SlotIndex Start = LI.beginIndex();
784 SlotIndex Stop = LI.endIndex();
788 // getMBBFromIndex doesn't need to search the MBB table when both indexes
789 // belong to proper instructions.
790 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
791 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
792 return MBB1 == MBB2 ? MBB1 : nullptr;
796 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
797 for (const VNInfo *PHI : LI.valnos) {
798 if (PHI->isUnused() || !PHI->isPHIDef())
800 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
801 // Conservatively return true instead of scanning huge predecessor lists.
802 if (PHIMBB->pred_size() > 100)
804 for (MachineBasicBlock::const_pred_iterator
805 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
806 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
813 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
814 const MachineBlockFrequencyInfo *MBFI,
815 const MachineInstr *MI) {
816 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
817 const float Scale = 1.0f / MBFI->getEntryFreq();
818 return (isDef + isUse) * (Freq.getFrequency() * Scale);
822 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
823 LiveInterval& Interval = createEmptyInterval(reg);
824 VNInfo* VN = Interval.getNextValue(
825 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
826 getVNInfoAllocator());
827 LiveRange::Segment S(
828 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
829 getMBBEndIdx(startInst->getParent()), VN);
830 Interval.addSegment(S);
836 //===----------------------------------------------------------------------===//
837 // Register mask functions
838 //===----------------------------------------------------------------------===//
840 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
841 BitVector &UsableRegs) {
844 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
846 // Use a smaller arrays for local live ranges.
847 ArrayRef<SlotIndex> Slots;
848 ArrayRef<const uint32_t*> Bits;
849 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
850 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
851 Bits = getRegMaskBitsInBlock(MBB->getNumber());
853 Slots = getRegMaskSlots();
854 Bits = getRegMaskBits();
857 // We are going to enumerate all the register mask slots contained in LI.
858 // Start with a binary search of RegMaskSlots to find a starting point.
859 ArrayRef<SlotIndex>::iterator SlotI =
860 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
861 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
863 // No slots in range, LI begins after the last call.
869 assert(*SlotI >= LiveI->start);
870 // Loop over all slots overlapping this segment.
871 while (*SlotI < LiveI->end) {
872 // *SlotI overlaps LI. Collect mask bits.
874 // This is the first overlap. Initialize UsableRegs to all ones.
876 UsableRegs.resize(TRI->getNumRegs(), true);
879 // Remove usable registers clobbered by this mask.
880 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
881 if (++SlotI == SlotE)
884 // *SlotI is beyond the current LI segment.
885 LiveI = LI.advanceTo(LiveI, *SlotI);
888 // Advance SlotI until it overlaps.
889 while (*SlotI < LiveI->start)
890 if (++SlotI == SlotE)
895 //===----------------------------------------------------------------------===//
896 // IntervalUpdate class.
897 //===----------------------------------------------------------------------===//
899 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
900 class LiveIntervals::HMEditor {
903 const MachineRegisterInfo& MRI;
904 const TargetRegisterInfo& TRI;
907 SmallPtrSet<LiveRange*, 8> Updated;
911 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
912 const TargetRegisterInfo& TRI,
913 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
914 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
915 UpdateFlags(UpdateFlags) {}
917 // FIXME: UpdateFlags is a workaround that creates live intervals for all
918 // physregs, even those that aren't needed for regalloc, in order to update
919 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
920 // flags, and postRA passes will use a live register utility instead.
921 LiveRange *getRegUnitLI(unsigned Unit) {
923 return &LIS.getRegUnit(Unit);
924 return LIS.getCachedRegUnit(Unit);
927 /// Update all live ranges touched by MI, assuming a move from OldIdx to
929 void updateAllRanges(MachineInstr *MI) {
930 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
931 bool hasRegMask = false;
932 for (MachineOperand &MO : MI->operands()) {
937 // Aggressively clear all kill flags.
938 // They are reinserted by VirtRegRewriter.
942 unsigned Reg = MO.getReg();
945 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
946 LiveInterval &LI = LIS.getInterval(Reg);
947 if (LI.hasSubRanges()) {
948 unsigned SubReg = MO.getSubReg();
949 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
950 for (LiveInterval::SubRange &S : LI.subranges()) {
951 if ((S.LaneMask & LaneMask) == 0)
953 updateRange(S, Reg, S.LaneMask);
956 updateRange(LI, Reg, 0);
960 // For physregs, only update the regunits that actually have a
961 // precomputed live range.
962 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
963 if (LiveRange *LR = getRegUnitLI(*Units))
964 updateRange(*LR, *Units, 0);
967 updateRegMaskSlots();
971 /// Update a single live range, assuming an instruction has been moved from
972 /// OldIdx to NewIdx.
973 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
974 if (!Updated.insert(&LR).second)
978 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
979 dbgs() << PrintReg(Reg);
981 dbgs() << format(" L%04X", LaneMask);
983 dbgs() << PrintRegUnit(Reg, &TRI);
985 dbgs() << ":\t" << LR << '\n';
987 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
990 handleMoveUp(LR, Reg, LaneMask);
991 DEBUG(dbgs() << " -->\t" << LR << '\n');
995 /// Update LR to reflect an instruction has been moved downwards from OldIdx
998 /// 1. Live def at OldIdx:
999 /// Move def to NewIdx, assert endpoint after NewIdx.
1001 /// 2. Live def at OldIdx, killed at NewIdx:
1002 /// Change to dead def at NewIdx.
1003 /// (Happens when bundling def+kill together).
1005 /// 3. Dead def at OldIdx:
1006 /// Move def to NewIdx, possibly across another live value.
1008 /// 4. Def at OldIdx AND at NewIdx:
1009 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
1010 /// (Happens when bundling multiple defs together).
1012 /// 5. Value read at OldIdx, killed before NewIdx:
1013 /// Extend kill to NewIdx.
1015 void handleMoveDown(LiveRange &LR) {
1016 // First look for a kill at OldIdx.
1017 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1018 LiveRange::iterator E = LR.end();
1019 // Is LR even live at OldIdx?
1020 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1023 // Handle a live-in value.
1024 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1025 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1026 // If the live-in value already extends to NewIdx, there is nothing to do.
1027 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1029 // Aggressively remove all kill flags from the old kill point.
1030 // Kill flags shouldn't be used while live intervals exist, they will be
1031 // reinserted by VirtRegRewriter.
1032 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1033 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1034 if (MO->isReg() && MO->isUse())
1035 MO->setIsKill(false);
1036 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
1037 // overlapping ranges. Case 5 above.
1038 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1039 // If this was a kill, there may also be a def. Otherwise we're done.
1045 // Check for a def at OldIdx.
1046 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1048 // We have a def at OldIdx.
1049 VNInfo *DefVNI = I->valno;
1050 assert(DefVNI->def == I->start && "Inconsistent def");
1051 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1052 // If the defined value extends beyond NewIdx, just move the def down.
1053 // This is case 1 above.
1054 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1055 I->start = DefVNI->def;
1058 // The remaining possibilities are now:
1059 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1060 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1061 // In either case, it is possible that there is an existing def at NewIdx.
1062 assert((I->end == OldIdx.getDeadSlot() ||
1063 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1064 "Cannot move def below kill");
1065 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
1066 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1067 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1068 // coalesced into that value.
1069 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1070 LR.removeValNo(DefVNI);
1073 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1074 // If the def at OldIdx was dead, we allow it to be moved across other LR
1075 // values. The new range should be placed immediately before NewI, move any
1076 // intermediate ranges up.
1077 assert(NewI != I && "Inconsistent iterators");
1078 std::copy(std::next(I), NewI, I);
1080 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1083 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1086 /// 1. Live def at OldIdx:
1087 /// Hoist def to NewIdx.
1089 /// 2. Dead def at OldIdx:
1090 /// Hoist def+end to NewIdx, possibly move across other values.
1092 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1093 /// Remove value defined at OldIdx, coalescing it with existing value.
1095 /// 4. Live def at OldIdx AND existing def at NewIdx:
1096 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1097 /// (Happens when bundling multiple defs together).
1099 /// 5. Value killed at OldIdx:
1100 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1103 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1104 // First look for a kill at OldIdx.
1105 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1106 LiveRange::iterator E = LR.end();
1107 // Is LR even live at OldIdx?
1108 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1111 // Handle a live-in value.
1112 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1113 // If the live-in value isn't killed here, there is nothing to do.
1114 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1116 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1117 // another use, we need to search for that use. Case 5 above.
1118 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1120 // If OldIdx also defines a value, there couldn't have been another use.
1121 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1122 // No def, search for the new kill.
1123 // This can never be an early clobber kill since there is no def.
1124 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1129 // Now deal with the def at OldIdx.
1130 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1131 VNInfo *DefVNI = I->valno;
1132 assert(DefVNI->def == I->start && "Inconsistent def");
1133 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1135 // Check for an existing def at NewIdx.
1136 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1137 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1138 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1139 // There is an existing def at NewIdx.
1140 if (I->end.isDead()) {
1141 // Case 3: Remove the dead def at OldIdx.
1142 LR.removeValNo(DefVNI);
1145 // Case 4: Replace def at NewIdx with live def at OldIdx.
1146 I->start = DefVNI->def;
1147 LR.removeValNo(NewI->valno);
1151 // There is no existing def at NewIdx. Hoist DefVNI.
1152 if (!I->end.isDead()) {
1153 // Leave the end point of a live def.
1154 I->start = DefVNI->def;
1158 // DefVNI is a dead def. It may have been moved across other values in LR,
1159 // so move I up to NewI. Slide [NewI;I) down one position.
1160 std::copy_backward(NewI, I, std::next(I));
1161 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1164 void updateRegMaskSlots() {
1165 SmallVectorImpl<SlotIndex>::iterator RI =
1166 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1168 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1169 "No RegMask at OldIdx.");
1170 *RI = NewIdx.getRegSlot();
1171 assert((RI == LIS.RegMaskSlots.begin() ||
1172 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1173 "Cannot move regmask instruction above another call");
1174 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1175 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1176 "Cannot move regmask instruction below another call");
1179 // Return the last use of reg between NewIdx and OldIdx.
1180 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1182 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1183 SlotIndex LastUse = NewIdx;
1184 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1185 unsigned SubReg = MO.getSubReg();
1186 if (SubReg != 0 && LaneMask != 0
1187 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1190 const MachineInstr *MI = MO.getParent();
1191 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1192 if (InstSlot > LastUse && InstSlot < OldIdx)
1198 // This is a regunit interval, so scanning the use list could be very
1199 // expensive. Scan upwards from OldIdx instead.
1200 assert(NewIdx < OldIdx && "Expected upwards move");
1201 SlotIndexes *Indexes = LIS.getSlotIndexes();
1202 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1204 // OldIdx may not correspond to an instruction any longer, so set MII to
1205 // point to the next instruction after OldIdx, or MBB->end().
1206 MachineBasicBlock::iterator MII = MBB->end();
1207 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1208 Indexes->getNextNonNullIndex(OldIdx)))
1209 if (MI->getParent() == MBB)
1212 MachineBasicBlock::iterator Begin = MBB->begin();
1213 while (MII != Begin) {
1214 if ((--MII)->isDebugValue())
1216 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1218 // Stop searching when NewIdx is reached.
1219 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1222 // Check if MII uses Reg.
1223 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1225 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1226 TRI.hasRegUnit(MO->getReg(), Reg))
1229 // Didn't reach NewIdx. It must be the first instruction in the block.
1234 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1235 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1236 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1237 Indexes->removeMachineInstrFromMaps(MI);
1238 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1239 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1240 OldIndex < getMBBEndIdx(MI->getParent()) &&
1241 "Cannot handle moves across basic block boundaries.");
1243 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1244 HME.updateAllRanges(MI);
1247 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1248 MachineInstr* BundleStart,
1250 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1251 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1252 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1253 HME.updateAllRanges(MI);
1256 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1257 const MachineBasicBlock::iterator End,
1258 const SlotIndex endIdx,
1259 LiveRange &LR, const unsigned Reg,
1260 const unsigned LaneMask) {
1261 LiveInterval::iterator LII = LR.find(endIdx);
1262 SlotIndex lastUseIdx;
1263 if (LII != LR.end() && LII->start < endIdx)
1264 lastUseIdx = LII->end;
1268 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1270 MachineInstr *MI = I;
1271 if (MI->isDebugValue())
1274 SlotIndex instrIdx = getInstructionIndex(MI);
1275 bool isStartValid = getInstructionFromIndex(LII->start);
1276 bool isEndValid = getInstructionFromIndex(LII->end);
1278 // FIXME: This doesn't currently handle early-clobber or multiple removed
1279 // defs inside of the region to repair.
1280 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1281 OE = MI->operands_end(); OI != OE; ++OI) {
1282 const MachineOperand &MO = *OI;
1283 if (!MO.isReg() || MO.getReg() != Reg)
1286 unsigned SubReg = MO.getSubReg();
1287 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1288 if ((Mask & LaneMask) == 0)
1292 if (!isStartValid) {
1293 if (LII->end.isDead()) {
1294 SlotIndex prevStart;
1295 if (LII != LR.begin())
1296 prevStart = std::prev(LII)->start;
1298 // FIXME: This could be more efficient if there was a
1299 // removeSegment method that returned an iterator.
1300 LR.removeSegment(*LII, true);
1301 if (prevStart.isValid())
1302 LII = LR.find(prevStart);
1306 LII->start = instrIdx.getRegSlot();
1307 LII->valno->def = instrIdx.getRegSlot();
1308 if (MO.getSubReg() && !MO.isUndef())
1309 lastUseIdx = instrIdx.getRegSlot();
1311 lastUseIdx = SlotIndex();
1316 if (!lastUseIdx.isValid()) {
1317 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1318 LiveRange::Segment S(instrIdx.getRegSlot(),
1319 instrIdx.getDeadSlot(), VNI);
1320 LII = LR.addSegment(S);
1321 } else if (LII->start != instrIdx.getRegSlot()) {
1322 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1323 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1324 LII = LR.addSegment(S);
1327 if (MO.getSubReg() && !MO.isUndef())
1328 lastUseIdx = instrIdx.getRegSlot();
1330 lastUseIdx = SlotIndex();
1331 } else if (MO.isUse()) {
1332 // FIXME: This should probably be handled outside of this branch,
1333 // either as part of the def case (for defs inside of the region) or
1334 // after the loop over the region.
1335 if (!isEndValid && !LII->end.isBlock())
1336 LII->end = instrIdx.getRegSlot();
1337 if (!lastUseIdx.isValid())
1338 lastUseIdx = instrIdx.getRegSlot();
1345 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1346 MachineBasicBlock::iterator Begin,
1347 MachineBasicBlock::iterator End,
1348 ArrayRef<unsigned> OrigRegs) {
1349 // Find anchor points, which are at the beginning/end of blocks or at
1350 // instructions that already have indexes.
1351 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1353 while (End != MBB->end() && !Indexes->hasIndex(End))
1357 if (End == MBB->end())
1358 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1360 endIdx = getInstructionIndex(End);
1362 Indexes->repairIndexesInRange(MBB, Begin, End);
1364 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1366 MachineInstr *MI = I;
1367 if (MI->isDebugValue())
1369 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1370 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1372 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1373 !hasInterval(MOI->getReg())) {
1374 createAndComputeVirtRegInterval(MOI->getReg());
1379 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1380 unsigned Reg = OrigRegs[i];
1381 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1384 LiveInterval &LI = getInterval(Reg);
1385 // FIXME: Should we support undefs that gain defs?
1386 if (!LI.hasAtLeastOneValue())
1389 for (LiveInterval::SubRange &S : LI.subranges()) {
1390 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1392 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1396 void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
1397 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1398 if (LiveRange *LR = getCachedRegUnit(*Units))
1399 if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1400 LR->removeValNo(VNI);
1404 void LiveIntervals::removeVRegDefAt(LiveInterval &LI, SlotIndex Pos) {
1405 VNInfo *VNI = LI.getVNInfoAt(Pos);
1408 LI.removeValNo(VNI);
1410 // Also remove the value in subranges.
1411 for (LiveInterval::SubRange &S : LI.subranges()) {
1412 if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1413 S.removeValNo(SVNI);
1415 LI.removeEmptySubRanges();