1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
40 // Hidden options for help debugging.
41 cl::opt<bool> DisableReMat("disable-rematerialization",
42 cl::init(false), cl::Hidden);
45 STATISTIC(numIntervals, "Number of original intervals");
46 STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
47 STATISTIC(numFolded , "Number of loads/stores folded into instructions");
49 char LiveIntervals::ID = 0;
51 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
54 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.addPreserved<LiveVariables>();
56 AU.addRequired<LiveVariables>();
57 AU.addPreservedID(PHIEliminationID);
58 AU.addRequiredID(PHIEliminationID);
59 AU.addRequiredID(TwoAddressInstructionPassID);
60 AU.addRequired<LoopInfo>();
61 MachineFunctionPass::getAnalysisUsage(AU);
64 void LiveIntervals::releaseMemory() {
68 for (unsigned i = 0, e = ClonedMIs.size(); i != e; ++i)
72 /// runOnMachineFunction - Register allocate the whole function
74 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
76 tm_ = &fn.getTarget();
77 mri_ = tm_->getRegisterInfo();
78 tii_ = tm_->getInstrInfo();
79 lv_ = &getAnalysis<LiveVariables>();
80 allocatableRegs_ = mri_->getAllocatableSet(fn);
82 // Number MachineInstrs and MachineBasicBlocks.
83 // Initialize MBB indexes to a sentinal.
84 MBB2IdxMap.resize(mf_->getNumBlockIDs(), std::make_pair(~0U,~0U));
87 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
89 unsigned StartIdx = MIIndex;
91 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
93 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
94 assert(inserted && "multiple MachineInstr -> index mappings");
95 i2miMap_.push_back(I);
96 MIIndex += InstrSlots::NUM;
99 // Set the MBB2IdxMap entry for this MBB.
100 MBB2IdxMap[MBB->getNumber()] = std::make_pair(StartIdx, MIIndex - 1);
105 numIntervals += getNumIntervals();
107 DOUT << "********** INTERVALS **********\n";
108 for (iterator I = begin(), E = end(); I != E; ++I) {
109 I->second.print(DOUT, mri_);
113 numIntervalsAfter += getNumIntervals();
118 /// print - Implement the dump method.
119 void LiveIntervals::print(std::ostream &O, const Module* ) const {
120 O << "********** INTERVALS **********\n";
121 for (const_iterator I = begin(), E = end(); I != E; ++I) {
122 I->second.print(DOUT, mri_);
126 O << "********** MACHINEINSTRS **********\n";
127 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
128 mbbi != mbbe; ++mbbi) {
129 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
130 for (MachineBasicBlock::iterator mii = mbbi->begin(),
131 mie = mbbi->end(); mii != mie; ++mii) {
132 O << getInstructionIndex(mii) << '\t' << *mii;
138 /// CreateNewLiveInterval - Create a new live interval with the given live
139 /// ranges. The new live interval will have an infinite spill weight.
141 LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
142 const std::vector<LiveRange> &LRs) {
143 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
145 // Create a new virtual register for the spill interval.
146 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
148 // Replace the old virtual registers in the machine operands with the shiny
150 for (std::vector<LiveRange>::const_iterator
151 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
152 unsigned Index = getBaseIndex(I->start);
153 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
155 for (; Index != End; Index += InstrSlots::NUM) {
156 // Skip deleted instructions
157 while (Index != End && !getInstructionFromIndex(Index))
158 Index += InstrSlots::NUM;
160 if (Index == End) break;
162 MachineInstr *MI = getInstructionFromIndex(Index);
164 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
165 MachineOperand &MOp = MI->getOperand(J);
166 if (MOp.isRegister() && MOp.getReg() == LI->reg)
172 LiveInterval &NewLI = getOrCreateInterval(NewVReg);
174 // The spill weight is now infinity as it cannot be spilled again
175 NewLI.weight = float(HUGE_VAL);
177 for (std::vector<LiveRange>::const_iterator
178 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
179 DOUT << " Adding live range " << *I << " to new interval\n";
183 DOUT << "Created new live interval " << NewLI << "\n";
187 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
188 /// two addr elimination.
189 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
190 const TargetInstrInfo *TII) {
191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
192 MachineOperand &MO1 = MI->getOperand(i);
193 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
194 for (unsigned j = i+1; j < e; ++j) {
195 MachineOperand &MO2 = MI->getOperand(j);
196 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
197 MI->getInstrDescriptor()->
198 getOperandConstraint(j, TOI::TIED_TO) == (int)i)
206 /// isReMaterializable - Returns true if the definition MI of the specified
207 /// val# of the specified interval is re-materializable.
208 bool LiveIntervals::isReMaterializable(const LiveInterval &li, unsigned ValNum,
213 if (tii_->isTriviallyReMaterializable(MI))
217 if (!tii_->isLoadFromStackSlot(MI, FrameIdx) ||
218 !mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx))
221 // This is a load from fixed stack slot. It can be rematerialized unless it's
222 // re-defined by a two-address instruction.
223 for (unsigned i = 0, e = li.getNumValNums(); i != e; ++i) {
226 unsigned DefIdx = li.getDefForValNum(i);
228 continue; // Dead val#.
229 MachineInstr *DefMI = (DefIdx == ~0u)
230 ? NULL : getInstructionFromIndex(DefIdx);
231 if (DefMI && isReDefinedByTwoAddr(DefMI, li.reg, tii_))
237 bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
238 unsigned index, unsigned i,
239 int slot, unsigned reg) {
240 MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot);
242 // Attempt to fold the memory reference into the instruction. If
243 // we can do this, we don't need to insert spill code.
245 lv_->instructionChanged(MI, fmi);
246 MachineBasicBlock &MBB = *MI->getParent();
247 vrm.virtFolded(reg, MI, i, fmi);
249 i2miMap_[index/InstrSlots::NUM] = fmi;
250 mi2iMap_[fmi] = index;
251 MI = MBB.insert(MBB.erase(MI), fmi);
258 std::vector<LiveInterval*> LiveIntervals::
259 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, unsigned reg) {
260 // since this is called after the analysis is done we don't know if
261 // LiveVariables is available
262 lv_ = getAnalysisToUpdate<LiveVariables>();
264 std::vector<LiveInterval*> added;
266 assert(li.weight != HUGE_VALF &&
267 "attempt to spill already spilled interval!");
269 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
270 li.print(DOUT, mri_);
273 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
275 unsigned NumValNums = li.getNumValNums();
276 SmallVector<MachineInstr*, 4> ReMatDefs;
277 ReMatDefs.resize(NumValNums, NULL);
278 SmallVector<MachineInstr*, 4> ReMatOrigDefs;
279 ReMatOrigDefs.resize(NumValNums, NULL);
280 SmallVector<int, 4> ReMatIds;
281 ReMatIds.resize(NumValNums, VirtRegMap::MAX_STACK_SLOT);
282 BitVector ReMatDelete(NumValNums);
283 unsigned slot = VirtRegMap::MAX_STACK_SLOT;
285 bool NeedStackSlot = false;
286 for (unsigned i = 0; i != NumValNums; ++i) {
287 unsigned DefIdx = li.getDefForValNum(i);
289 continue; // Dead val#.
290 // Is the def for the val# rematerializable?
291 MachineInstr *DefMI = (DefIdx == ~0u)
292 ? NULL : getInstructionFromIndex(DefIdx);
293 if (DefMI && isReMaterializable(li, i, DefMI)) {
294 // Remember how to remat the def of this val#.
295 ReMatOrigDefs[i] = DefMI;
296 // Original def may be modified so we have to make a copy here. vrm must
298 ReMatDefs[i] = DefMI = DefMI->clone();
299 vrm.setVirtIsReMaterialized(reg, DefMI);
301 bool CanDelete = true;
302 const SmallVector<unsigned, 4> &kills = li.getKillsForValNum(i);
303 for (unsigned j = 0, ee = kills.size(); j != ee; ++j) {
304 unsigned KillIdx = kills[j];
305 MachineInstr *KillMI = (KillIdx & 1)
306 ? NULL : getInstructionFromIndex(KillIdx);
307 // Kill is a phi node, not all of its uses can be rematerialized.
308 // It must not be deleted.
311 // Need a stack slot if there is any live range where uses cannot be
313 NeedStackSlot = true;
321 // Need a stack slot if there is any live range where uses cannot be
323 NeedStackSlot = true;
327 // One stack slot per live interval.
329 slot = vrm.assignVirt2StackSlot(reg);
331 for (LiveInterval::Ranges::const_iterator
332 I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
333 MachineInstr *DefMI = ReMatDefs[I->ValId];
334 MachineInstr *OrigDefMI = ReMatOrigDefs[I->ValId];
335 bool DefIsReMat = DefMI != NULL;
336 bool CanDelete = ReMatDelete[I->ValId];
338 bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(DefMI, LdSlot);
339 unsigned index = getBaseIndex(I->start);
340 unsigned end = getBaseIndex(I->end-1) + InstrSlots::NUM;
341 for (; index != end; index += InstrSlots::NUM) {
342 // skip deleted instructions
343 while (index != end && !getInstructionFromIndex(index))
344 index += InstrSlots::NUM;
345 if (index == end) break;
347 MachineInstr *MI = getInstructionFromIndex(index);
350 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
351 MachineOperand& mop = MI->getOperand(i);
352 if (mop.isRegister() && mop.getReg() == li.reg) {
354 // If this is the rematerializable definition MI itself and
355 // all of its uses are rematerialized, simply delete it.
356 if (MI == OrigDefMI) {
358 RemoveMachineInstrFromMaps(MI);
359 MI->eraseFromParent();
361 } else if (tryFoldMemoryOperand(MI, vrm, index, i, slot, li.reg))
362 // Folding the load/store can completely change the instruction
363 // in unpredictable ways, rescan it from the beginning.
364 goto RestartInstruction;
365 } else if (isLoadSS &&
366 tryFoldMemoryOperand(MI, vrm, index, i, LdSlot, li.reg)){
367 // FIXME: Other rematerializable loads can be folded as well.
368 // Folding the load/store can completely change the
369 // instruction in unpredictable ways, rescan it from
371 goto RestartInstruction;
374 if (tryFoldMemoryOperand(MI, vrm, index, i, slot, li.reg))
375 // Folding the load/store can completely change the instruction in
376 // unpredictable ways, rescan it from the beginning.
377 goto RestartInstruction;
380 // Create a new virtual register for the spill interval.
381 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
383 // Scan all of the operands of this instruction rewriting operands
384 // to use NewVReg instead of li.reg as appropriate. We do this for
387 // 1. If the instr reads the same spilled vreg multiple times, we
388 // want to reuse the NewVReg.
389 // 2. If the instr is a two-addr instruction, we are required to
390 // keep the src/dst regs pinned.
392 // Keep track of whether we replace a use and/or def so that we can
393 // create the spill interval with the appropriate range.
396 bool HasUse = mop.isUse();
397 bool HasDef = mop.isDef();
398 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
399 if (MI->getOperand(j).isReg() &&
400 MI->getOperand(j).getReg() == li.reg) {
401 MI->getOperand(j).setReg(NewVReg);
402 HasUse |= MI->getOperand(j).isUse();
403 HasDef |= MI->getOperand(j).isDef();
409 vrm.setVirtIsReMaterialized(NewVReg, DefMI/*, CanDelete*/);
410 if (ReMatIds[I->ValId] == VirtRegMap::MAX_STACK_SLOT) {
411 // Each valnum may have its own remat id.
412 ReMatIds[I->ValId] = vrm.assignVirtReMatId(NewVReg);
414 vrm.assignVirtReMatId(NewVReg, ReMatIds[I->ValId]);
416 if (!CanDelete || (HasUse && HasDef)) {
417 // If this is a two-addr instruction then its use operands are
418 // rematerializable but its def is not. It should be assigned a
420 vrm.assignVirt2StackSlot(NewVReg, slot);
423 vrm.assignVirt2StackSlot(NewVReg, slot);
426 // create a new register interval for this spill / remat.
427 LiveInterval &nI = getOrCreateInterval(NewVReg);
430 // the spill weight is now infinity as it
431 // cannot be spilled again
432 nI.weight = HUGE_VALF;
435 LiveRange LR(getLoadIndex(index), getUseIndex(index),
436 nI.getNextValue(~0U, 0));
441 LiveRange LR(getDefIndex(index), getStoreIndex(index),
442 nI.getNextValue(~0U, 0));
447 added.push_back(&nI);
449 // update live variables if it is available
451 lv_->addVirtualRegisterKilled(NewVReg, MI);
453 DOUT << "\t\t\t\tadded new interval: ";
454 nI.print(DOUT, mri_);
464 void LiveIntervals::printRegName(unsigned reg) const {
465 if (MRegisterInfo::isPhysicalRegister(reg))
466 cerr << mri_->getName(reg);
468 cerr << "%reg" << reg;
471 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
472 MachineBasicBlock::iterator mi,
474 LiveInterval &interval) {
475 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
476 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
478 // Virtual registers may be defined multiple times (due to phi
479 // elimination and 2-addr elimination). Much of what we do only has to be
480 // done once for the vreg. We use an empty interval to detect the first
481 // time we see a vreg.
482 if (interval.empty()) {
483 // Get the Idx of the defining instructions.
484 unsigned defIndex = getDefIndex(MIIdx);
486 unsigned SrcReg, DstReg;
487 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
488 ValNum = interval.getNextValue(defIndex, 0);
490 ValNum = interval.getNextValue(defIndex, SrcReg);
492 assert(ValNum == 0 && "First value in interval is not 0?");
493 ValNum = 0; // Clue in the optimizer.
495 // Loop over all of the blocks that the vreg is defined in. There are
496 // two cases we have to handle here. The most common case is a vreg
497 // whose lifetime is contained within a basic block. In this case there
498 // will be a single kill, in MBB, which comes after the definition.
499 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
500 // FIXME: what about dead vars?
502 if (vi.Kills[0] != mi)
503 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
505 killIdx = defIndex+1;
507 // If the kill happens after the definition, we have an intra-block
509 if (killIdx > defIndex) {
510 assert(vi.AliveBlocks.none() &&
511 "Shouldn't be alive across any blocks!");
512 LiveRange LR(defIndex, killIdx, ValNum);
513 interval.addRange(LR);
514 DOUT << " +" << LR << "\n";
515 interval.addKillForValNum(ValNum, killIdx);
520 // The other case we handle is when a virtual register lives to the end
521 // of the defining block, potentially live across some blocks, then is
522 // live into some number of blocks, but gets killed. Start by adding a
523 // range that goes from this definition to the end of the defining block.
524 LiveRange NewLR(defIndex,
525 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
527 DOUT << " +" << NewLR;
528 interval.addRange(NewLR);
530 // Iterate over all of the blocks that the variable is completely
531 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
533 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
534 if (vi.AliveBlocks[i]) {
535 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
537 LiveRange LR(getMBBStartIdx(i),
538 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
540 interval.addRange(LR);
546 // Finally, this virtual register is live from the start of any killing
547 // block to the 'use' slot of the killing instruction.
548 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
549 MachineInstr *Kill = vi.Kills[i];
550 unsigned killIdx = getUseIndex(getInstructionIndex(Kill))+1;
551 LiveRange LR(getMBBStartIdx(Kill->getParent()),
553 interval.addRange(LR);
554 interval.addKillForValNum(ValNum, killIdx);
559 // If this is the second time we see a virtual register definition, it
560 // must be due to phi elimination or two addr elimination. If this is
561 // the result of two address elimination, then the vreg is one of the
562 // def-and-use register operand.
563 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
564 // If this is a two-address definition, then we have already processed
565 // the live range. The only problem is that we didn't realize there
566 // are actually two values in the live interval. Because of this we
567 // need to take the LiveRegion that defines this register and split it
569 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
570 unsigned RedefIndex = getDefIndex(MIIdx);
572 const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex-1);
573 unsigned OldEnd = OldLR->end;
575 // Delete the initial value, which should be short and continuous,
576 // because the 2-addr copy must be in the same MBB as the redef.
577 interval.removeRange(DefIndex, RedefIndex);
579 // Two-address vregs should always only be redefined once. This means
580 // that at this point, there should be exactly one value number in it.
581 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
583 // The new value number (#1) is defined by the instruction we claimed
585 unsigned ValNo = interval.getNextValue(0, 0);
586 interval.copyValNumInfo(ValNo, 0);
588 // Value#0 is now defined by the 2-addr instruction.
589 interval.setDefForValNum(0, RedefIndex);
590 interval.setSrcRegForValNum(0, 0);
592 // Add the new live interval which replaces the range for the input copy.
593 LiveRange LR(DefIndex, RedefIndex, ValNo);
594 DOUT << " replace range with " << LR;
595 interval.addRange(LR);
596 interval.addKillForValNum(ValNo, RedefIndex);
597 interval.removeKillForValNum(ValNo, RedefIndex, OldEnd);
599 // If this redefinition is dead, we need to add a dummy unit live
600 // range covering the def slot.
601 if (lv_->RegisterDefIsDead(mi, interval.reg))
602 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
605 interval.print(DOUT, mri_);
608 // Otherwise, this must be because of phi elimination. If this is the
609 // first redefinition of the vreg that we have seen, go back and change
610 // the live range in the PHI block to be a different value number.
611 if (interval.containsOneValue()) {
612 assert(vi.Kills.size() == 1 &&
613 "PHI elimination vreg should have one kill, the PHI itself!");
615 // Remove the old range that we now know has an incorrect number.
616 MachineInstr *Killer = vi.Kills[0];
617 unsigned Start = getMBBStartIdx(Killer->getParent());
618 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
619 DOUT << " Removing [" << Start << "," << End << "] from: ";
620 interval.print(DOUT, mri_); DOUT << "\n";
621 interval.removeRange(Start, End);
622 interval.addKillForValNum(0, Start+1); // odd # means phi node
623 DOUT << " RESULT: "; interval.print(DOUT, mri_);
625 // Replace the interval with one of a NEW value number. Note that this
626 // value number isn't actually defined by an instruction, weird huh? :)
627 LiveRange LR(Start, End, interval.getNextValue(~0, 0));
628 DOUT << " replace range with " << LR;
629 interval.addRange(LR);
630 interval.addKillForValNum(LR.ValId, End);
631 DOUT << " RESULT: "; interval.print(DOUT, mri_);
634 // In the case of PHI elimination, each variable definition is only
635 // live until the end of the block. We've already taken care of the
636 // rest of the live range.
637 unsigned defIndex = getDefIndex(MIIdx);
640 unsigned SrcReg, DstReg;
641 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
642 ValNum = interval.getNextValue(defIndex, 0);
644 ValNum = interval.getNextValue(defIndex, SrcReg);
646 unsigned killIndex = getInstructionIndex(&mbb->back()) + InstrSlots::NUM;
647 LiveRange LR(defIndex, killIndex, ValNum);
648 interval.addRange(LR);
649 interval.addKillForValNum(ValNum, killIndex-1); // odd # means phi node
657 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
658 MachineBasicBlock::iterator mi,
660 LiveInterval &interval,
662 // A physical register cannot be live across basic block, so its
663 // lifetime must end somewhere in its defining basic block.
664 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
666 unsigned baseIndex = MIIdx;
667 unsigned start = getDefIndex(baseIndex);
668 unsigned end = start;
670 // If it is not used after definition, it is considered dead at
671 // the instruction defining it. Hence its interval is:
672 // [defSlot(def), defSlot(def)+1)
673 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
675 end = getDefIndex(start) + 1;
679 // If it is not dead on definition, it must be killed by a
680 // subsequent instruction. Hence its interval is:
681 // [defSlot(def), useSlot(kill)+1)
682 while (++mi != MBB->end()) {
683 baseIndex += InstrSlots::NUM;
684 if (lv_->KillsRegister(mi, interval.reg)) {
686 end = getUseIndex(baseIndex) + 1;
688 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
689 // Another instruction redefines the register before it is ever read.
690 // Then the register is essentially dead at the instruction that defines
691 // it. Hence its interval is:
692 // [defSlot(def), defSlot(def)+1)
694 end = getDefIndex(start) + 1;
699 // The only case we should have a dead physreg here without a killing or
700 // instruction where we know it's dead is if it is live-in to the function
702 assert(!SrcReg && "physreg was not killed in defining block!");
703 end = getDefIndex(start) + 1; // It's dead.
706 assert(start < end && "did not find end of interval?");
708 // Already exists? Extend old live interval.
709 LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
710 unsigned Id = (OldLR != interval.end())
711 ? OldLR->ValId : interval.getNextValue(start, SrcReg);
712 LiveRange LR(start, end, Id);
713 interval.addRange(LR);
714 interval.addKillForValNum(LR.ValId, end);
715 DOUT << " +" << LR << '\n';
718 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
719 MachineBasicBlock::iterator MI,
722 if (MRegisterInfo::isVirtualRegister(reg))
723 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
724 else if (allocatableRegs_[reg]) {
725 unsigned SrcReg, DstReg;
726 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
728 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
729 // Def of a register also defines its sub-registers.
730 for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
731 // Avoid processing some defs more than once.
732 if (!MI->findRegisterDefOperand(*AS))
733 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
737 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
739 LiveInterval &interval, bool isAlias) {
740 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
742 // Look for kills, if it reaches a def before it's killed, then it shouldn't
743 // be considered a livein.
744 MachineBasicBlock::iterator mi = MBB->begin();
745 unsigned baseIndex = MIIdx;
746 unsigned start = baseIndex;
747 unsigned end = start;
748 while (mi != MBB->end()) {
749 if (lv_->KillsRegister(mi, interval.reg)) {
751 end = getUseIndex(baseIndex) + 1;
753 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
754 // Another instruction redefines the register before it is ever read.
755 // Then the register is essentially dead at the instruction that defines
756 // it. Hence its interval is:
757 // [defSlot(def), defSlot(def)+1)
759 end = getDefIndex(start) + 1;
763 baseIndex += InstrSlots::NUM;
768 // Live-in register might not be used at all.
772 end = getDefIndex(MIIdx) + 1;
774 DOUT << " live through";
779 LiveRange LR(start, end, interval.getNextValue(start, 0));
780 interval.addRange(LR);
781 interval.addKillForValNum(LR.ValId, end);
782 DOUT << " +" << LR << '\n';
785 /// computeIntervals - computes the live intervals for virtual
786 /// registers. for some ordering of the machine instructions [1,N] a
787 /// live interval is an interval [i, j) where 1 <= i <= j < N for
788 /// which a variable is live
789 void LiveIntervals::computeIntervals() {
790 DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
791 << "********** Function: "
792 << ((Value*)mf_->getFunction())->getName() << '\n';
793 // Track the index of the current machine instr.
794 unsigned MIIndex = 0;
795 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
797 MachineBasicBlock *MBB = MBBI;
798 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
800 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
802 if (MBB->livein_begin() != MBB->livein_end()) {
803 // Create intervals for live-ins to this BB first.
804 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
805 LE = MBB->livein_end(); LI != LE; ++LI) {
806 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
807 // Multiple live-ins can alias the same register.
808 for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
809 if (!hasInterval(*AS))
810 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
815 for (; MI != miEnd; ++MI) {
816 DOUT << MIIndex << "\t" << *MI;
819 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
820 MachineOperand &MO = MI->getOperand(i);
821 // handle register defs - build intervals
822 if (MO.isRegister() && MO.getReg() && MO.isDef())
823 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
826 MIIndex += InstrSlots::NUM;
831 LiveInterval LiveIntervals::createInterval(unsigned reg) {
832 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
834 return LiveInterval(reg, Weight);