1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/DenseSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
41 // Hidden options for help debugging.
42 static cl::opt<bool> DisableReMat("disable-rematerialization",
43 cl::init(false), cl::Hidden);
45 STATISTIC(numIntervals , "Number of original intervals");
47 char LiveIntervals::ID = 0;
48 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
50 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
53 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
54 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
55 "Live Interval Analysis", false, false)
57 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<AliasAnalysis>();
60 AU.addPreserved<AliasAnalysis>();
61 AU.addRequired<LiveVariables>();
62 AU.addPreserved<LiveVariables>();
63 AU.addPreservedID(MachineLoopInfoID);
64 AU.addPreservedID(MachineDominatorsID);
65 AU.addPreserved<SlotIndexes>();
66 AU.addRequiredTransitive<SlotIndexes>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 void LiveIntervals::releaseMemory() {
71 // Free the live intervals themselves.
72 for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
73 E = r2iMap_.end(); I != E; ++I)
79 RegMaskBlocks.clear();
81 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
82 VNInfoAllocator.Reset();
85 /// runOnMachineFunction - Register allocate the whole function
87 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
89 mri_ = &mf_->getRegInfo();
90 tm_ = &fn.getTarget();
91 tri_ = tm_->getRegisterInfo();
92 tii_ = tm_->getInstrInfo();
93 aa_ = &getAnalysis<AliasAnalysis>();
94 lv_ = &getAnalysis<LiveVariables>();
95 indexes_ = &getAnalysis<SlotIndexes>();
96 allocatableRegs_ = tri_->getAllocatableSet(fn);
97 reservedRegs_ = tri_->getReservedRegs(fn);
101 numIntervals += getNumIntervals();
107 /// print - Implement the dump method.
108 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
109 OS << "********** INTERVALS **********\n";
111 // Dump the physregs.
112 for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
113 if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
118 // Dump the virtregs.
119 for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
120 if (const LiveInterval *LI =
121 r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
129 void LiveIntervals::printInstrs(raw_ostream &OS) const {
130 OS << "********** MACHINEINSTRS **********\n";
131 mf_->print(OS, indexes_);
134 void LiveIntervals::dumpInstrs() const {
139 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
140 unsigned Reg = MI.getOperand(MOIdx).getReg();
141 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
142 const MachineOperand &MO = MI.getOperand(i);
145 if (MO.getReg() == Reg && MO.isDef()) {
146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
147 MI.getOperand(MOIdx).getSubReg() &&
148 (MO.getSubReg() || MO.isImplicit()));
155 /// isPartialRedef - Return true if the specified def at the specific index is
156 /// partially re-defining the specified live interval. A common case of this is
157 /// a definition of the sub-register.
158 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
159 LiveInterval &interval) {
160 if (!MO.getSubReg() || MO.isEarlyClobber())
163 SlotIndex RedefIndex = MIIdx.getRegSlot();
164 const LiveRange *OldLR =
165 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
173 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
174 MachineBasicBlock::iterator mi,
178 LiveInterval &interval) {
179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
181 // Virtual registers may be defined multiple times (due to phi
182 // elimination and 2-addr elimination). Much of what we do only has to be
183 // done once for the vreg. We use an empty interval to detect the first
184 // time we see a vreg.
185 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
186 if (interval.empty()) {
187 // Get the Idx of the defining instructions.
188 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
190 // Make sure the first definition is not a partial redefinition.
191 assert(!MO.readsReg() && "First def cannot also read virtual register "
192 "missing <undef> flag?");
194 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
195 assert(ValNo->id == 0 && "First value in interval is not 0?");
197 // Loop over all of the blocks that the vreg is defined in. There are
198 // two cases we have to handle here. The most common case is a vreg
199 // whose lifetime is contained within a basic block. In this case there
200 // will be a single kill, in MBB, which comes after the definition.
201 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
202 // FIXME: what about dead vars?
204 if (vi.Kills[0] != mi)
205 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
207 killIdx = defIndex.getDeadSlot();
209 // If the kill happens after the definition, we have an intra-block
211 if (killIdx > defIndex) {
212 assert(vi.AliveBlocks.empty() &&
213 "Shouldn't be alive across any blocks!");
214 LiveRange LR(defIndex, killIdx, ValNo);
215 interval.addRange(LR);
216 DEBUG(dbgs() << " +" << LR << "\n");
221 // The other case we handle is when a virtual register lives to the end
222 // of the defining block, potentially live across some blocks, then is
223 // live into some number of blocks, but gets killed. Start by adding a
224 // range that goes from this definition to the end of the defining block.
225 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
226 DEBUG(dbgs() << " +" << NewLR);
227 interval.addRange(NewLR);
229 bool PHIJoin = lv_->isPHIJoin(interval.reg);
232 // A phi join register is killed at the end of the MBB and revived as a new
233 // valno in the killing blocks.
234 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
235 DEBUG(dbgs() << " phi-join");
236 ValNo->setHasPHIKill(true);
238 // Iterate over all of the blocks that the variable is completely
239 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
241 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
242 E = vi.AliveBlocks.end(); I != E; ++I) {
243 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
244 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
245 interval.addRange(LR);
246 DEBUG(dbgs() << " +" << LR);
250 // Finally, this virtual register is live from the start of any killing
251 // block to the 'use' slot of the killing instruction.
252 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
253 MachineInstr *Kill = vi.Kills[i];
254 SlotIndex Start = getMBBStartIdx(Kill->getParent());
255 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
257 // Create interval with one of a NEW value number. Note that this value
258 // number isn't actually defined by an instruction, weird huh? :)
260 assert(getInstructionFromIndex(Start) == 0 &&
261 "PHI def index points at actual instruction.");
262 ValNo = interval.getNextValue(Start, VNInfoAllocator);
263 ValNo->setIsPHIDef(true);
265 LiveRange LR(Start, killIdx, ValNo);
266 interval.addRange(LR);
267 DEBUG(dbgs() << " +" << LR);
271 if (MultipleDefsBySameMI(*mi, MOIdx))
272 // Multiple defs of the same virtual register by the same instruction.
273 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
274 // This is likely due to elimination of REG_SEQUENCE instructions. Return
275 // here since there is nothing to do.
278 // If this is the second time we see a virtual register definition, it
279 // must be due to phi elimination or two addr elimination. If this is
280 // the result of two address elimination, then the vreg is one of the
281 // def-and-use register operand.
283 // It may also be partial redef like this:
284 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
285 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
286 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
287 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
288 // If this is a two-address definition, then we have already processed
289 // the live range. The only problem is that we didn't realize there
290 // are actually two values in the live interval. Because of this we
291 // need to take the LiveRegion that defines this register and split it
293 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
295 const LiveRange *OldLR =
296 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
297 VNInfo *OldValNo = OldLR->valno;
298 SlotIndex DefIndex = OldValNo->def.getRegSlot();
300 // Delete the previous value, which should be short and continuous,
301 // because the 2-addr copy must be in the same MBB as the redef.
302 interval.removeRange(DefIndex, RedefIndex);
304 // The new value number (#1) is defined by the instruction we claimed
306 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
308 // Value#0 is now defined by the 2-addr instruction.
309 OldValNo->def = RedefIndex;
311 // Add the new live interval which replaces the range for the input copy.
312 LiveRange LR(DefIndex, RedefIndex, ValNo);
313 DEBUG(dbgs() << " replace range with " << LR);
314 interval.addRange(LR);
316 // If this redefinition is dead, we need to add a dummy unit live
317 // range covering the def slot.
319 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
323 dbgs() << " RESULT: ";
324 interval.print(dbgs(), tri_);
326 } else if (lv_->isPHIJoin(interval.reg)) {
327 // In the case of PHI elimination, each variable definition is only
328 // live until the end of the block. We've already taken care of the
329 // rest of the live range.
331 SlotIndex defIndex = MIIdx.getRegSlot();
332 if (MO.isEarlyClobber())
333 defIndex = MIIdx.getRegSlot(true);
335 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
337 SlotIndex killIndex = getMBBEndIdx(mbb);
338 LiveRange LR(defIndex, killIndex, ValNo);
339 interval.addRange(LR);
340 ValNo->setHasPHIKill(true);
341 DEBUG(dbgs() << " phi-join +" << LR);
343 llvm_unreachable("Multiply defined register");
347 DEBUG(dbgs() << '\n');
350 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
351 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
352 SE = MBB->succ_end();
354 const MachineBasicBlock* succ = *SI;
355 if (succ->isLiveIn(Reg))
361 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
362 MachineBasicBlock::iterator mi,
365 LiveInterval &interval) {
366 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
368 SlotIndex baseIndex = MIIdx;
369 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
370 SlotIndex end = start;
372 // If it is not used after definition, it is considered dead at
373 // the instruction defining it. Hence its interval is:
374 // [defSlot(def), defSlot(def)+1)
375 // For earlyclobbers, the defSlot was pushed back one; the extra
376 // advance below compensates.
378 DEBUG(dbgs() << " dead");
379 end = start.getDeadSlot();
383 // If it is not dead on definition, it must be killed by a
384 // subsequent instruction. Hence its interval is:
385 // [defSlot(def), useSlot(kill)+1)
386 baseIndex = baseIndex.getNextIndex();
387 while (++mi != MBB->end()) {
389 if (mi->isDebugValue())
391 if (getInstructionFromIndex(baseIndex) == 0)
392 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
394 if (mi->killsRegister(interval.reg, tri_)) {
395 DEBUG(dbgs() << " killed");
396 end = baseIndex.getRegSlot();
399 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
401 if (mi->isRegTiedToUseOperand(DefIdx)) {
402 // Two-address instruction.
403 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
405 // Another instruction redefines the register before it is ever read.
406 // Then the register is essentially dead at the instruction that
407 // defines it. Hence its interval is:
408 // [defSlot(def), defSlot(def)+1)
409 DEBUG(dbgs() << " dead");
410 end = start.getDeadSlot();
416 baseIndex = baseIndex.getNextIndex();
419 // If we get here the register *should* be live out.
420 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
422 // FIXME: We need saner rules for reserved regs.
423 if (isReserved(interval.reg)) {
424 end = start.getDeadSlot();
426 // Unreserved, unallocable registers like EFLAGS can be live across basic
428 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
429 "Unreserved reg not live-out?");
430 end = getMBBEndIdx(MBB);
433 assert(start < end && "did not find end of interval?");
435 // Already exists? Extend old live interval.
436 VNInfo *ValNo = interval.getVNInfoAt(start);
437 bool Extend = ValNo != 0;
439 ValNo = interval.getNextValue(start, VNInfoAllocator);
440 LiveRange LR(start, end, ValNo);
441 interval.addRange(LR);
442 DEBUG(dbgs() << " +" << LR << '\n');
445 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
446 MachineBasicBlock::iterator MI,
450 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
451 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
452 getOrCreateInterval(MO.getReg()));
454 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
455 getOrCreateInterval(MO.getReg()));
458 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
460 LiveInterval &interval) {
461 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
462 "Only physical registers can be live in.");
463 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
464 MBB->isLandingPad()) &&
465 "Allocatable live-ins only valid for entry blocks and landing pads.");
467 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
469 // Look for kills, if it reaches a def before it's killed, then it shouldn't
470 // be considered a livein.
471 MachineBasicBlock::iterator mi = MBB->begin();
472 MachineBasicBlock::iterator E = MBB->end();
473 // Skip over DBG_VALUE at the start of the MBB.
474 if (mi != E && mi->isDebugValue()) {
475 while (++mi != E && mi->isDebugValue())
478 // MBB is empty except for DBG_VALUE's.
482 SlotIndex baseIndex = MIIdx;
483 SlotIndex start = baseIndex;
484 if (getInstructionFromIndex(baseIndex) == 0)
485 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
487 SlotIndex end = baseIndex;
488 bool SeenDefUse = false;
491 if (mi->killsRegister(interval.reg, tri_)) {
492 DEBUG(dbgs() << " killed");
493 end = baseIndex.getRegSlot();
496 } else if (mi->modifiesRegister(interval.reg, tri_)) {
497 // Another instruction redefines the register before it is ever read.
498 // Then the register is essentially dead at the instruction that defines
499 // it. Hence its interval is:
500 // [defSlot(def), defSlot(def)+1)
501 DEBUG(dbgs() << " dead");
502 end = start.getDeadSlot();
507 while (++mi != E && mi->isDebugValue())
508 // Skip over DBG_VALUE.
511 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
514 // Live-in register might not be used at all.
516 if (isAllocatable(interval.reg) ||
517 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
518 // Allocatable registers are never live through.
519 // Non-allocatable registers that aren't live into any successors also
520 // aren't live through.
521 DEBUG(dbgs() << " dead");
524 // If we get here the register is non-allocatable and live into some
525 // successor. We'll conservatively assume it's live-through.
526 DEBUG(dbgs() << " live through");
527 end = getMBBEndIdx(MBB);
531 SlotIndex defIdx = getMBBStartIdx(MBB);
532 assert(getInstructionFromIndex(defIdx) == 0 &&
533 "PHI def index points at actual instruction.");
534 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
535 vni->setIsPHIDef(true);
536 LiveRange LR(start, end, vni);
538 interval.addRange(LR);
539 DEBUG(dbgs() << " +" << LR << '\n');
542 /// computeIntervals - computes the live intervals for virtual
543 /// registers. for some ordering of the machine instructions [1,N] a
544 /// live interval is an interval [i, j) where 1 <= i <= j < N for
545 /// which a variable is live
546 void LiveIntervals::computeIntervals() {
547 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
548 << "********** Function: "
549 << ((Value*)mf_->getFunction())->getName() << '\n');
551 RegMaskBlocks.resize(mf_->getNumBlockIDs());
553 SmallVector<unsigned, 8> UndefUses;
554 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
556 MachineBasicBlock *MBB = MBBI;
557 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
562 // Track the index of the current machine instr.
563 SlotIndex MIIndex = getMBBStartIdx(MBB);
564 DEBUG(dbgs() << "BB#" << MBB->getNumber()
565 << ":\t\t# derived from " << MBB->getName() << "\n");
567 // Create intervals for live-ins to this BB first.
568 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
569 LE = MBB->livein_end(); LI != LE; ++LI) {
570 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
573 // Skip over empty initial indices.
574 if (getInstructionFromIndex(MIIndex) == 0)
575 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
577 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
579 DEBUG(dbgs() << MIIndex << "\t" << *MI);
580 if (MI->isDebugValue())
582 assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
583 "Lost SlotIndex synchronization");
586 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
587 MachineOperand &MO = MI->getOperand(i);
589 // Collect register masks.
590 if (MO.isRegMask()) {
591 RegMaskSlots.push_back(MIIndex.getRegSlot());
592 RegMaskBits.push_back(MO.getRegMask());
596 if (!MO.isReg() || !MO.getReg())
599 // handle register defs - build intervals
601 handleRegisterDef(MBB, MI, MIIndex, MO, i);
602 else if (MO.isUndef())
603 UndefUses.push_back(MO.getReg());
606 // Move to the next instr slot.
607 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
610 // Compute the number of register mask instructions in this block.
611 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
612 RMB.second = RegMaskSlots.size() - RMB.first;;
615 // Create empty intervals for registers defined by implicit_def's (except
616 // for those implicit_def that define values which are liveout of their
618 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
619 unsigned UndefReg = UndefUses[i];
620 (void)getOrCreateInterval(UndefReg);
624 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
625 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
626 return new LiveInterval(reg, Weight);
629 /// dupInterval - Duplicate a live interval. The caller is responsible for
630 /// managing the allocated memory.
631 LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
632 LiveInterval *NewLI = createInterval(li->reg);
633 NewLI->Copy(*li, mri_, getVNInfoAllocator());
637 /// shrinkToUses - After removing some uses of a register, shrink its live
638 /// range to just the remaining uses. This method does not compute reaching
639 /// defs for new uses, and it doesn't remove dead defs.
640 bool LiveIntervals::shrinkToUses(LiveInterval *li,
641 SmallVectorImpl<MachineInstr*> *dead) {
642 DEBUG(dbgs() << "Shrink: " << *li << '\n');
643 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
644 && "Can only shrink virtual registers");
645 // Find all the values used, including PHI kills.
646 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
648 // Blocks that have already been added to WorkList as live-out.
649 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
651 // Visit all instructions reading li->reg.
652 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
653 MachineInstr *UseMI = I.skipInstruction();) {
654 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
656 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
657 LiveRangeQuery LRQ(*li, Idx);
658 VNInfo *VNI = LRQ.valueIn();
660 // This shouldn't happen: readsVirtualRegister returns true, but there is
661 // no live value. It is likely caused by a target getting <undef> flags
663 DEBUG(dbgs() << Idx << '\t' << *UseMI
664 << "Warning: Instr claims to read non-existent value in "
668 // Special case: An early-clobber tied operand reads and writes the
669 // register one slot early.
670 if (VNInfo *DefVNI = LRQ.valueDefined())
673 WorkList.push_back(std::make_pair(Idx, VNI));
676 // Create a new live interval with only minimal live segments per def.
677 LiveInterval NewLI(li->reg, 0);
678 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
683 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
686 // Keep track of the PHIs that are in use.
687 SmallPtrSet<VNInfo*, 8> UsedPHIs;
689 // Extend intervals to reach all uses in WorkList.
690 while (!WorkList.empty()) {
691 SlotIndex Idx = WorkList.back().first;
692 VNInfo *VNI = WorkList.back().second;
694 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
695 SlotIndex BlockStart = getMBBStartIdx(MBB);
697 // Extend the live range for VNI to be live at Idx.
698 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
700 assert(ExtVNI == VNI && "Unexpected existing value number");
701 // Is this a PHIDef we haven't seen before?
702 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
704 // The PHI is live, make sure the predecessors are live-out.
705 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
706 PE = MBB->pred_end(); PI != PE; ++PI) {
707 if (!LiveOut.insert(*PI))
709 SlotIndex Stop = getMBBEndIdx(*PI);
710 // A predecessor is not required to have a live-out value for a PHI.
711 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
712 WorkList.push_back(std::make_pair(Stop, PVNI));
717 // VNI is live-in to MBB.
718 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
719 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
721 // Make sure VNI is live-out from the predecessors.
722 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
723 PE = MBB->pred_end(); PI != PE; ++PI) {
724 if (!LiveOut.insert(*PI))
726 SlotIndex Stop = getMBBEndIdx(*PI);
727 assert(li->getVNInfoBefore(Stop) == VNI &&
728 "Wrong value out of predecessor");
729 WorkList.push_back(std::make_pair(Stop, VNI));
733 // Handle dead values.
734 bool CanSeparate = false;
735 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
740 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
741 assert(LII != NewLI.end() && "Missing live range for PHI");
742 if (LII->end != VNI->def.getDeadSlot())
744 if (VNI->isPHIDef()) {
745 // This is a dead PHI. Remove it.
746 VNI->setIsUnused(true);
747 NewLI.removeRange(*LII);
748 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
751 // This is a dead def. Make sure the instruction knows.
752 MachineInstr *MI = getInstructionFromIndex(VNI->def);
753 assert(MI && "No instruction defining live value");
754 MI->addRegisterDead(li->reg, tri_);
755 if (dead && MI->allDefsAreDead()) {
756 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
762 // Move the trimmed ranges back.
763 li->ranges.swap(NewLI.ranges);
764 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
769 //===----------------------------------------------------------------------===//
770 // Register allocator hooks.
773 void LiveIntervals::addKillFlags() {
774 for (iterator I = begin(), E = end(); I != E; ++I) {
775 unsigned Reg = I->first;
776 if (TargetRegisterInfo::isPhysicalRegister(Reg))
778 if (mri_->reg_nodbg_empty(Reg))
780 LiveInterval *LI = I->second;
782 // Every instruction that kills Reg corresponds to a live range end point.
783 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
785 // A block index indicates an MBB edge.
786 if (RI->end.isBlock())
788 MachineInstr *MI = getInstructionFromIndex(RI->end);
791 MI->addRegisterKilled(Reg, NULL);
796 /// getReMatImplicitUse - If the remat definition MI has one (for now, we only
797 /// allow one) virtual register operand, then its uses are implicitly using
798 /// the register. Returns the virtual register.
799 unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
800 MachineInstr *MI) const {
802 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
803 MachineOperand &MO = MI->getOperand(i);
804 if (!MO.isReg() || !MO.isUse())
806 unsigned Reg = MO.getReg();
807 if (Reg == 0 || Reg == li.reg)
810 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
813 break; // Found vreg operand - leave the loop.
818 /// isValNoAvailableAt - Return true if the val# of the specified interval
819 /// which reaches the given instruction also reaches the specified use index.
820 bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
821 SlotIndex UseIdx) const {
822 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
823 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
826 /// isReMaterializable - Returns true if the definition MI of the specified
827 /// val# of the specified interval is re-materializable.
829 LiveIntervals::isReMaterializable(const LiveInterval &li,
830 const VNInfo *ValNo, MachineInstr *MI,
831 const SmallVectorImpl<LiveInterval*> *SpillIs,
836 if (!tii_->isTriviallyReMaterializable(MI, aa_))
839 // Target-specific code can mark an instruction as being rematerializable
840 // if it has one virtual reg use, though it had better be something like
841 // a PIC base register which is likely to be live everywhere.
842 unsigned ImpUse = getReMatImplicitUse(li, MI);
844 const LiveInterval &ImpLi = getInterval(ImpUse);
845 for (MachineRegisterInfo::use_nodbg_iterator
846 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
848 MachineInstr *UseMI = &*ri;
849 SlotIndex UseIdx = getInstructionIndex(UseMI);
850 if (li.getVNInfoAt(UseIdx) != ValNo)
852 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
856 // If a register operand of the re-materialized instruction is going to
857 // be spilled next, then it's not legal to re-materialize this instruction.
859 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
860 if (ImpUse == (*SpillIs)[i]->reg)
866 /// isReMaterializable - Returns true if every definition of MI of every
867 /// val# of the specified interval is re-materializable.
869 LiveIntervals::isReMaterializable(const LiveInterval &li,
870 const SmallVectorImpl<LiveInterval*> *SpillIs,
873 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
875 const VNInfo *VNI = *i;
877 continue; // Dead val#.
878 // Is the def for the val# rematerializable?
879 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
882 bool DefIsLoad = false;
884 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
892 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
893 // A local live range must be fully contained inside the block, meaning it is
894 // defined and killed at instructions, not at block boundaries. It is not
895 // live in or or out of any block.
897 // It is technically possible to have a PHI-defined live range identical to a
898 // single block, but we are going to return false in that case.
900 SlotIndex Start = LI.beginIndex();
904 SlotIndex Stop = LI.endIndex();
908 // getMBBFromIndex doesn't need to search the MBB table when both indexes
909 // belong to proper instructions.
910 MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
911 MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
912 return MBB1 == MBB2 ? MBB1 : NULL;
916 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
917 // Limit the loop depth ridiculousness.
921 // The loop depth is used to roughly estimate the number of times the
922 // instruction is executed. Something like 10^d is simple, but will quickly
923 // overflow a float. This expression behaves like 10^d for small d, but is
924 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
925 // headroom before overflow.
926 // By the way, powf() might be unavailable here. For consistency,
927 // We may take pow(double,double).
928 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
930 return (isDef + isUse) * lc;
933 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
934 MachineInstr* startInst) {
935 LiveInterval& Interval = getOrCreateInterval(reg);
936 VNInfo* VN = Interval.getNextValue(
937 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
938 getVNInfoAllocator());
939 VN->setHasPHIKill(true);
941 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
942 getMBBEndIdx(startInst->getParent()), VN);
943 Interval.addRange(LR);
949 //===----------------------------------------------------------------------===//
950 // Register mask functions
951 //===----------------------------------------------------------------------===//
953 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
954 BitVector &UsableRegs) {
957 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
959 // Use a smaller arrays for local live ranges.
960 ArrayRef<SlotIndex> Slots;
961 ArrayRef<const uint32_t*> Bits;
962 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
963 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
964 Bits = getRegMaskBitsInBlock(MBB->getNumber());
966 Slots = getRegMaskSlots();
967 Bits = getRegMaskBits();
970 // We are going to enumerate all the register mask slots contained in LI.
971 // Start with a binary search of RegMaskSlots to find a starting point.
972 ArrayRef<SlotIndex>::iterator SlotI =
973 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
974 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
976 // No slots in range, LI begins after the last call.
982 assert(*SlotI >= LiveI->start);
983 // Loop over all slots overlapping this segment.
984 while (*SlotI < LiveI->end) {
985 // *SlotI overlaps LI. Collect mask bits.
987 // This is the first overlap. Initialize UsableRegs to all ones.
989 UsableRegs.resize(tri_->getNumRegs(), true);
992 // Remove usable registers clobbered by this mask.
993 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
994 if (++SlotI == SlotE)
997 // *SlotI is beyond the current LI segment.
998 LiveI = LI.advanceTo(LiveI, *SlotI);
1001 // Advance SlotI until it overlaps.
1002 while (*SlotI < LiveI->start)
1003 if (++SlotI == SlotE)
1008 //===----------------------------------------------------------------------===//
1009 // IntervalUpdate class.
1010 //===----------------------------------------------------------------------===//
1012 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1013 class LiveIntervals::HMEditor {
1016 const MachineRegisterInfo& MRI;
1017 const TargetRegisterInfo& TRI;
1020 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1021 typedef DenseSet<IntRangePair> RangeSet;
1028 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
1030 typedef DenseMap<unsigned, RegRanges> BundleRanges;
1033 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1034 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1035 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1037 // Update intervals for all operands of MI from OldIdx to NewIdx.
1038 // This assumes that MI used to be at OldIdx, and now resides at
1040 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
1041 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
1043 // Collect the operands.
1044 RangeSet Entering, Internal, Exiting;
1045 bool hasRegMaskOp = false;
1046 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1048 // To keep the LiveRanges valid within an interval, move the ranges closest
1049 // to the destination first. This prevents ranges from overlapping, to that
1050 // APIs like removeRange still work.
1051 if (NewIdx < OldIdx) {
1052 moveAllEnteringFrom(OldIdx, Entering);
1053 moveAllInternalFrom(OldIdx, Internal);
1054 moveAllExitingFrom(OldIdx, Exiting);
1057 moveAllExitingFrom(OldIdx, Exiting);
1058 moveAllInternalFrom(OldIdx, Internal);
1059 moveAllEnteringFrom(OldIdx, Entering);
1063 updateRegMaskSlots(OldIdx);
1066 LIValidator validator;
1067 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1068 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1069 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1070 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1075 // Update intervals for all operands of MI to refer to BundleStart's
1077 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1078 if (MI == BundleStart)
1079 return; // Bundling instr with itself - nothing to do.
1081 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1082 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1083 "SlotIndex <-> Instruction mapping broken for MI");
1085 // Collect all ranges already in the bundle.
1086 MachineBasicBlock::instr_iterator BII(BundleStart);
1087 RangeSet Entering, Internal, Exiting;
1088 bool hasRegMaskOp = false;
1089 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1090 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1091 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1094 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1095 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1098 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1103 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1104 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1106 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1107 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1108 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1110 moveAllEnteringFromInto(OldIdx, Entering, BR);
1111 moveAllInternalFromInto(OldIdx, Internal, BR);
1112 moveAllExitingFromInto(OldIdx, Exiting, BR);
1116 LIValidator validator;
1117 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1118 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1119 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1120 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1129 DenseSet<const LiveInterval*> Checked, Bogus;
1131 void operator()(const IntRangePair& P) {
1132 const LiveInterval* LI = P.first;
1133 if (Checked.count(LI))
1138 SlotIndex LastEnd = LI->begin()->start;
1139 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1140 LRI != LRE; ++LRI) {
1141 const LiveRange& LR = *LRI;
1142 if (LastEnd > LR.start || LR.start >= LR.end)
1148 bool rangesOk() const {
1149 return Bogus.empty();
1154 // Collect IntRangePairs for all operands of MI that may need fixing.
1155 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1157 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1158 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1159 hasRegMaskOp = false;
1160 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1161 MOE = MI->operands_end();
1162 MOI != MOE; ++MOI) {
1163 const MachineOperand& MO = *MOI;
1165 if (MO.isRegMask()) {
1166 hasRegMaskOp = true;
1170 if (!MO.isReg() || MO.getReg() == 0)
1173 unsigned Reg = MO.getReg();
1175 // TODO: Currently we're skipping uses that are reserved or have no
1176 // interval, but we're not updating their kills. This should be
1178 if (!LIS.hasInterval(Reg) ||
1179 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1182 LiveInterval* LI = &LIS.getInterval(Reg);
1184 if (MO.readsReg()) {
1185 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1187 Entering.insert(std::make_pair(LI, LR));
1190 if (MO.isEarlyClobber()) {
1191 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
1192 assert(LR != 0 && "No EC range?");
1193 if (LR->end > OldIdx.getDeadSlot())
1194 Exiting.insert(std::make_pair(LI, LR));
1196 Internal.insert(std::make_pair(LI, LR));
1197 } else if (MO.isDead()) {
1198 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1199 assert(LR != 0 && "No dead-def range?");
1200 Internal.insert(std::make_pair(LI, LR));
1202 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
1203 assert(LR && LR->end > OldIdx.getDeadSlot() &&
1204 "Non-dead-def should have live range exiting.");
1205 Exiting.insert(std::make_pair(LI, LR));
1211 // Collect IntRangePairs for all operands of MI that may need fixing.
1212 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
1213 RangeSet& Exiting, SlotIndex MIStartIdx,
1214 SlotIndex MIEndIdx) {
1215 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1216 MOE = MI->operands_end();
1217 MOI != MOE; ++MOI) {
1218 const MachineOperand& MO = *MOI;
1219 assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
1220 if (!MO.isReg() || MO.getReg() == 0)
1223 unsigned Reg = MO.getReg();
1225 // TODO: Currently we're skipping uses that are reserved or have no
1226 // interval, but we're not updating their kills. This should be
1228 if (!LIS.hasInterval(Reg) ||
1229 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1232 LiveInterval* LI = &LIS.getInterval(Reg);
1234 if (MO.readsReg()) {
1235 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
1237 Entering.insert(std::make_pair(LI, LR));
1240 assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles.");
1241 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1242 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
1243 assert(LR != 0 && "Internal ranges not allowed in bundles.");
1244 Exiting.insert(std::make_pair(LI, LR));
1249 BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) {
1252 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1254 LiveInterval* LI = EI->first;
1255 LiveRange* LR = EI->second;
1256 BR[LI->reg].Use = LR;
1259 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1261 LiveInterval* LI = II->first;
1262 LiveRange* LR = II->second;
1263 if (LR->end.isDead()) {
1264 BR[LI->reg].Dead = LR;
1266 BR[LI->reg].EC = LR;
1270 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1272 LiveInterval* LI = EI->first;
1273 LiveRange* LR = EI->second;
1274 BR[LI->reg].Def = LR;
1280 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1281 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1282 if (!OldKillMI->killsRegister(reg))
1283 return; // Bail out if we don't have kill flags on the old register.
1284 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1285 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1286 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1287 OldKillMI->clearRegisterKills(reg, &TRI);
1288 NewKillMI->addRegisterKilled(reg, &TRI);
1291 void updateRegMaskSlots(SlotIndex OldIdx) {
1292 SmallVectorImpl<SlotIndex>::iterator RI =
1293 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1295 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1297 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1298 "RegSlots out of order. Did you move one call across another?");
1301 // Return the last use of reg between NewIdx and OldIdx.
1302 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1303 SlotIndex LastUse = NewIdx;
1304 for (MachineRegisterInfo::use_nodbg_iterator
1305 UI = MRI.use_nodbg_begin(Reg),
1306 UE = MRI.use_nodbg_end();
1307 UI != UE; UI.skipInstruction()) {
1308 const MachineInstr* MI = &*UI;
1309 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1310 if (InstSlot > LastUse && InstSlot < OldIdx)
1316 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1317 LiveInterval* LI = P.first;
1318 LiveRange* LR = P.second;
1319 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1322 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1323 if (LastUse != NewIdx)
1324 moveKillFlags(LI->reg, NewIdx, LastUse);
1325 LR->end = LastUse.getRegSlot();
1328 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1329 LiveInterval* LI = P.first;
1330 LiveRange* LR = P.second;
1331 // Extend the LiveRange if NewIdx is past the end.
1332 if (NewIdx > LR->end) {
1333 // Move kill flags if OldIdx was not originally the end
1334 // (otherwise LR->end points to an invalid slot).
1335 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1336 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1337 moveKillFlags(LI->reg, LR->end, NewIdx);
1339 LR->end = NewIdx.getRegSlot();
1343 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1344 bool GoingUp = NewIdx < OldIdx;
1347 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1349 moveEnteringUpFrom(OldIdx, *EI);
1351 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1353 moveEnteringDownFrom(OldIdx, *EI);
1357 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1358 LiveInterval* LI = P.first;
1359 LiveRange* LR = P.second;
1360 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1361 LR->end <= OldIdx.getDeadSlot() &&
1362 "Range should be internal to OldIdx.");
1364 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1365 Tmp.valno->def = Tmp.start;
1366 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1367 LI->removeRange(*LR);
1371 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1372 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1374 moveInternalFrom(OldIdx, *II);
1377 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1378 LiveRange* LR = P.second;
1379 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1380 "Range should start in OldIdx.");
1381 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1382 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1383 LR->start = NewStart;
1384 LR->valno->def = NewStart;
1387 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1388 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1390 moveExitingFrom(OldIdx, *EI);
1393 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1395 LiveInterval* LI = P.first;
1396 LiveRange* LR = P.second;
1397 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1399 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1400 "Def in bundle should be def range.");
1401 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1402 "If bundle has use for this reg it should be LR.");
1403 BR[LI->reg].Use = LR;
1407 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1408 moveKillFlags(LI->reg, OldIdx, LastUse);
1410 if (LR->start < NewIdx) {
1411 // Becoming a new entering range.
1412 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1413 "Bundle shouldn't be re-defining reg mid-range.");
1414 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1415 "Bundle shouldn't have different use range for same reg.");
1416 LR->end = LastUse.getRegSlot();
1417 BR[LI->reg].Use = LR;
1419 // Becoming a new Dead-def.
1420 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1421 "Live range starting at unexpected slot.");
1422 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1423 assert(BR[LI->reg].Dead == 0 &&
1424 "Can't have def and dead def of same reg in a bundle.");
1425 LR->end = LastUse.getDeadSlot();
1426 BR[LI->reg].Dead = BR[LI->reg].Def;
1427 BR[LI->reg].Def = 0;
1431 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1433 LiveInterval* LI = P.first;
1434 LiveRange* LR = P.second;
1435 if (NewIdx > LR->end) {
1436 // Range extended to bundle. Add to bundle uses.
1437 // Note: Currently adds kill flags to bundle start.
1438 assert(BR[LI->reg].Use == 0 &&
1439 "Bundle already has use range for reg.");
1440 moveKillFlags(LI->reg, LR->end, NewIdx);
1441 LR->end = NewIdx.getRegSlot();
1442 BR[LI->reg].Use = LR;
1444 assert(BR[LI->reg].Use != 0 &&
1445 "Bundle should already have a use range for reg.");
1449 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1451 bool GoingUp = NewIdx < OldIdx;
1454 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1456 moveEnteringUpFromInto(OldIdx, *EI, BR);
1458 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1460 moveEnteringDownFromInto(OldIdx, *EI, BR);
1464 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1466 // TODO: Sane rules for moving ranges into bundles.
1469 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1471 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1473 moveInternalFromInto(OldIdx, *II, BR);
1476 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1478 LiveInterval* LI = P.first;
1479 LiveRange* LR = P.second;
1481 assert(LR->start.isRegister() &&
1482 "Don't know how to merge exiting ECs into bundles yet.");
1484 if (LR->end > NewIdx.getDeadSlot()) {
1485 // This range is becoming an exiting range on the bundle.
1486 // If there was an old dead-def of this reg, delete it.
1487 if (BR[LI->reg].Dead != 0) {
1488 LI->removeRange(*BR[LI->reg].Dead);
1489 BR[LI->reg].Dead = 0;
1491 assert(BR[LI->reg].Def == 0 &&
1492 "Can't have two defs for the same variable exiting a bundle.");
1493 LR->start = NewIdx.getRegSlot();
1494 LR->valno->def = LR->start;
1495 BR[LI->reg].Def = LR;
1497 // This range is becoming internal to the bundle.
1498 assert(LR->end == NewIdx.getRegSlot() &&
1499 "Can't bundle def whose kill is before the bundle");
1500 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1501 // Already have a def for this. Just delete range.
1502 LI->removeRange(*LR);
1504 // Make range dead, record.
1505 LR->end = NewIdx.getDeadSlot();
1506 BR[LI->reg].Dead = LR;
1507 assert(BR[LI->reg].Use == LR &&
1508 "Range becoming dead should currently be use.");
1510 // In both cases the range is no longer a use on the bundle.
1511 BR[LI->reg].Use = 0;
1515 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1517 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1519 moveExitingFromInto(OldIdx, *EI, BR);
1524 void LiveIntervals::handleMove(MachineInstr* MI) {
1525 SlotIndex OldIndex = indexes_->getInstructionIndex(MI);
1526 indexes_->removeMachineInstrFromMaps(MI);
1527 SlotIndex NewIndex = MI->isInsideBundle() ?
1528 indexes_->getInstructionIndex(MI) :
1529 indexes_->insertMachineInstrInMaps(MI);
1530 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1531 OldIndex < getMBBEndIdx(MI->getParent()) &&
1532 "Cannot handle moves across basic block boundaries.");
1533 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1535 HMEditor HME(*this, *mri_, *tri_, NewIndex);
1536 HME.moveAllRangesFrom(MI, OldIndex);
1539 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) {
1540 SlotIndex NewIndex = indexes_->getInstructionIndex(BundleStart);
1541 HMEditor HME(*this, *mri_, *tri_, NewIndex);
1542 HME.moveAllRangesInto(MI, BundleStart);