1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "LiveRangeCalc.h"
43 // Temporary option to enable regunit liveness.
44 static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden);
46 STATISTIC(numIntervals , "Number of original intervals");
48 char LiveIntervals::ID = 0;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
58 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<AliasAnalysis>();
61 AU.addPreserved<AliasAnalysis>();
62 AU.addRequired<LiveVariables>();
63 AU.addPreserved<LiveVariables>();
64 AU.addPreservedID(MachineLoopInfoID);
66 AU.addRequiredTransitiveID(MachineDominatorsID);
67 AU.addPreservedID(MachineDominatorsID);
68 AU.addPreserved<SlotIndexes>();
69 AU.addRequiredTransitive<SlotIndexes>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
74 DomTree(0), LRCalc(0) {
75 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
78 LiveIntervals::~LiveIntervals() {
82 void LiveIntervals::releaseMemory() {
83 // Free the live intervals themselves.
84 for (DenseMap<unsigned, LiveInterval*>::iterator I = R2IMap.begin(),
85 E = R2IMap.end(); I != E; ++I)
91 RegMaskBlocks.clear();
93 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
94 delete RegUnitIntervals[i];
95 RegUnitIntervals.clear();
97 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
98 VNInfoAllocator.Reset();
101 /// runOnMachineFunction - Register allocate the whole function
103 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
105 MRI = &MF->getRegInfo();
106 TM = &fn.getTarget();
107 TRI = TM->getRegisterInfo();
108 TII = TM->getInstrInfo();
109 AA = &getAnalysis<AliasAnalysis>();
110 LV = &getAnalysis<LiveVariables>();
111 Indexes = &getAnalysis<SlotIndexes>();
113 DomTree = &getAnalysis<MachineDominatorTree>();
114 if (LiveRegUnits && !LRCalc)
115 LRCalc = new LiveRangeCalc();
116 AllocatableRegs = TRI->getAllocatableSet(fn);
117 ReservedRegs = TRI->getReservedRegs(fn);
121 numIntervals += getNumIntervals();
124 computeLiveInRegUnits();
131 /// print - Implement the dump method.
132 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
133 OS << "********** INTERVALS **********\n";
135 // Dump the physregs.
136 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
137 if (const LiveInterval *LI = R2IMap.lookup(Reg))
138 OS << PrintReg(Reg, TRI) << '\t' << *LI << '\n';
140 // Dump the regunits.
141 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
142 if (LiveInterval *LI = RegUnitIntervals[i])
143 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
145 // Dump the virtregs.
146 for (unsigned Reg = 0, RegE = MRI->getNumVirtRegs(); Reg != RegE; ++Reg)
147 if (const LiveInterval *LI =
148 R2IMap.lookup(TargetRegisterInfo::index2VirtReg(Reg)))
149 OS << PrintReg(LI->reg) << '\t' << *LI << '\n';
154 void LiveIntervals::printInstrs(raw_ostream &OS) const {
155 OS << "********** MACHINEINSTRS **********\n";
156 MF->print(OS, Indexes);
159 void LiveIntervals::dumpInstrs() const {
164 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
165 unsigned Reg = MI.getOperand(MOIdx).getReg();
166 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
167 const MachineOperand &MO = MI.getOperand(i);
170 if (MO.getReg() == Reg && MO.isDef()) {
171 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
172 MI.getOperand(MOIdx).getSubReg() &&
173 (MO.getSubReg() || MO.isImplicit()));
180 /// isPartialRedef - Return true if the specified def at the specific index is
181 /// partially re-defining the specified live interval. A common case of this is
182 /// a definition of the sub-register.
183 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
184 LiveInterval &interval) {
185 if (!MO.getSubReg() || MO.isEarlyClobber())
188 SlotIndex RedefIndex = MIIdx.getRegSlot();
189 const LiveRange *OldLR =
190 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
191 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
193 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
198 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
199 MachineBasicBlock::iterator mi,
203 LiveInterval &interval) {
204 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
206 // Virtual registers may be defined multiple times (due to phi
207 // elimination and 2-addr elimination). Much of what we do only has to be
208 // done once for the vreg. We use an empty interval to detect the first
209 // time we see a vreg.
210 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
211 if (interval.empty()) {
212 // Get the Idx of the defining instructions.
213 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
215 // Make sure the first definition is not a partial redefinition.
216 assert(!MO.readsReg() && "First def cannot also read virtual register "
217 "missing <undef> flag?");
219 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
220 assert(ValNo->id == 0 && "First value in interval is not 0?");
222 // Loop over all of the blocks that the vreg is defined in. There are
223 // two cases we have to handle here. The most common case is a vreg
224 // whose lifetime is contained within a basic block. In this case there
225 // will be a single kill, in MBB, which comes after the definition.
226 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
227 // FIXME: what about dead vars?
229 if (vi.Kills[0] != mi)
230 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
232 killIdx = defIndex.getDeadSlot();
234 // If the kill happens after the definition, we have an intra-block
236 if (killIdx > defIndex) {
237 assert(vi.AliveBlocks.empty() &&
238 "Shouldn't be alive across any blocks!");
239 LiveRange LR(defIndex, killIdx, ValNo);
240 interval.addRange(LR);
241 DEBUG(dbgs() << " +" << LR << "\n");
246 // The other case we handle is when a virtual register lives to the end
247 // of the defining block, potentially live across some blocks, then is
248 // live into some number of blocks, but gets killed. Start by adding a
249 // range that goes from this definition to the end of the defining block.
250 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
251 DEBUG(dbgs() << " +" << NewLR);
252 interval.addRange(NewLR);
254 bool PHIJoin = LV->isPHIJoin(interval.reg);
257 // A phi join register is killed at the end of the MBB and revived as a new
258 // valno in the killing blocks.
259 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
260 DEBUG(dbgs() << " phi-join");
261 ValNo->setHasPHIKill(true);
263 // Iterate over all of the blocks that the variable is completely
264 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
266 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
267 E = vi.AliveBlocks.end(); I != E; ++I) {
268 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
269 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
270 interval.addRange(LR);
271 DEBUG(dbgs() << " +" << LR);
275 // Finally, this virtual register is live from the start of any killing
276 // block to the 'use' slot of the killing instruction.
277 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
278 MachineInstr *Kill = vi.Kills[i];
279 SlotIndex Start = getMBBStartIdx(Kill->getParent());
280 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
282 // Create interval with one of a NEW value number. Note that this value
283 // number isn't actually defined by an instruction, weird huh? :)
285 assert(getInstructionFromIndex(Start) == 0 &&
286 "PHI def index points at actual instruction.");
287 ValNo = interval.getNextValue(Start, VNInfoAllocator);
288 ValNo->setIsPHIDef(true);
290 LiveRange LR(Start, killIdx, ValNo);
291 interval.addRange(LR);
292 DEBUG(dbgs() << " +" << LR);
296 if (MultipleDefsBySameMI(*mi, MOIdx))
297 // Multiple defs of the same virtual register by the same instruction.
298 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
299 // This is likely due to elimination of REG_SEQUENCE instructions. Return
300 // here since there is nothing to do.
303 // If this is the second time we see a virtual register definition, it
304 // must be due to phi elimination or two addr elimination. If this is
305 // the result of two address elimination, then the vreg is one of the
306 // def-and-use register operand.
308 // It may also be partial redef like this:
309 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
310 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
311 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
312 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
313 // If this is a two-address definition, then we have already processed
314 // the live range. The only problem is that we didn't realize there
315 // are actually two values in the live interval. Because of this we
316 // need to take the LiveRegion that defines this register and split it
318 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
320 const LiveRange *OldLR =
321 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
322 VNInfo *OldValNo = OldLR->valno;
323 SlotIndex DefIndex = OldValNo->def.getRegSlot();
325 // Delete the previous value, which should be short and continuous,
326 // because the 2-addr copy must be in the same MBB as the redef.
327 interval.removeRange(DefIndex, RedefIndex);
329 // The new value number (#1) is defined by the instruction we claimed
331 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
333 // Value#0 is now defined by the 2-addr instruction.
334 OldValNo->def = RedefIndex;
336 // Add the new live interval which replaces the range for the input copy.
337 LiveRange LR(DefIndex, RedefIndex, ValNo);
338 DEBUG(dbgs() << " replace range with " << LR);
339 interval.addRange(LR);
341 // If this redefinition is dead, we need to add a dummy unit live
342 // range covering the def slot.
344 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
347 DEBUG(dbgs() << " RESULT: " << interval);
348 } else if (LV->isPHIJoin(interval.reg)) {
349 // In the case of PHI elimination, each variable definition is only
350 // live until the end of the block. We've already taken care of the
351 // rest of the live range.
353 SlotIndex defIndex = MIIdx.getRegSlot();
354 if (MO.isEarlyClobber())
355 defIndex = MIIdx.getRegSlot(true);
357 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
359 SlotIndex killIndex = getMBBEndIdx(mbb);
360 LiveRange LR(defIndex, killIndex, ValNo);
361 interval.addRange(LR);
362 ValNo->setHasPHIKill(true);
363 DEBUG(dbgs() << " phi-join +" << LR);
365 llvm_unreachable("Multiply defined register");
369 DEBUG(dbgs() << '\n');
372 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
373 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
374 SE = MBB->succ_end();
376 const MachineBasicBlock* succ = *SI;
377 if (succ->isLiveIn(Reg))
383 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
384 MachineBasicBlock::iterator mi,
387 LiveInterval &interval) {
388 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
390 SlotIndex baseIndex = MIIdx;
391 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
392 SlotIndex end = start;
394 // If it is not used after definition, it is considered dead at
395 // the instruction defining it. Hence its interval is:
396 // [defSlot(def), defSlot(def)+1)
397 // For earlyclobbers, the defSlot was pushed back one; the extra
398 // advance below compensates.
400 DEBUG(dbgs() << " dead");
401 end = start.getDeadSlot();
405 // If it is not dead on definition, it must be killed by a
406 // subsequent instruction. Hence its interval is:
407 // [defSlot(def), useSlot(kill)+1)
408 baseIndex = baseIndex.getNextIndex();
409 while (++mi != MBB->end()) {
411 if (mi->isDebugValue())
413 if (getInstructionFromIndex(baseIndex) == 0)
414 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
416 if (mi->killsRegister(interval.reg, TRI)) {
417 DEBUG(dbgs() << " killed");
418 end = baseIndex.getRegSlot();
421 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,TRI);
423 if (mi->isRegTiedToUseOperand(DefIdx)) {
424 // Two-address instruction.
425 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
427 // Another instruction redefines the register before it is ever read.
428 // Then the register is essentially dead at the instruction that
429 // defines it. Hence its interval is:
430 // [defSlot(def), defSlot(def)+1)
431 DEBUG(dbgs() << " dead");
432 end = start.getDeadSlot();
438 baseIndex = baseIndex.getNextIndex();
441 // If we get here the register *should* be live out.
442 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
444 // FIXME: We need saner rules for reserved regs.
445 if (isReserved(interval.reg)) {
446 end = start.getDeadSlot();
448 // Unreserved, unallocable registers like EFLAGS can be live across basic
450 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
451 "Unreserved reg not live-out?");
452 end = getMBBEndIdx(MBB);
455 assert(start < end && "did not find end of interval?");
457 // Already exists? Extend old live interval.
458 VNInfo *ValNo = interval.getVNInfoAt(start);
459 bool Extend = ValNo != 0;
461 ValNo = interval.getNextValue(start, VNInfoAllocator);
462 LiveRange LR(start, end, ValNo);
463 interval.addRange(LR);
464 DEBUG(dbgs() << " +" << LR << '\n');
467 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
468 MachineBasicBlock::iterator MI,
472 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
473 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
474 getOrCreateInterval(MO.getReg()));
476 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
477 getOrCreateInterval(MO.getReg()));
480 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
482 LiveInterval &interval) {
483 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
484 "Only physical registers can be live in.");
485 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
486 MBB->isLandingPad()) &&
487 "Allocatable live-ins only valid for entry blocks and landing pads.");
489 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, TRI));
491 // Look for kills, if it reaches a def before it's killed, then it shouldn't
492 // be considered a livein.
493 MachineBasicBlock::iterator mi = MBB->begin();
494 MachineBasicBlock::iterator E = MBB->end();
495 // Skip over DBG_VALUE at the start of the MBB.
496 if (mi != E && mi->isDebugValue()) {
497 while (++mi != E && mi->isDebugValue())
500 // MBB is empty except for DBG_VALUE's.
504 SlotIndex baseIndex = MIIdx;
505 SlotIndex start = baseIndex;
506 if (getInstructionFromIndex(baseIndex) == 0)
507 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
509 SlotIndex end = baseIndex;
510 bool SeenDefUse = false;
513 if (mi->killsRegister(interval.reg, TRI)) {
514 DEBUG(dbgs() << " killed");
515 end = baseIndex.getRegSlot();
518 } else if (mi->modifiesRegister(interval.reg, TRI)) {
519 // Another instruction redefines the register before it is ever read.
520 // Then the register is essentially dead at the instruction that defines
521 // it. Hence its interval is:
522 // [defSlot(def), defSlot(def)+1)
523 DEBUG(dbgs() << " dead");
524 end = start.getDeadSlot();
529 while (++mi != E && mi->isDebugValue())
530 // Skip over DBG_VALUE.
533 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
536 // Live-in register might not be used at all.
538 if (isAllocatable(interval.reg) ||
539 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
540 // Allocatable registers are never live through.
541 // Non-allocatable registers that aren't live into any successors also
542 // aren't live through.
543 DEBUG(dbgs() << " dead");
546 // If we get here the register is non-allocatable and live into some
547 // successor. We'll conservatively assume it's live-through.
548 DEBUG(dbgs() << " live through");
549 end = getMBBEndIdx(MBB);
553 SlotIndex defIdx = getMBBStartIdx(MBB);
554 assert(getInstructionFromIndex(defIdx) == 0 &&
555 "PHI def index points at actual instruction.");
556 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
557 vni->setIsPHIDef(true);
558 LiveRange LR(start, end, vni);
560 interval.addRange(LR);
561 DEBUG(dbgs() << " +" << LR << '\n');
564 /// computeIntervals - computes the live intervals for virtual
565 /// registers. for some ordering of the machine instructions [1,N] a
566 /// live interval is an interval [i, j) where 1 <= i <= j < N for
567 /// which a variable is live
568 void LiveIntervals::computeIntervals() {
569 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
570 << "********** Function: "
571 << ((Value*)MF->getFunction())->getName() << '\n');
573 RegMaskBlocks.resize(MF->getNumBlockIDs());
575 SmallVector<unsigned, 8> UndefUses;
576 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
578 MachineBasicBlock *MBB = MBBI;
579 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
584 // Track the index of the current machine instr.
585 SlotIndex MIIndex = getMBBStartIdx(MBB);
586 DEBUG(dbgs() << "BB#" << MBB->getNumber()
587 << ":\t\t# derived from " << MBB->getName() << "\n");
589 // Create intervals for live-ins to this BB first.
590 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
591 LE = MBB->livein_end(); LI != LE; ++LI) {
592 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
595 // Skip over empty initial indices.
596 if (getInstructionFromIndex(MIIndex) == 0)
597 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
599 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
601 DEBUG(dbgs() << MIIndex << "\t" << *MI);
602 if (MI->isDebugValue())
604 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
605 "Lost SlotIndex synchronization");
608 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
609 MachineOperand &MO = MI->getOperand(i);
611 // Collect register masks.
612 if (MO.isRegMask()) {
613 RegMaskSlots.push_back(MIIndex.getRegSlot());
614 RegMaskBits.push_back(MO.getRegMask());
618 if (!MO.isReg() || !MO.getReg())
621 // handle register defs - build intervals
623 handleRegisterDef(MBB, MI, MIIndex, MO, i);
624 else if (MO.isUndef())
625 UndefUses.push_back(MO.getReg());
628 // Move to the next instr slot.
629 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
632 // Compute the number of register mask instructions in this block.
633 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
634 RMB.second = RegMaskSlots.size() - RMB.first;;
637 // Create empty intervals for registers defined by implicit_def's (except
638 // for those implicit_def that define values which are liveout of their
640 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
641 unsigned UndefReg = UndefUses[i];
642 (void)getOrCreateInterval(UndefReg);
646 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
647 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
648 return new LiveInterval(reg, Weight);
652 //===----------------------------------------------------------------------===//
653 // Register Unit Liveness
654 //===----------------------------------------------------------------------===//
656 // Fixed interference typically comes from ABI boundaries: Function arguments
657 // and return values are passed in fixed registers, and so are exception
658 // pointers entering landing pads. Certain instructions require values to be
659 // present in specific registers. That is also represented through fixed
663 /// computeRegUnitInterval - Compute the live interval of a register unit, based
664 /// on the uses and defs of aliasing registers. The interval should be empty,
665 /// or contain only dead phi-defs from ABI blocks.
666 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
667 unsigned Unit = LI->reg;
669 assert(LRCalc && "LRCalc not initialized.");
670 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
672 // The physregs aliasing Unit are the roots and their super-registers.
673 // Create all values as dead defs before extending to uses. Note that roots
674 // may share super-registers. That's OK because createDeadDefs() is
675 // idempotent. It is very rare for a register unit to have multiple roots, so
676 // uniquing super-registers is probably not worthwhile.
677 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
678 unsigned Root = *Roots;
679 if (!MRI->reg_empty(Root))
680 LRCalc->createDeadDefs(LI, Root);
681 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
682 if (!MRI->reg_empty(*Supers))
683 LRCalc->createDeadDefs(LI, *Supers);
687 // Now extend LI to reach all uses.
688 // Ignore uses of reserved registers. We only track defs of those.
689 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
690 unsigned Root = *Roots;
691 if (!isReserved(Root) && !MRI->reg_empty(Root))
692 LRCalc->extendToUses(LI, Root);
693 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
694 unsigned Reg = *Supers;
695 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
696 LRCalc->extendToUses(LI, Reg);
702 /// computeLiveInRegUnits - Precompute the live ranges of any register units
703 /// that are live-in to an ABI block somewhere. Register values can appear
704 /// without a corresponding def when entering the entry block or a landing pad.
706 void LiveIntervals::computeLiveInRegUnits() {
707 RegUnitIntervals.resize(TRI->getNumRegUnits());
708 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
710 // Keep track of the intervals allocated.
711 SmallVector<LiveInterval*, 8> NewIntvs;
713 // Check all basic blocks for live-ins.
714 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
716 const MachineBasicBlock *MBB = MFI;
718 // We only care about ABI blocks: Entry + landing pads.
719 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
722 // Create phi-defs at Begin for all live-in registers.
723 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
724 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
725 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
726 LIE = MBB->livein_end(); LII != LIE; ++LII) {
727 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
728 unsigned Unit = *Units;
729 LiveInterval *Intv = RegUnitIntervals[Unit];
731 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
732 NewIntvs.push_back(Intv);
734 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
736 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
739 DEBUG(dbgs() << '\n');
741 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
743 // Compute the 'normal' part of the intervals.
744 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
745 computeRegUnitInterval(NewIntvs[i]);
749 /// shrinkToUses - After removing some uses of a register, shrink its live
750 /// range to just the remaining uses. This method does not compute reaching
751 /// defs for new uses, and it doesn't remove dead defs.
752 bool LiveIntervals::shrinkToUses(LiveInterval *li,
753 SmallVectorImpl<MachineInstr*> *dead) {
754 DEBUG(dbgs() << "Shrink: " << *li << '\n');
755 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
756 && "Can only shrink virtual registers");
757 // Find all the values used, including PHI kills.
758 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
760 // Blocks that have already been added to WorkList as live-out.
761 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
763 // Visit all instructions reading li->reg.
764 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
765 MachineInstr *UseMI = I.skipInstruction();) {
766 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
768 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
769 LiveRangeQuery LRQ(*li, Idx);
770 VNInfo *VNI = LRQ.valueIn();
772 // This shouldn't happen: readsVirtualRegister returns true, but there is
773 // no live value. It is likely caused by a target getting <undef> flags
775 DEBUG(dbgs() << Idx << '\t' << *UseMI
776 << "Warning: Instr claims to read non-existent value in "
780 // Special case: An early-clobber tied operand reads and writes the
781 // register one slot early.
782 if (VNInfo *DefVNI = LRQ.valueDefined())
785 WorkList.push_back(std::make_pair(Idx, VNI));
788 // Create a new live interval with only minimal live segments per def.
789 LiveInterval NewLI(li->reg, 0);
790 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
795 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
798 // Keep track of the PHIs that are in use.
799 SmallPtrSet<VNInfo*, 8> UsedPHIs;
801 // Extend intervals to reach all uses in WorkList.
802 while (!WorkList.empty()) {
803 SlotIndex Idx = WorkList.back().first;
804 VNInfo *VNI = WorkList.back().second;
806 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
807 SlotIndex BlockStart = getMBBStartIdx(MBB);
809 // Extend the live range for VNI to be live at Idx.
810 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
812 assert(ExtVNI == VNI && "Unexpected existing value number");
813 // Is this a PHIDef we haven't seen before?
814 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
816 // The PHI is live, make sure the predecessors are live-out.
817 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
818 PE = MBB->pred_end(); PI != PE; ++PI) {
819 if (!LiveOut.insert(*PI))
821 SlotIndex Stop = getMBBEndIdx(*PI);
822 // A predecessor is not required to have a live-out value for a PHI.
823 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
824 WorkList.push_back(std::make_pair(Stop, PVNI));
829 // VNI is live-in to MBB.
830 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
831 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
833 // Make sure VNI is live-out from the predecessors.
834 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
835 PE = MBB->pred_end(); PI != PE; ++PI) {
836 if (!LiveOut.insert(*PI))
838 SlotIndex Stop = getMBBEndIdx(*PI);
839 assert(li->getVNInfoBefore(Stop) == VNI &&
840 "Wrong value out of predecessor");
841 WorkList.push_back(std::make_pair(Stop, VNI));
845 // Handle dead values.
846 bool CanSeparate = false;
847 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
852 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
853 assert(LII != NewLI.end() && "Missing live range for PHI");
854 if (LII->end != VNI->def.getDeadSlot())
856 if (VNI->isPHIDef()) {
857 // This is a dead PHI. Remove it.
858 VNI->setIsUnused(true);
859 NewLI.removeRange(*LII);
860 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
863 // This is a dead def. Make sure the instruction knows.
864 MachineInstr *MI = getInstructionFromIndex(VNI->def);
865 assert(MI && "No instruction defining live value");
866 MI->addRegisterDead(li->reg, TRI);
867 if (dead && MI->allDefsAreDead()) {
868 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
874 // Move the trimmed ranges back.
875 li->ranges.swap(NewLI.ranges);
876 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
881 //===----------------------------------------------------------------------===//
882 // Register allocator hooks.
885 void LiveIntervals::addKillFlags() {
886 for (iterator I = begin(), E = end(); I != E; ++I) {
887 unsigned Reg = I->first;
888 if (TargetRegisterInfo::isPhysicalRegister(Reg))
890 if (MRI->reg_nodbg_empty(Reg))
892 LiveInterval *LI = I->second;
894 // Every instruction that kills Reg corresponds to a live range end point.
895 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
897 // A block index indicates an MBB edge.
898 if (RI->end.isBlock())
900 MachineInstr *MI = getInstructionFromIndex(RI->end);
903 MI->addRegisterKilled(Reg, NULL);
909 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
910 // A local live range must be fully contained inside the block, meaning it is
911 // defined and killed at instructions, not at block boundaries. It is not
912 // live in or or out of any block.
914 // It is technically possible to have a PHI-defined live range identical to a
915 // single block, but we are going to return false in that case.
917 SlotIndex Start = LI.beginIndex();
921 SlotIndex Stop = LI.endIndex();
925 // getMBBFromIndex doesn't need to search the MBB table when both indexes
926 // belong to proper instructions.
927 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
928 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
929 return MBB1 == MBB2 ? MBB1 : NULL;
933 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
934 // Limit the loop depth ridiculousness.
938 // The loop depth is used to roughly estimate the number of times the
939 // instruction is executed. Something like 10^d is simple, but will quickly
940 // overflow a float. This expression behaves like 10^d for small d, but is
941 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
942 // headroom before overflow.
943 // By the way, powf() might be unavailable here. For consistency,
944 // We may take pow(double,double).
945 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
947 return (isDef + isUse) * lc;
950 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
951 MachineInstr* startInst) {
952 LiveInterval& Interval = getOrCreateInterval(reg);
953 VNInfo* VN = Interval.getNextValue(
954 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
955 getVNInfoAllocator());
956 VN->setHasPHIKill(true);
958 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
959 getMBBEndIdx(startInst->getParent()), VN);
960 Interval.addRange(LR);
966 //===----------------------------------------------------------------------===//
967 // Register mask functions
968 //===----------------------------------------------------------------------===//
970 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
971 BitVector &UsableRegs) {
974 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
976 // Use a smaller arrays for local live ranges.
977 ArrayRef<SlotIndex> Slots;
978 ArrayRef<const uint32_t*> Bits;
979 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
980 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
981 Bits = getRegMaskBitsInBlock(MBB->getNumber());
983 Slots = getRegMaskSlots();
984 Bits = getRegMaskBits();
987 // We are going to enumerate all the register mask slots contained in LI.
988 // Start with a binary search of RegMaskSlots to find a starting point.
989 ArrayRef<SlotIndex>::iterator SlotI =
990 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
991 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
993 // No slots in range, LI begins after the last call.
999 assert(*SlotI >= LiveI->start);
1000 // Loop over all slots overlapping this segment.
1001 while (*SlotI < LiveI->end) {
1002 // *SlotI overlaps LI. Collect mask bits.
1004 // This is the first overlap. Initialize UsableRegs to all ones.
1006 UsableRegs.resize(TRI->getNumRegs(), true);
1009 // Remove usable registers clobbered by this mask.
1010 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1011 if (++SlotI == SlotE)
1014 // *SlotI is beyond the current LI segment.
1015 LiveI = LI.advanceTo(LiveI, *SlotI);
1018 // Advance SlotI until it overlaps.
1019 while (*SlotI < LiveI->start)
1020 if (++SlotI == SlotE)
1025 //===----------------------------------------------------------------------===//
1026 // IntervalUpdate class.
1027 //===----------------------------------------------------------------------===//
1029 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1030 class LiveIntervals::HMEditor {
1033 const MachineRegisterInfo& MRI;
1034 const TargetRegisterInfo& TRI;
1037 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1038 typedef DenseSet<IntRangePair> RangeSet;
1045 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
1047 typedef DenseMap<unsigned, RegRanges> BundleRanges;
1050 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1051 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1052 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1054 // Update intervals for all operands of MI from OldIdx to NewIdx.
1055 // This assumes that MI used to be at OldIdx, and now resides at
1057 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
1058 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
1060 // Collect the operands.
1061 RangeSet Entering, Internal, Exiting;
1062 bool hasRegMaskOp = false;
1063 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1065 // To keep the LiveRanges valid within an interval, move the ranges closest
1066 // to the destination first. This prevents ranges from overlapping, to that
1067 // APIs like removeRange still work.
1068 if (NewIdx < OldIdx) {
1069 moveAllEnteringFrom(OldIdx, Entering);
1070 moveAllInternalFrom(OldIdx, Internal);
1071 moveAllExitingFrom(OldIdx, Exiting);
1074 moveAllExitingFrom(OldIdx, Exiting);
1075 moveAllInternalFrom(OldIdx, Internal);
1076 moveAllEnteringFrom(OldIdx, Entering);
1080 updateRegMaskSlots(OldIdx);
1083 LIValidator validator;
1084 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1085 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1086 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1087 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1092 // Update intervals for all operands of MI to refer to BundleStart's
1094 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1095 if (MI == BundleStart)
1096 return; // Bundling instr with itself - nothing to do.
1098 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1099 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1100 "SlotIndex <-> Instruction mapping broken for MI");
1102 // Collect all ranges already in the bundle.
1103 MachineBasicBlock::instr_iterator BII(BundleStart);
1104 RangeSet Entering, Internal, Exiting;
1105 bool hasRegMaskOp = false;
1106 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1107 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1108 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1111 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1112 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1115 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1120 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1121 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1123 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1124 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1125 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1127 moveAllEnteringFromInto(OldIdx, Entering, BR);
1128 moveAllInternalFromInto(OldIdx, Internal, BR);
1129 moveAllExitingFromInto(OldIdx, Exiting, BR);
1133 LIValidator validator;
1134 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1135 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1136 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1137 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1146 DenseSet<const LiveInterval*> Checked, Bogus;
1148 void operator()(const IntRangePair& P) {
1149 const LiveInterval* LI = P.first;
1150 if (Checked.count(LI))
1155 SlotIndex LastEnd = LI->begin()->start;
1156 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1157 LRI != LRE; ++LRI) {
1158 const LiveRange& LR = *LRI;
1159 if (LastEnd > LR.start || LR.start >= LR.end)
1165 bool rangesOk() const {
1166 return Bogus.empty();
1171 // Collect IntRangePairs for all operands of MI that may need fixing.
1172 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1174 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1175 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1176 hasRegMaskOp = false;
1177 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1178 MOE = MI->operands_end();
1179 MOI != MOE; ++MOI) {
1180 const MachineOperand& MO = *MOI;
1182 if (MO.isRegMask()) {
1183 hasRegMaskOp = true;
1187 if (!MO.isReg() || MO.getReg() == 0)
1190 unsigned Reg = MO.getReg();
1192 // TODO: Currently we're skipping uses that are reserved or have no
1193 // interval, but we're not updating their kills. This should be
1195 if (!LIS.hasInterval(Reg) ||
1196 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1199 LiveInterval* LI = &LIS.getInterval(Reg);
1201 if (MO.readsReg()) {
1202 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1204 Entering.insert(std::make_pair(LI, LR));
1207 if (MO.isEarlyClobber()) {
1208 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
1209 assert(LR != 0 && "No EC range?");
1210 if (LR->end > OldIdx.getDeadSlot())
1211 Exiting.insert(std::make_pair(LI, LR));
1213 Internal.insert(std::make_pair(LI, LR));
1214 } else if (MO.isDead()) {
1215 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1216 assert(LR != 0 && "No dead-def range?");
1217 Internal.insert(std::make_pair(LI, LR));
1219 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
1220 assert(LR && LR->end > OldIdx.getDeadSlot() &&
1221 "Non-dead-def should have live range exiting.");
1222 Exiting.insert(std::make_pair(LI, LR));
1228 // Collect IntRangePairs for all operands of MI that may need fixing.
1229 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
1230 RangeSet& Exiting, SlotIndex MIStartIdx,
1231 SlotIndex MIEndIdx) {
1232 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1233 MOE = MI->operands_end();
1234 MOI != MOE; ++MOI) {
1235 const MachineOperand& MO = *MOI;
1236 assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
1237 if (!MO.isReg() || MO.getReg() == 0)
1240 unsigned Reg = MO.getReg();
1242 // TODO: Currently we're skipping uses that are reserved or have no
1243 // interval, but we're not updating their kills. This should be
1245 if (!LIS.hasInterval(Reg) ||
1246 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1249 LiveInterval* LI = &LIS.getInterval(Reg);
1251 if (MO.readsReg()) {
1252 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
1254 Entering.insert(std::make_pair(LI, LR));
1257 assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles.");
1258 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1259 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
1260 assert(LR != 0 && "Internal ranges not allowed in bundles.");
1261 Exiting.insert(std::make_pair(LI, LR));
1266 BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) {
1269 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1271 LiveInterval* LI = EI->first;
1272 LiveRange* LR = EI->second;
1273 BR[LI->reg].Use = LR;
1276 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1278 LiveInterval* LI = II->first;
1279 LiveRange* LR = II->second;
1280 if (LR->end.isDead()) {
1281 BR[LI->reg].Dead = LR;
1283 BR[LI->reg].EC = LR;
1287 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1289 LiveInterval* LI = EI->first;
1290 LiveRange* LR = EI->second;
1291 BR[LI->reg].Def = LR;
1297 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1298 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1299 if (!OldKillMI->killsRegister(reg))
1300 return; // Bail out if we don't have kill flags on the old register.
1301 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1302 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1303 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1304 OldKillMI->clearRegisterKills(reg, &TRI);
1305 NewKillMI->addRegisterKilled(reg, &TRI);
1308 void updateRegMaskSlots(SlotIndex OldIdx) {
1309 SmallVectorImpl<SlotIndex>::iterator RI =
1310 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1312 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1314 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1315 "RegSlots out of order. Did you move one call across another?");
1318 // Return the last use of reg between NewIdx and OldIdx.
1319 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1320 SlotIndex LastUse = NewIdx;
1321 for (MachineRegisterInfo::use_nodbg_iterator
1322 UI = MRI.use_nodbg_begin(Reg),
1323 UE = MRI.use_nodbg_end();
1324 UI != UE; UI.skipInstruction()) {
1325 const MachineInstr* MI = &*UI;
1326 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1327 if (InstSlot > LastUse && InstSlot < OldIdx)
1333 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1334 LiveInterval* LI = P.first;
1335 LiveRange* LR = P.second;
1336 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1339 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1340 if (LastUse != NewIdx)
1341 moveKillFlags(LI->reg, NewIdx, LastUse);
1342 LR->end = LastUse.getRegSlot();
1345 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1346 LiveInterval* LI = P.first;
1347 LiveRange* LR = P.second;
1348 // Extend the LiveRange if NewIdx is past the end.
1349 if (NewIdx > LR->end) {
1350 // Move kill flags if OldIdx was not originally the end
1351 // (otherwise LR->end points to an invalid slot).
1352 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1353 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1354 moveKillFlags(LI->reg, LR->end, NewIdx);
1356 LR->end = NewIdx.getRegSlot();
1360 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1361 bool GoingUp = NewIdx < OldIdx;
1364 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1366 moveEnteringUpFrom(OldIdx, *EI);
1368 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1370 moveEnteringDownFrom(OldIdx, *EI);
1374 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1375 LiveInterval* LI = P.first;
1376 LiveRange* LR = P.second;
1377 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1378 LR->end <= OldIdx.getDeadSlot() &&
1379 "Range should be internal to OldIdx.");
1381 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1382 Tmp.valno->def = Tmp.start;
1383 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1384 LI->removeRange(*LR);
1388 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1389 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1391 moveInternalFrom(OldIdx, *II);
1394 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1395 LiveRange* LR = P.second;
1396 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1397 "Range should start in OldIdx.");
1398 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1399 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1400 LR->start = NewStart;
1401 LR->valno->def = NewStart;
1404 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1405 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1407 moveExitingFrom(OldIdx, *EI);
1410 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1412 LiveInterval* LI = P.first;
1413 LiveRange* LR = P.second;
1414 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1416 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1417 "Def in bundle should be def range.");
1418 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1419 "If bundle has use for this reg it should be LR.");
1420 BR[LI->reg].Use = LR;
1424 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1425 moveKillFlags(LI->reg, OldIdx, LastUse);
1427 if (LR->start < NewIdx) {
1428 // Becoming a new entering range.
1429 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1430 "Bundle shouldn't be re-defining reg mid-range.");
1431 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1432 "Bundle shouldn't have different use range for same reg.");
1433 LR->end = LastUse.getRegSlot();
1434 BR[LI->reg].Use = LR;
1436 // Becoming a new Dead-def.
1437 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1438 "Live range starting at unexpected slot.");
1439 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1440 assert(BR[LI->reg].Dead == 0 &&
1441 "Can't have def and dead def of same reg in a bundle.");
1442 LR->end = LastUse.getDeadSlot();
1443 BR[LI->reg].Dead = BR[LI->reg].Def;
1444 BR[LI->reg].Def = 0;
1448 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1450 LiveInterval* LI = P.first;
1451 LiveRange* LR = P.second;
1452 if (NewIdx > LR->end) {
1453 // Range extended to bundle. Add to bundle uses.
1454 // Note: Currently adds kill flags to bundle start.
1455 assert(BR[LI->reg].Use == 0 &&
1456 "Bundle already has use range for reg.");
1457 moveKillFlags(LI->reg, LR->end, NewIdx);
1458 LR->end = NewIdx.getRegSlot();
1459 BR[LI->reg].Use = LR;
1461 assert(BR[LI->reg].Use != 0 &&
1462 "Bundle should already have a use range for reg.");
1466 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1468 bool GoingUp = NewIdx < OldIdx;
1471 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1473 moveEnteringUpFromInto(OldIdx, *EI, BR);
1475 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1477 moveEnteringDownFromInto(OldIdx, *EI, BR);
1481 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1483 // TODO: Sane rules for moving ranges into bundles.
1486 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1488 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1490 moveInternalFromInto(OldIdx, *II, BR);
1493 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1495 LiveInterval* LI = P.first;
1496 LiveRange* LR = P.second;
1498 assert(LR->start.isRegister() &&
1499 "Don't know how to merge exiting ECs into bundles yet.");
1501 if (LR->end > NewIdx.getDeadSlot()) {
1502 // This range is becoming an exiting range on the bundle.
1503 // If there was an old dead-def of this reg, delete it.
1504 if (BR[LI->reg].Dead != 0) {
1505 LI->removeRange(*BR[LI->reg].Dead);
1506 BR[LI->reg].Dead = 0;
1508 assert(BR[LI->reg].Def == 0 &&
1509 "Can't have two defs for the same variable exiting a bundle.");
1510 LR->start = NewIdx.getRegSlot();
1511 LR->valno->def = LR->start;
1512 BR[LI->reg].Def = LR;
1514 // This range is becoming internal to the bundle.
1515 assert(LR->end == NewIdx.getRegSlot() &&
1516 "Can't bundle def whose kill is before the bundle");
1517 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1518 // Already have a def for this. Just delete range.
1519 LI->removeRange(*LR);
1521 // Make range dead, record.
1522 LR->end = NewIdx.getDeadSlot();
1523 BR[LI->reg].Dead = LR;
1524 assert(BR[LI->reg].Use == LR &&
1525 "Range becoming dead should currently be use.");
1527 // In both cases the range is no longer a use on the bundle.
1528 BR[LI->reg].Use = 0;
1532 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1534 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1536 moveExitingFromInto(OldIdx, *EI, BR);
1541 void LiveIntervals::handleMove(MachineInstr* MI) {
1542 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1543 Indexes->removeMachineInstrFromMaps(MI);
1544 SlotIndex NewIndex = MI->isInsideBundle() ?
1545 Indexes->getInstructionIndex(MI) :
1546 Indexes->insertMachineInstrInMaps(MI);
1547 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1548 OldIndex < getMBBEndIdx(MI->getParent()) &&
1549 "Cannot handle moves across basic block boundaries.");
1550 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1552 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1553 HME.moveAllRangesFrom(MI, OldIndex);
1556 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) {
1557 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1558 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1559 HME.moveAllRangesInto(MI, BundleStart);