1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
40 STATISTIC(numIntervals, "Number of original intervals");
41 STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numFolded , "Number of loads/stores folded into instructions");
45 STATISTIC(numAborts , "Number of times interval joining aborted");
48 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
51 EnableJoining("join-liveintervals",
52 cl::desc("Coallesce copies (default=true)"),
56 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
57 AU.addRequired<LiveVariables>();
58 AU.addPreservedID(PHIEliminationID);
59 AU.addRequiredID(PHIEliminationID);
60 AU.addRequiredID(TwoAddressInstructionPassID);
61 AU.addRequired<LoopInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
65 void LiveIntervals::releaseMemory() {
74 static bool isZeroLengthInterval(LiveInterval *li) {
75 for (LiveInterval::Ranges::const_iterator
76 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
77 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
83 /// runOnMachineFunction - Register allocate the whole function
85 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
87 tm_ = &fn.getTarget();
88 mri_ = tm_->getRegisterInfo();
89 tii_ = tm_->getInstrInfo();
90 lv_ = &getAnalysis<LiveVariables>();
91 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
92 allocatableRegs_ = mri_->getAllocatableSet(fn);
93 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
94 E = mri_->regclass_end(); I != E; ++I)
95 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
97 // Number MachineInstrs and MachineBasicBlocks.
98 // Initialize MBB indexes to a sentinal.
99 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
101 unsigned MIIndex = 0;
102 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
104 // Set the MBB2IdxMap entry for this MBB.
105 MBB2IdxMap[MBB->getNumber()] = MIIndex;
107 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
109 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
110 assert(inserted && "multiple MachineInstr -> index mappings");
111 i2miMap_.push_back(I);
112 MIIndex += InstrSlots::NUM;
118 numIntervals += getNumIntervals();
120 DOUT << "********** INTERVALS **********\n";
121 for (iterator I = begin(), E = end(); I != E; ++I) {
122 I->second.print(DOUT, mri_);
126 // Join (coallesce) intervals if requested.
129 DOUT << "********** INTERVALS POST JOINING **********\n";
130 for (iterator I = begin(), E = end(); I != E; ++I) {
131 I->second.print(DOUT, mri_);
136 numIntervalsAfter += getNumIntervals();
138 // perform a final pass over the instructions and compute spill
139 // weights, coalesce virtual registers and remove identity moves.
140 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
142 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
143 mbbi != mbbe; ++mbbi) {
144 MachineBasicBlock* mbb = mbbi;
145 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
147 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
149 // if the move will be an identity move delete it
150 unsigned srcReg, dstReg, RegRep;
151 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
152 (RegRep = rep(srcReg)) == rep(dstReg)) {
153 // remove from def list
154 LiveInterval &RegInt = getOrCreateInterval(RegRep);
155 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
156 // If def of this move instruction is dead, remove its live range from
157 // the dstination register's live interval.
159 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
160 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
161 RegInt.removeRange(MLR->start, MoveIdx+1);
163 removeInterval(RegRep);
165 RemoveMachineInstrFromMaps(mii);
166 mii = mbbi->erase(mii);
169 SmallSet<unsigned, 4> UniqueUses;
170 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
171 const MachineOperand &mop = mii->getOperand(i);
172 if (mop.isRegister() && mop.getReg() &&
173 MRegisterInfo::isVirtualRegister(mop.getReg())) {
174 // replace register with representative register
175 unsigned reg = rep(mop.getReg());
176 mii->getOperand(i).setReg(reg);
178 // Multiple uses of reg by the same instruction. It should not
179 // contribute to spill weight again.
180 if (UniqueUses.count(reg) != 0)
182 LiveInterval &RegInt = getInterval(reg);
183 float w = (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
184 // If the definition instruction is re-materializable, its spill
185 // weight is half of what it would have been normally unless it's
186 // a load from fixed stack slot.
188 if (RegInt.remat && !tii_->isLoadFromStackSlot(RegInt.remat, Dummy))
191 UniqueUses.insert(reg);
199 for (iterator I = begin(), E = end(); I != E; ++I) {
200 LiveInterval &LI = I->second;
201 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
202 // If the live interval length is essentially zero, i.e. in every live
203 // range the use follows def immediately, it doesn't make sense to spill
204 // it and hope it will be easier to allocate for this li.
205 if (isZeroLengthInterval(&LI))
206 LI.weight = HUGE_VALF;
208 // Slightly prefer live interval that has been assigned a preferred reg.
212 // Divide the weight of the interval by its size. This encourages
213 // spilling of intervals that are large and have few uses, and
214 // discourages spilling of small intervals with many uses.
215 LI.weight /= LI.getSize();
223 /// print - Implement the dump method.
224 void LiveIntervals::print(std::ostream &O, const Module* ) const {
225 O << "********** INTERVALS **********\n";
226 for (const_iterator I = begin(), E = end(); I != E; ++I) {
227 I->second.print(DOUT, mri_);
231 O << "********** MACHINEINSTRS **********\n";
232 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
233 mbbi != mbbe; ++mbbi) {
234 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
235 for (MachineBasicBlock::iterator mii = mbbi->begin(),
236 mie = mbbi->end(); mii != mie; ++mii) {
237 O << getInstructionIndex(mii) << '\t' << *mii;
242 /// CreateNewLiveInterval - Create a new live interval with the given live
243 /// ranges. The new live interval will have an infinite spill weight.
245 LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
246 const std::vector<LiveRange> &LRs) {
247 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
249 // Create a new virtual register for the spill interval.
250 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
252 // Replace the old virtual registers in the machine operands with the shiny
254 for (std::vector<LiveRange>::const_iterator
255 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
256 unsigned Index = getBaseIndex(I->start);
257 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
259 for (; Index != End; Index += InstrSlots::NUM) {
260 // Skip deleted instructions
261 while (Index != End && !getInstructionFromIndex(Index))
262 Index += InstrSlots::NUM;
264 if (Index == End) break;
266 MachineInstr *MI = getInstructionFromIndex(Index);
268 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
269 MachineOperand &MOp = MI->getOperand(J);
270 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg)
276 LiveInterval &NewLI = getOrCreateInterval(NewVReg);
278 // The spill weight is now infinity as it cannot be spilled again
279 NewLI.weight = float(HUGE_VAL);
281 for (std::vector<LiveRange>::const_iterator
282 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
283 DOUT << " Adding live range " << *I << " to new interval\n";
287 DOUT << "Created new live interval " << NewLI << "\n";
291 std::vector<LiveInterval*> LiveIntervals::
292 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
293 // since this is called after the analysis is done we don't know if
294 // LiveVariables is available
295 lv_ = getAnalysisToUpdate<LiveVariables>();
297 std::vector<LiveInterval*> added;
299 assert(li.weight != HUGE_VALF &&
300 "attempt to spill already spilled interval!");
302 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
303 li.print(DOUT, mri_);
306 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
308 for (LiveInterval::Ranges::const_iterator
309 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
310 unsigned index = getBaseIndex(i->start);
311 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
312 for (; index != end; index += InstrSlots::NUM) {
313 // skip deleted instructions
314 while (index != end && !getInstructionFromIndex(index))
315 index += InstrSlots::NUM;
316 if (index == end) break;
318 MachineInstr *MI = getInstructionFromIndex(index);
321 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
322 MachineOperand& mop = MI->getOperand(i);
323 if (mop.isRegister() && mop.getReg() == li.reg) {
324 MachineInstr *fmi = li.remat ? NULL
325 : mri_->foldMemoryOperand(MI, i, slot);
327 // Attempt to fold the memory reference into the instruction. If we
328 // can do this, we don't need to insert spill code.
330 lv_->instructionChanged(MI, fmi);
331 MachineBasicBlock &MBB = *MI->getParent();
332 vrm.virtFolded(li.reg, MI, i, fmi);
334 i2miMap_[index/InstrSlots::NUM] = fmi;
335 mi2iMap_[fmi] = index;
336 MI = MBB.insert(MBB.erase(MI), fmi);
338 // Folding the load/store can completely change the instruction in
339 // unpredictable ways, rescan it from the beginning.
340 goto RestartInstruction;
342 // Create a new virtual register for the spill interval.
343 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
345 // Scan all of the operands of this instruction rewriting operands
346 // to use NewVReg instead of li.reg as appropriate. We do this for
349 // 1. If the instr reads the same spilled vreg multiple times, we
350 // want to reuse the NewVReg.
351 // 2. If the instr is a two-addr instruction, we are required to
352 // keep the src/dst regs pinned.
354 // Keep track of whether we replace a use and/or def so that we can
355 // create the spill interval with the appropriate range.
358 bool HasUse = mop.isUse();
359 bool HasDef = mop.isDef();
360 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
361 if (MI->getOperand(j).isReg() &&
362 MI->getOperand(j).getReg() == li.reg) {
363 MI->getOperand(j).setReg(NewVReg);
364 HasUse |= MI->getOperand(j).isUse();
365 HasDef |= MI->getOperand(j).isDef();
369 // create a new register for this spill
372 vrm.setVirtIsReMaterialized(NewVReg, li.remat);
373 vrm.assignVirt2StackSlot(NewVReg, slot);
374 LiveInterval &nI = getOrCreateInterval(NewVReg);
378 // the spill weight is now infinity as it
379 // cannot be spilled again
380 nI.weight = HUGE_VALF;
383 LiveRange LR(getLoadIndex(index), getUseIndex(index),
384 nI.getNextValue(~0U, 0));
389 LiveRange LR(getDefIndex(index), getStoreIndex(index),
390 nI.getNextValue(~0U, 0));
395 added.push_back(&nI);
397 // update live variables if it is available
399 lv_->addVirtualRegisterKilled(NewVReg, MI);
401 DOUT << "\t\t\t\tadded new interval: ";
402 nI.print(DOUT, mri_);
413 void LiveIntervals::printRegName(unsigned reg) const {
414 if (MRegisterInfo::isPhysicalRegister(reg))
415 cerr << mri_->getName(reg);
417 cerr << "%reg" << reg;
420 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
421 /// two addr elimination.
422 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
423 const TargetInstrInfo *TII) {
424 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
425 MachineOperand &MO1 = MI->getOperand(i);
426 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
427 for (unsigned j = i+1; j < e; ++j) {
428 MachineOperand &MO2 = MI->getOperand(j);
429 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
430 MI->getInstrDescriptor()->
431 getOperandConstraint(j, TOI::TIED_TO) == (int)i)
439 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
440 MachineBasicBlock::iterator mi,
442 LiveInterval &interval) {
443 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
444 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
446 // Virtual registers may be defined multiple times (due to phi
447 // elimination and 2-addr elimination). Much of what we do only has to be
448 // done once for the vreg. We use an empty interval to detect the first
449 // time we see a vreg.
450 if (interval.empty()) {
451 // Remember if the definition can be rematerialized. All load's from fixed
452 // stack slots are re-materializable.
455 (tii_->isReMaterializable(vi.DefInst->getOpcode()) ||
456 (tii_->isLoadFromStackSlot(vi.DefInst, FrameIdx) &&
457 mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx))))
458 interval.remat = vi.DefInst;
460 // Get the Idx of the defining instructions.
461 unsigned defIndex = getDefIndex(MIIdx);
464 unsigned SrcReg, DstReg;
465 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
466 ValNum = interval.getNextValue(~0U, 0);
468 ValNum = interval.getNextValue(defIndex, SrcReg);
470 assert(ValNum == 0 && "First value in interval is not 0?");
471 ValNum = 0; // Clue in the optimizer.
473 // Loop over all of the blocks that the vreg is defined in. There are
474 // two cases we have to handle here. The most common case is a vreg
475 // whose lifetime is contained within a basic block. In this case there
476 // will be a single kill, in MBB, which comes after the definition.
477 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
478 // FIXME: what about dead vars?
480 if (vi.Kills[0] != mi)
481 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
483 killIdx = defIndex+1;
485 // If the kill happens after the definition, we have an intra-block
487 if (killIdx > defIndex) {
488 assert(vi.AliveBlocks.none() &&
489 "Shouldn't be alive across any blocks!");
490 LiveRange LR(defIndex, killIdx, ValNum);
491 interval.addRange(LR);
492 DOUT << " +" << LR << "\n";
497 // The other case we handle is when a virtual register lives to the end
498 // of the defining block, potentially live across some blocks, then is
499 // live into some number of blocks, but gets killed. Start by adding a
500 // range that goes from this definition to the end of the defining block.
501 LiveRange NewLR(defIndex,
502 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
504 DOUT << " +" << NewLR;
505 interval.addRange(NewLR);
507 // Iterate over all of the blocks that the variable is completely
508 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
510 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
511 if (vi.AliveBlocks[i]) {
512 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
514 LiveRange LR(getMBBStartIdx(i),
515 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
517 interval.addRange(LR);
523 // Finally, this virtual register is live from the start of any killing
524 // block to the 'use' slot of the killing instruction.
525 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
526 MachineInstr *Kill = vi.Kills[i];
527 LiveRange LR(getMBBStartIdx(Kill->getParent()),
528 getUseIndex(getInstructionIndex(Kill))+1,
530 interval.addRange(LR);
535 // Can no longer safely assume definition is rematerializable.
536 interval.remat = NULL;
538 // If this is the second time we see a virtual register definition, it
539 // must be due to phi elimination or two addr elimination. If this is
540 // the result of two address elimination, then the vreg is one of the
541 // def-and-use register operand.
542 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
543 // If this is a two-address definition, then we have already processed
544 // the live range. The only problem is that we didn't realize there
545 // are actually two values in the live interval. Because of this we
546 // need to take the LiveRegion that defines this register and split it
548 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
549 unsigned RedefIndex = getDefIndex(MIIdx);
551 // Delete the initial value, which should be short and continuous,
552 // because the 2-addr copy must be in the same MBB as the redef.
553 interval.removeRange(DefIndex, RedefIndex);
555 // Two-address vregs should always only be redefined once. This means
556 // that at this point, there should be exactly one value number in it.
557 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
559 // The new value number (#1) is defined by the instruction we claimed
561 unsigned ValNo = interval.getNextValue(0, 0);
562 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
564 // Value#0 is now defined by the 2-addr instruction.
565 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
567 // Add the new live interval which replaces the range for the input copy.
568 LiveRange LR(DefIndex, RedefIndex, ValNo);
569 DOUT << " replace range with " << LR;
570 interval.addRange(LR);
572 // If this redefinition is dead, we need to add a dummy unit live
573 // range covering the def slot.
574 if (lv_->RegisterDefIsDead(mi, interval.reg))
575 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
578 interval.print(DOUT, mri_);
581 // Otherwise, this must be because of phi elimination. If this is the
582 // first redefinition of the vreg that we have seen, go back and change
583 // the live range in the PHI block to be a different value number.
584 if (interval.containsOneValue()) {
585 assert(vi.Kills.size() == 1 &&
586 "PHI elimination vreg should have one kill, the PHI itself!");
588 // Remove the old range that we now know has an incorrect number.
589 MachineInstr *Killer = vi.Kills[0];
590 unsigned Start = getMBBStartIdx(Killer->getParent());
591 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
592 DOUT << " Removing [" << Start << "," << End << "] from: ";
593 interval.print(DOUT, mri_); DOUT << "\n";
594 interval.removeRange(Start, End);
595 DOUT << " RESULT: "; interval.print(DOUT, mri_);
597 // Replace the interval with one of a NEW value number. Note that this
598 // value number isn't actually defined by an instruction, weird huh? :)
599 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
600 DOUT << " replace range with " << LR;
601 interval.addRange(LR);
602 DOUT << " RESULT: "; interval.print(DOUT, mri_);
605 // In the case of PHI elimination, each variable definition is only
606 // live until the end of the block. We've already taken care of the
607 // rest of the live range.
608 unsigned defIndex = getDefIndex(MIIdx);
611 unsigned SrcReg, DstReg;
612 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
613 ValNum = interval.getNextValue(~0U, 0);
615 ValNum = interval.getNextValue(defIndex, SrcReg);
617 LiveRange LR(defIndex,
618 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
619 interval.addRange(LR);
627 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
628 MachineBasicBlock::iterator mi,
630 LiveInterval &interval,
632 // A physical register cannot be live across basic block, so its
633 // lifetime must end somewhere in its defining basic block.
634 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
636 unsigned baseIndex = MIIdx;
637 unsigned start = getDefIndex(baseIndex);
638 unsigned end = start;
640 // If it is not used after definition, it is considered dead at
641 // the instruction defining it. Hence its interval is:
642 // [defSlot(def), defSlot(def)+1)
643 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
645 end = getDefIndex(start) + 1;
649 // If it is not dead on definition, it must be killed by a
650 // subsequent instruction. Hence its interval is:
651 // [defSlot(def), useSlot(kill)+1)
652 while (++mi != MBB->end()) {
653 baseIndex += InstrSlots::NUM;
654 if (lv_->KillsRegister(mi, interval.reg)) {
656 end = getUseIndex(baseIndex) + 1;
658 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
659 // Another instruction redefines the register before it is ever read.
660 // Then the register is essentially dead at the instruction that defines
661 // it. Hence its interval is:
662 // [defSlot(def), defSlot(def)+1)
664 end = getDefIndex(start) + 1;
669 // The only case we should have a dead physreg here without a killing or
670 // instruction where we know it's dead is if it is live-in to the function
672 assert(!SrcReg && "physreg was not killed in defining block!");
673 end = getDefIndex(start) + 1; // It's dead.
676 assert(start < end && "did not find end of interval?");
678 // Already exists? Extend old live interval.
679 LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
680 unsigned Id = (OldLR != interval.end())
682 : interval.getNextValue(SrcReg != 0 ? start : ~0U, SrcReg);
683 LiveRange LR(start, end, Id);
684 interval.addRange(LR);
685 DOUT << " +" << LR << '\n';
688 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
689 MachineBasicBlock::iterator MI,
692 if (MRegisterInfo::isVirtualRegister(reg))
693 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
694 else if (allocatableRegs_[reg]) {
695 unsigned SrcReg, DstReg;
696 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
698 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
699 // Def of a register also defines its sub-registers.
700 for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
701 // Avoid processing some defs more than once.
702 if (!MI->findRegisterDefOperand(*AS))
703 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
707 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
709 LiveInterval &interval, bool isAlias) {
710 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
712 // Look for kills, if it reaches a def before it's killed, then it shouldn't
713 // be considered a livein.
714 MachineBasicBlock::iterator mi = MBB->begin();
715 unsigned baseIndex = MIIdx;
716 unsigned start = baseIndex;
717 unsigned end = start;
718 while (mi != MBB->end()) {
719 if (lv_->KillsRegister(mi, interval.reg)) {
721 end = getUseIndex(baseIndex) + 1;
723 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
724 // Another instruction redefines the register before it is ever read.
725 // Then the register is essentially dead at the instruction that defines
726 // it. Hence its interval is:
727 // [defSlot(def), defSlot(def)+1)
729 end = getDefIndex(start) + 1;
733 baseIndex += InstrSlots::NUM;
738 // Alias of a live-in register might not be used at all.
739 if (isAlias && end == 0) {
741 end = getDefIndex(start) + 1;
744 assert(start < end && "did not find end of interval?");
746 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
747 DOUT << " +" << LR << '\n';
748 interval.addRange(LR);
751 /// computeIntervals - computes the live intervals for virtual
752 /// registers. for some ordering of the machine instructions [1,N] a
753 /// live interval is an interval [i, j) where 1 <= i <= j < N for
754 /// which a variable is live
755 void LiveIntervals::computeIntervals() {
756 DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
757 << "********** Function: "
758 << ((Value*)mf_->getFunction())->getName() << '\n';
759 // Track the index of the current machine instr.
760 unsigned MIIndex = 0;
761 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
763 MachineBasicBlock *MBB = MBBI;
764 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
766 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
768 if (MBB->livein_begin() != MBB->livein_end()) {
769 // Create intervals for live-ins to this BB first.
770 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
771 LE = MBB->livein_end(); LI != LE; ++LI) {
772 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
773 // Multiple live-ins can alias the same register.
774 for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
775 if (!hasInterval(*AS))
776 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true);
780 for (; MI != miEnd; ++MI) {
781 DOUT << MIIndex << "\t" << *MI;
784 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
785 MachineOperand &MO = MI->getOperand(i);
786 // handle register defs - build intervals
787 if (MO.isRegister() && MO.getReg() && MO.isDef())
788 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
791 MIIndex += InstrSlots::NUM;
796 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
797 /// being the source and IntB being the dest, thus this defines a value number
798 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
799 /// see if we can merge these two pieces of B into a single value number,
800 /// eliminating a copy. For example:
804 /// B1 = A3 <- this copy
806 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
807 /// value number to be replaced with B0 (which simplifies the B liveinterval).
809 /// This returns true if an interval was modified.
811 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
812 MachineInstr *CopyMI) {
813 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
815 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
816 // the example above.
817 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
818 unsigned BValNo = BLR->ValId;
820 // Get the location that B is defined at. Two options: either this value has
821 // an unknown definition point or it is defined at CopyIdx. If unknown, we
823 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
824 if (BValNoDefIdx == ~0U) return false;
825 assert(BValNoDefIdx == CopyIdx &&
826 "Copy doesn't define the value?");
828 // AValNo is the value number in A that defines the copy, A0 in the example.
829 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
830 unsigned AValNo = AValLR->ValId;
832 // If AValNo is defined as a copy from IntB, we can potentially process this.
834 // Get the instruction that defines this value number.
835 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
836 if (!SrcReg) return false; // Not defined by a copy.
838 // If the value number is not defined by a copy instruction, ignore it.
840 // If the source register comes from an interval other than IntB, we can't
842 if (rep(SrcReg) != IntB.reg) return false;
844 // Get the LiveRange in IntB that this value number starts with.
845 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
846 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
848 // Make sure that the end of the live range is inside the same block as
850 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
852 ValLREndInst->getParent() != CopyMI->getParent()) return false;
854 // Okay, we now know that ValLR ends in the same block that the CopyMI
855 // live-range starts. If there are no intervening live ranges between them in
856 // IntB, we can merge them.
857 if (ValLR+1 != BLR) return false;
859 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
861 // We are about to delete CopyMI, so need to remove it as the 'instruction
862 // that defines this value #'.
863 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
865 // Okay, we can merge them. We need to insert a new liverange:
866 // [ValLR.end, BLR.begin) of either value number, then we merge the
867 // two value numbers.
868 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
869 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
871 // If the IntB live range is assigned to a physical register, and if that
872 // physreg has aliases,
873 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
874 // Update the liveintervals of sub-registers.
875 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
876 LiveInterval &AliasLI = getInterval(*AS);
877 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
878 AliasLI.getNextValue(~0U, 0)));
882 // Okay, merge "B1" into the same value number as "B0".
883 if (BValNo != ValLR->ValId)
884 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
885 DOUT << " result = "; IntB.print(DOUT, mri_);
888 // If the source instruction was killing the source register before the
889 // merge, unset the isKill marker given the live range has been extended.
890 int UIdx = ValLREndInst->findRegisterUseOperand(IntB.reg, true);
892 ValLREndInst->getOperand(UIdx).unsetIsKill();
894 // Finally, delete the copy instruction.
895 RemoveMachineInstrFromMaps(CopyMI);
896 CopyMI->eraseFromParent();
902 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
903 /// which are the src/dst of the copy instruction CopyMI. This returns true
904 /// if the copy was successfully coallesced away, or if it is never possible
905 /// to coallesce this copy, due to register constraints. It returns
906 /// false if it is not currently possible to coallesce this interval, but
907 /// it may be possible if other things get coallesced.
908 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
909 unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
910 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
912 // Get representative registers.
913 unsigned repSrcReg = rep(SrcReg);
914 unsigned repDstReg = rep(DstReg);
916 // If they are already joined we continue.
917 if (repSrcReg == repDstReg) {
918 DOUT << "\tCopy already coallesced.\n";
919 return true; // Not coallescable.
922 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
923 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
924 if (PhysOnly && !SrcIsPhys && !DstIsPhys)
925 // Only joining physical registers with virtual registers in this round.
928 // If they are both physical registers, we cannot join them.
929 if (SrcIsPhys && DstIsPhys) {
930 DOUT << "\tCan not coallesce physregs.\n";
931 return true; // Not coallescable.
934 // We only join virtual registers with allocatable physical registers.
935 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
936 DOUT << "\tSrc reg is unallocatable physreg.\n";
937 return true; // Not coallescable.
939 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
940 DOUT << "\tDst reg is unallocatable physreg.\n";
941 return true; // Not coallescable.
944 // If they are not of the same register class, we cannot join them.
945 if (differingRegisterClasses(repSrcReg, repDstReg)) {
946 DOUT << "\tSrc/Dest are different register classes.\n";
947 return true; // Not coallescable.
950 LiveInterval &SrcInt = getInterval(repSrcReg);
951 LiveInterval &DstInt = getInterval(repDstReg);
952 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
953 "Register mapping is horribly broken!");
955 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
956 DOUT << " and "; DstInt.print(DOUT, mri_);
959 // Check if it is necessary to propagate "isDead" property before intervals
961 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
962 bool isDead = mopd->isDead();
963 bool isShorten = false;
964 unsigned SrcStart = 0, RemoveStart = 0;
965 unsigned SrcEnd = 0, RemoveEnd = 0;
967 unsigned CopyIdx = getInstructionIndex(CopyMI);
968 LiveInterval::iterator SrcLR =
969 SrcInt.FindLiveRangeContaining(getUseIndex(CopyIdx));
970 RemoveStart = SrcStart = SrcLR->start;
971 RemoveEnd = SrcEnd = SrcLR->end;
972 // The instruction which defines the src is only truly dead if there are
973 // no intermediate uses and there isn't a use beyond the copy.
974 // FIXME: find the last use, mark is kill and shorten the live range.
975 if (SrcEnd > getDefIndex(CopyIdx)) {
979 MachineInstr *LastUse= lastRegisterUse(repSrcReg, SrcStart, CopyIdx, MOU);
981 // Shorten the liveinterval to the end of last use.
985 RemoveStart = getDefIndex(getInstructionIndex(LastUse));
988 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
990 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
992 // A dead def should have a single cycle interval.
999 // We need to be careful about coalescing a source physical register with a
1000 // virtual register. Once the coalescing is done, it cannot be broken and
1001 // these are not spillable! If the destination interval uses are far away,
1002 // think twice about coalescing them!
1003 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys)) {
1004 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1005 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
1006 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
1007 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
1008 unsigned Threshold = allocatableRCRegs_[RC].count();
1010 // If the virtual register live interval is long has it has low use desity,
1011 // do not join them, instead mark the physical register as its allocation
1013 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
1014 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
1015 if (Length > Threshold &&
1016 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
1017 JoinVInt.preference = JoinPReg;
1019 DOUT << "\tMay tie down a physical register, abort!\n";
1024 // Okay, attempt to join these two intervals. On failure, this returns false.
1025 // Otherwise, if one of the intervals being joined is a physreg, this method
1026 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1027 // been modified, so we can use this information below to update aliases.
1028 if (JoinIntervals(DstInt, SrcInt)) {
1030 // Result of the copy is dead. Propagate this property.
1031 if (SrcStart == 0) {
1032 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
1033 "Live-in must be a physical register!");
1034 // Live-in to the function but dead. Remove it from entry live-in set.
1035 // JoinIntervals may end up swapping the two intervals.
1036 mf_->begin()->removeLiveIn(repSrcReg);
1038 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
1040 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
1047 if (isShorten || isDead) {
1048 // Shorten the live interval.
1049 LiveInterval &LiveInInt = (repSrcReg == DstInt.reg) ? DstInt : SrcInt;
1050 LiveInInt.removeRange(RemoveStart, RemoveEnd);
1053 // Coallescing failed.
1055 // If we can eliminate the copy without merging the live ranges, do so now.
1056 if (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI))
1059 // Otherwise, we are unable to join the intervals.
1060 DOUT << "Interference!\n";
1064 bool Swapped = repSrcReg == DstInt.reg;
1066 std::swap(repSrcReg, repDstReg);
1067 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
1068 "LiveInterval::join didn't work right!");
1070 // If we're about to merge live ranges into a physical register live range,
1071 // we have to update any aliased register's live ranges to indicate that they
1072 // have clobbered values for this range.
1073 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
1074 // Update the liveintervals of sub-registers.
1075 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
1076 getInterval(*AS).MergeInClobberRanges(SrcInt);
1078 // Merge use info if the destination is a virtual register.
1079 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
1080 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
1081 dVI.NumUses += sVI.NumUses;
1084 DOUT << "\n\t\tJoined. Result = "; DstInt.print(DOUT, mri_);
1087 // Remember these liveintervals have been joined.
1088 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
1089 if (MRegisterInfo::isVirtualRegister(repDstReg))
1090 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
1092 // If the intervals were swapped by Join, swap them back so that the register
1093 // mapping (in the r2i map) is correct.
1094 if (Swapped) SrcInt.swap(DstInt);
1095 removeInterval(repSrcReg);
1096 r2rMap_[repSrcReg] = repDstReg;
1098 // Finally, delete the copy instruction.
1099 RemoveMachineInstrFromMaps(CopyMI);
1100 CopyMI->eraseFromParent();
1106 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1107 /// compute what the resultant value numbers for each value in the input two
1108 /// ranges will be. This is complicated by copies between the two which can
1109 /// and will commonly cause multiple value numbers to be merged into one.
1111 /// VN is the value number that we're trying to resolve. InstDefiningValue
1112 /// keeps track of the new InstDefiningValue assignment for the result
1113 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1114 /// whether a value in this or other is a copy from the opposite set.
1115 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1116 /// already been assigned.
1118 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1119 /// contains the value number the copy is from.
1121 static unsigned ComputeUltimateVN(unsigned VN,
1122 SmallVector<std::pair<unsigned,
1123 unsigned>, 16> &ValueNumberInfo,
1124 SmallVector<int, 16> &ThisFromOther,
1125 SmallVector<int, 16> &OtherFromThis,
1126 SmallVector<int, 16> &ThisValNoAssignments,
1127 SmallVector<int, 16> &OtherValNoAssignments,
1128 LiveInterval &ThisLI, LiveInterval &OtherLI) {
1129 // If the VN has already been computed, just return it.
1130 if (ThisValNoAssignments[VN] >= 0)
1131 return ThisValNoAssignments[VN];
1132 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1134 // If this val is not a copy from the other val, then it must be a new value
1135 // number in the destination.
1136 int OtherValNo = ThisFromOther[VN];
1137 if (OtherValNo == -1) {
1138 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
1139 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
1142 // Otherwise, this *is* a copy from the RHS. If the other side has already
1143 // been computed, return it.
1144 if (OtherValNoAssignments[OtherValNo] >= 0)
1145 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
1147 // Mark this value number as currently being computed, then ask what the
1148 // ultimate value # of the other value is.
1149 ThisValNoAssignments[VN] = -2;
1150 unsigned UltimateVN =
1151 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
1152 OtherFromThis, ThisFromOther,
1153 OtherValNoAssignments, ThisValNoAssignments,
1155 return ThisValNoAssignments[VN] = UltimateVN;
1158 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
1159 return std::find(V.begin(), V.end(), Val) != V.end();
1162 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1163 /// caller of this method must guarantee that the RHS only contains a single
1164 /// value number and that the RHS is not defined by a copy from this
1165 /// interval. This returns false if the intervals are not joinable, or it
1166 /// joins them and returns true.
1167 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
1168 assert(RHS.containsOneValue());
1170 // Some number (potentially more than one) value numbers in the current
1171 // interval may be defined as copies from the RHS. Scan the overlapping
1172 // portions of the LHS and RHS, keeping track of this and looking for
1173 // overlapping live ranges that are NOT defined as copies. If these exist, we
1174 // cannot coallesce.
1176 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1177 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1179 if (LHSIt->start < RHSIt->start) {
1180 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1181 if (LHSIt != LHS.begin()) --LHSIt;
1182 } else if (RHSIt->start < LHSIt->start) {
1183 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1184 if (RHSIt != RHS.begin()) --RHSIt;
1187 SmallVector<unsigned, 8> EliminatedLHSVals;
1190 // Determine if these live intervals overlap.
1191 bool Overlaps = false;
1192 if (LHSIt->start <= RHSIt->start)
1193 Overlaps = LHSIt->end > RHSIt->start;
1195 Overlaps = RHSIt->end > LHSIt->start;
1197 // If the live intervals overlap, there are two interesting cases: if the
1198 // LHS interval is defined by a copy from the RHS, it's ok and we record
1199 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1200 // coallesce these live ranges and we bail out.
1202 // If we haven't already recorded that this value # is safe, check it.
1203 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
1204 // Copy from the RHS?
1205 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
1206 if (rep(SrcReg) != RHS.reg)
1207 return false; // Nope, bail out.
1209 EliminatedLHSVals.push_back(LHSIt->ValId);
1212 // We know this entire LHS live range is okay, so skip it now.
1213 if (++LHSIt == LHSEnd) break;
1217 if (LHSIt->end < RHSIt->end) {
1218 if (++LHSIt == LHSEnd) break;
1220 // One interesting case to check here. It's possible that we have
1221 // something like "X3 = Y" which defines a new value number in the LHS,
1222 // and is the last use of this liverange of the RHS. In this case, we
1223 // want to notice this copy (so that it gets coallesced away) even though
1224 // the live ranges don't actually overlap.
1225 if (LHSIt->start == RHSIt->end) {
1226 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
1227 // We already know that this value number is going to be merged in
1228 // if coallescing succeeds. Just skip the liverange.
1229 if (++LHSIt == LHSEnd) break;
1231 // Otherwise, if this is a copy from the RHS, mark it as being merged
1233 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
1234 EliminatedLHSVals.push_back(LHSIt->ValId);
1236 // We know this entire LHS live range is okay, so skip it now.
1237 if (++LHSIt == LHSEnd) break;
1242 if (++RHSIt == RHSEnd) break;
1246 // If we got here, we know that the coallescing will be successful and that
1247 // the value numbers in EliminatedLHSVals will all be merged together. Since
1248 // the most common case is that EliminatedLHSVals has a single number, we
1249 // optimize for it: if there is more than one value, we merge them all into
1250 // the lowest numbered one, then handle the interval as if we were merging
1251 // with one value number.
1253 if (EliminatedLHSVals.size() > 1) {
1254 // Loop through all the equal value numbers merging them into the smallest
1256 unsigned Smallest = EliminatedLHSVals[0];
1257 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1258 if (EliminatedLHSVals[i] < Smallest) {
1259 // Merge the current notion of the smallest into the smaller one.
1260 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1261 Smallest = EliminatedLHSVals[i];
1263 // Merge into the smallest.
1264 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1267 LHSValNo = Smallest;
1269 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1270 LHSValNo = EliminatedLHSVals[0];
1273 // Okay, now that there is a single LHS value number that we're merging the
1274 // RHS into, update the value number info for the LHS to indicate that the
1275 // value number is defined where the RHS value number was.
1276 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1278 // Okay, the final step is to loop over the RHS live intervals, adding them to
1280 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1281 LHS.weight += RHS.weight;
1282 if (RHS.preference && !LHS.preference)
1283 LHS.preference = RHS.preference;
1288 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1289 /// returns false. Otherwise, if one of the intervals being joined is a
1290 /// physreg, this method always canonicalizes LHS to be it. The output
1291 /// "RHS" will not have been modified, so we can use this information
1292 /// below to update aliases.
1293 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1294 // Compute the final value assignment, assuming that the live ranges can be
1296 SmallVector<int, 16> LHSValNoAssignments;
1297 SmallVector<int, 16> RHSValNoAssignments;
1298 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1300 // If a live interval is a physical register, conservatively check if any
1301 // of its sub-registers is overlapping the live interval of the virtual
1302 // register. If so, do not coalesce.
1303 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
1304 *mri_->getSubRegisters(LHS.reg)) {
1305 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
1306 if (hasInterval(*SR) && RHS.overlaps(getInterval(*SR))) {
1307 DOUT << "Interfere with sub-register ";
1308 DEBUG(getInterval(*SR).print(DOUT, mri_));
1311 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
1312 *mri_->getSubRegisters(RHS.reg)) {
1313 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
1314 if (hasInterval(*SR) && LHS.overlaps(getInterval(*SR))) {
1315 DOUT << "Interfere with sub-register ";
1316 DEBUG(getInterval(*SR).print(DOUT, mri_));
1321 // Compute ultimate value numbers for the LHS and RHS values.
1322 if (RHS.containsOneValue()) {
1323 // Copies from a liveinterval with a single value are simple to handle and
1324 // very common, handle the special case here. This is important, because
1325 // often RHS is small and LHS is large (e.g. a physreg).
1327 // Find out if the RHS is defined as a copy from some value in the LHS.
1329 std::pair<unsigned,unsigned> RHSValNoInfo;
1330 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1331 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1332 // If RHS is not defined as a copy from the LHS, we can use simpler and
1333 // faster checks to see if the live ranges are coallescable. This joiner
1334 // can't swap the LHS/RHS intervals though.
1335 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1336 return SimpleJoin(LHS, RHS);
1338 RHSValNoInfo = RHS.getValNumInfo(0);
1341 // It was defined as a copy from the LHS, find out what value # it is.
1342 unsigned ValInst = RHS.getInstForValNum(0);
1343 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1344 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1347 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1348 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1349 ValueNumberInfo.resize(LHS.getNumValNums());
1351 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1352 // should now get updated.
1353 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1354 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1355 if (rep(LHSSrcReg) != RHS.reg) {
1356 // If this is not a copy from the RHS, its value number will be
1357 // unmodified by the coallescing.
1358 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1359 LHSValNoAssignments[VN] = VN;
1360 } else if (RHSValID == -1) {
1361 // Otherwise, it is a copy from the RHS, and we don't already have a
1362 // value# for it. Keep the current value number, but remember it.
1363 LHSValNoAssignments[VN] = RHSValID = VN;
1364 ValueNumberInfo[VN] = RHSValNoInfo;
1366 // Otherwise, use the specified value #.
1367 LHSValNoAssignments[VN] = RHSValID;
1368 if (VN != (unsigned)RHSValID)
1369 ValueNumberInfo[VN].first = ~1U;
1371 ValueNumberInfo[VN] = RHSValNoInfo;
1374 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1375 LHSValNoAssignments[VN] = VN;
1379 assert(RHSValID != -1 && "Didn't find value #?");
1380 RHSValNoAssignments[0] = RHSValID;
1383 // Loop over the value numbers of the LHS, seeing if any are defined from
1385 SmallVector<int, 16> LHSValsDefinedFromRHS;
1386 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1387 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1388 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1389 if (ValSrcReg == 0) // Src not defined by a copy?
1392 // DstReg is known to be a register in the LHS interval. If the src is
1393 // from the RHS interval, we can use its value #.
1394 if (rep(ValSrcReg) != RHS.reg)
1397 // Figure out the value # from the RHS.
1398 unsigned ValInst = LHS.getInstForValNum(VN);
1399 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1402 // Loop over the value numbers of the RHS, seeing if any are defined from
1404 SmallVector<int, 16> RHSValsDefinedFromLHS;
1405 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1406 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1407 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1408 if (ValSrcReg == 0) // Src not defined by a copy?
1411 // DstReg is known to be a register in the RHS interval. If the src is
1412 // from the LHS interval, we can use its value #.
1413 if (rep(ValSrcReg) != LHS.reg)
1416 // Figure out the value # from the LHS.
1417 unsigned ValInst = RHS.getInstForValNum(VN);
1418 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1421 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1422 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1423 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1425 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1426 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1428 ComputeUltimateVN(VN, ValueNumberInfo,
1429 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1430 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1432 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1433 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1435 // If this value number isn't a copy from the LHS, it's a new number.
1436 if (RHSValsDefinedFromLHS[VN] == -1) {
1437 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1438 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1442 ComputeUltimateVN(VN, ValueNumberInfo,
1443 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1444 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1448 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1449 // interval lists to see if these intervals are coallescable.
1450 LiveInterval::const_iterator I = LHS.begin();
1451 LiveInterval::const_iterator IE = LHS.end();
1452 LiveInterval::const_iterator J = RHS.begin();
1453 LiveInterval::const_iterator JE = RHS.end();
1455 // Skip ahead until the first place of potential sharing.
1456 if (I->start < J->start) {
1457 I = std::upper_bound(I, IE, J->start);
1458 if (I != LHS.begin()) --I;
1459 } else if (J->start < I->start) {
1460 J = std::upper_bound(J, JE, I->start);
1461 if (J != RHS.begin()) --J;
1465 // Determine if these two live ranges overlap.
1467 if (I->start < J->start) {
1468 Overlaps = I->end > J->start;
1470 Overlaps = J->end > I->start;
1473 // If so, check value # info to determine if they are really different.
1475 // If the live range overlap will map to the same value number in the
1476 // result liverange, we can still coallesce them. If not, we can't.
1477 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1481 if (I->end < J->end) {
1490 // If we get here, we know that we can coallesce the live ranges. Ask the
1491 // intervals to coallesce themselves now.
1492 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1499 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1500 // depth of the basic block (the unsigned), and then on the MBB number.
1501 struct DepthMBBCompare {
1502 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1503 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1504 if (LHS.first > RHS.first) return true; // Deeper loops first
1505 return LHS.first == RHS.first &&
1506 LHS.second->getNumber() < RHS.second->getNumber();
1512 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1513 std::vector<CopyRec> *TryAgain, bool PhysOnly) {
1514 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1516 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1518 MachineInstr *Inst = MII++;
1520 // If this isn't a copy, we can't join intervals.
1521 unsigned SrcReg, DstReg;
1522 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1524 if (TryAgain && !JoinCopy(Inst, SrcReg, DstReg, PhysOnly))
1525 TryAgain->push_back(getCopyRec(Inst, SrcReg, DstReg));
1530 void LiveIntervals::joinIntervals() {
1531 DOUT << "********** JOINING INTERVALS ***********\n";
1533 JoinedLIs.resize(getNumIntervals());
1536 std::vector<CopyRec> TryAgainList;
1537 const LoopInfo &LI = getAnalysis<LoopInfo>();
1538 if (LI.begin() == LI.end()) {
1539 // If there are no loops in the function, join intervals in function order.
1540 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1542 CopyCoallesceInMBB(I, &TryAgainList);
1544 // Otherwise, join intervals in inner loops before other intervals.
1545 // Unfortunately we can't just iterate over loop hierarchy here because
1546 // there may be more MBB's than BB's. Collect MBB's for sorting.
1548 // Join intervals in the function prolog first. We want to join physical
1549 // registers with virtual registers before the intervals got too long.
1550 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1551 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
1552 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1554 // Sort by loop depth.
1555 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1557 // Finally, join intervals in loop nest order.
1558 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1559 CopyCoallesceInMBB(MBBs[i].second, NULL, true);
1560 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1561 CopyCoallesceInMBB(MBBs[i].second, &TryAgainList, false);
1564 // Joining intervals can allow other intervals to be joined. Iteratively join
1565 // until we make no progress.
1566 bool ProgressMade = true;
1567 while (ProgressMade) {
1568 ProgressMade = false;
1570 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1571 CopyRec &TheCopy = TryAgainList[i];
1573 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1574 TheCopy.MI = 0; // Mark this one as done.
1575 ProgressMade = true;
1580 // Some live range has been lengthened due to colaescing, eliminate the
1581 // unnecessary kills.
1582 int RegNum = JoinedLIs.find_first();
1583 while (RegNum != -1) {
1584 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
1585 unsigned repReg = rep(Reg);
1586 LiveInterval &LI = getInterval(repReg);
1587 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
1588 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
1589 MachineInstr *Kill = svi.Kills[i];
1590 // Suppose vr1 = op vr2, x
1591 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
1592 // unless it is a two-address operand.
1593 if (isRemoved(Kill) || hasRegisterDef(Kill, repReg))
1595 if (LI.liveAt(getInstructionIndex(Kill) + InstrSlots::NUM))
1596 unsetRegisterKill(Kill, repReg);
1598 RegNum = JoinedLIs.find_next(RegNum);
1601 DOUT << "*** Register mapping ***\n";
1602 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1604 DOUT << " reg " << i << " -> ";
1605 DEBUG(printRegName(r2rMap_[i]));
1610 /// Return true if the two specified registers belong to different register
1611 /// classes. The registers may be either phys or virt regs.
1612 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1613 unsigned RegB) const {
1615 // Get the register classes for the first reg.
1616 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1617 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1618 "Shouldn't consider two physregs!");
1619 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1622 // Compare against the regclass for the second reg.
1623 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1624 if (MRegisterInfo::isVirtualRegister(RegB))
1625 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1627 return !RegClass->contains(RegB);
1630 /// lastRegisterUse - Returns the last use of the specific register between
1631 /// cycles Start and End. It also returns the use operand by reference. It
1632 /// returns NULL if there are no uses.
1634 LiveIntervals::lastRegisterUse(unsigned Reg, unsigned Start, unsigned End,
1635 MachineOperand *&MOU) {
1636 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1639 // Skip deleted instructions
1640 MachineInstr *MI = getInstructionFromIndex(e);
1641 while ((e - InstrSlots::NUM) >= s && !MI) {
1642 e -= InstrSlots::NUM;
1643 MI = getInstructionFromIndex(e);
1645 if (e < s || MI == NULL)
1648 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1649 MachineOperand &MO = MI->getOperand(i);
1650 if (MO.isReg() && MO.isUse() && MO.getReg() &&
1651 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1657 e -= InstrSlots::NUM;
1664 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1665 /// register. It returns NULL if the def is not found.
1666 MachineOperand *LiveIntervals::findDefOperand(MachineInstr *MI, unsigned Reg) {
1667 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1668 MachineOperand &MO = MI->getOperand(i);
1669 if (MO.isReg() && MO.isDef() &&
1670 mri_->regsOverlap(rep(MO.getReg()), Reg))
1676 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1677 /// of the specific instruction.
1678 void LiveIntervals::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1679 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1680 MachineOperand &MO = MI->getOperand(i);
1681 if (MO.isReg() && MO.isUse() && MO.isKill() && MO.getReg() &&
1682 mri_->regsOverlap(rep(MO.getReg()), Reg))
1687 /// hasRegisterDef - True if the instruction defines the specific register.
1689 bool LiveIntervals::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1690 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1691 MachineOperand &MO = MI->getOperand(i);
1692 if (MO.isReg() && MO.isDef() &&
1693 mri_->regsOverlap(rep(MO.getReg()), Reg))
1699 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1700 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1702 return LiveInterval(reg, Weight);