1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numIntervals, "Number of original intervals");
40 STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
41 STATISTIC(numJoins , "Number of interval joins performed");
42 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
43 STATISTIC(numFolded , "Number of loads/stores folded into instructions");
46 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
49 EnableJoining("join-liveintervals",
50 cl::desc("Coallesce copies (default=true)"),
54 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.addRequired<LiveVariables>();
56 AU.addPreservedID(PHIEliminationID);
57 AU.addRequiredID(PHIEliminationID);
58 AU.addRequiredID(TwoAddressInstructionPassID);
59 AU.addRequired<LoopInfo>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 void LiveIntervals::releaseMemory() {
71 static bool isZeroLengthInterval(LiveInterval *li) {
72 for (LiveInterval::Ranges::const_iterator
73 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
74 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
80 /// runOnMachineFunction - Register allocate the whole function
82 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
84 tm_ = &fn.getTarget();
85 mri_ = tm_->getRegisterInfo();
86 tii_ = tm_->getInstrInfo();
87 lv_ = &getAnalysis<LiveVariables>();
88 allocatableRegs_ = mri_->getAllocatableSet(fn);
89 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
91 // Number MachineInstrs and MachineBasicBlocks.
92 // Initialize MBB indexes to a sentinal.
93 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
96 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
98 // Set the MBB2IdxMap entry for this MBB.
99 MBB2IdxMap[MBB->getNumber()] = MIIndex;
101 // If this BB has any live ins, insert a dummy instruction at the
102 // beginning of the function that we will pretend "defines" the values. This
103 // is to make the interval analysis simpler by providing a number.
104 if (MBB->livein_begin() != MBB->livein_end()) {
105 unsigned FirstLiveIn = *MBB->livein_begin();
107 // Find a reg class that contains this live in.
108 const TargetRegisterClass *RC = 0;
109 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
110 RCE = mri_->regclass_end(); RCI != RCE; ++RCI)
111 if ((*RCI)->contains(FirstLiveIn)) {
116 MachineInstr *OldFirstMI = MBB->begin();
117 mri_->copyRegToReg(*MBB, MBB->begin(),
118 FirstLiveIn, FirstLiveIn, RC);
119 assert(OldFirstMI != MBB->begin() &&
120 "copyRetToReg didn't insert anything!");
123 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
125 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
126 assert(inserted && "multiple MachineInstr -> index mappings");
127 i2miMap_.push_back(I);
128 MIIndex += InstrSlots::NUM;
134 numIntervals += getNumIntervals();
136 DOUT << "********** INTERVALS **********\n";
137 for (iterator I = begin(), E = end(); I != E; ++I) {
138 I->second.print(DOUT, mri_);
142 // Join (coallesce) intervals if requested.
143 if (EnableJoining) joinIntervals();
145 numIntervalsAfter += getNumIntervals();
148 // perform a final pass over the instructions and compute spill
149 // weights, coalesce virtual registers and remove identity moves.
150 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
152 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
153 mbbi != mbbe; ++mbbi) {
154 MachineBasicBlock* mbb = mbbi;
155 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
157 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
159 // if the move will be an identity move delete it
160 unsigned srcReg, dstReg, RegRep;
161 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
162 (RegRep = rep(srcReg)) == rep(dstReg)) {
163 // remove from def list
164 getOrCreateInterval(RegRep);
165 RemoveMachineInstrFromMaps(mii);
166 mii = mbbi->erase(mii);
170 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
171 const MachineOperand &mop = mii->getOperand(i);
172 if (mop.isRegister() && mop.getReg() &&
173 MRegisterInfo::isVirtualRegister(mop.getReg())) {
174 // replace register with representative register
175 unsigned reg = rep(mop.getReg());
176 mii->getOperand(i).setReg(reg);
178 LiveInterval &RegInt = getInterval(reg);
180 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
189 for (iterator I = begin(), E = end(); I != E; ++I) {
190 LiveInterval &LI = I->second;
191 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
192 // If the live interval length is essentially zero, i.e. in every live
193 // range the use follows def immediately, it doesn't make sense to spill
194 // it and hope it will be easier to allocate for this li.
195 if (isZeroLengthInterval(&LI))
196 LI.weight = HUGE_VALF;
198 // Divide the weight of the interval by its size. This encourages
199 // spilling of intervals that are large and have few uses, and
200 // discourages spilling of small intervals with many uses.
202 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II)
203 Size += II->end - II->start;
213 /// print - Implement the dump method.
214 void LiveIntervals::print(std::ostream &O, const Module* ) const {
215 O << "********** INTERVALS **********\n";
216 for (const_iterator I = begin(), E = end(); I != E; ++I) {
217 I->second.print(DOUT, mri_);
221 O << "********** MACHINEINSTRS **********\n";
222 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
223 mbbi != mbbe; ++mbbi) {
224 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
225 for (MachineBasicBlock::iterator mii = mbbi->begin(),
226 mie = mbbi->end(); mii != mie; ++mii) {
227 O << getInstructionIndex(mii) << '\t' << *mii;
232 /// CreateNewLiveInterval - Create a new live interval with the given live
233 /// ranges. The new live interval will have an infinite spill weight.
235 LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
236 const std::vector<LiveRange> &LRs) {
237 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
239 // Create a new virtual register for the spill interval.
240 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
242 // Replace the old virtual registers in the machine operands with the shiny
244 for (std::vector<LiveRange>::const_iterator
245 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
246 unsigned Index = getBaseIndex(I->start);
247 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
249 for (; Index != End; Index += InstrSlots::NUM) {
250 // Skip deleted instructions
251 while (Index != End && !getInstructionFromIndex(Index))
252 Index += InstrSlots::NUM;
254 if (Index == End) break;
256 MachineInstr *MI = getInstructionFromIndex(Index);
258 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
259 MachineOperand &MOp = MI->getOperand(J);
260 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg)
266 LiveInterval &NewLI = getOrCreateInterval(NewVReg);
268 // The spill weight is now infinity as it cannot be spilled again
269 NewLI.weight = float(HUGE_VAL);
271 for (std::vector<LiveRange>::const_iterator
272 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
273 DOUT << " Adding live range " << *I << " to new interval\n";
277 DOUT << "Created new live interval " << NewLI << "\n";
281 std::vector<LiveInterval*> LiveIntervals::
282 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
283 // since this is called after the analysis is done we don't know if
284 // LiveVariables is available
285 lv_ = getAnalysisToUpdate<LiveVariables>();
287 std::vector<LiveInterval*> added;
289 assert(li.weight != HUGE_VALF &&
290 "attempt to spill already spilled interval!");
292 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
293 li.print(DOUT, mri_);
296 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
298 for (LiveInterval::Ranges::const_iterator
299 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
300 unsigned index = getBaseIndex(i->start);
301 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
302 for (; index != end; index += InstrSlots::NUM) {
303 // skip deleted instructions
304 while (index != end && !getInstructionFromIndex(index))
305 index += InstrSlots::NUM;
306 if (index == end) break;
308 MachineInstr *MI = getInstructionFromIndex(index);
311 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
312 MachineOperand& mop = MI->getOperand(i);
313 if (mop.isRegister() && mop.getReg() == li.reg) {
314 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) {
315 // Attempt to fold the memory reference into the instruction. If we
316 // can do this, we don't need to insert spill code.
318 lv_->instructionChanged(MI, fmi);
319 MachineBasicBlock &MBB = *MI->getParent();
320 vrm.virtFolded(li.reg, MI, i, fmi);
322 i2miMap_[index/InstrSlots::NUM] = fmi;
323 mi2iMap_[fmi] = index;
324 MI = MBB.insert(MBB.erase(MI), fmi);
326 // Folding the load/store can completely change the instruction in
327 // unpredictable ways, rescan it from the beginning.
328 goto RestartInstruction;
330 // Create a new virtual register for the spill interval.
331 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
333 // Scan all of the operands of this instruction rewriting operands
334 // to use NewVReg instead of li.reg as appropriate. We do this for
337 // 1. If the instr reads the same spilled vreg multiple times, we
338 // want to reuse the NewVReg.
339 // 2. If the instr is a two-addr instruction, we are required to
340 // keep the src/dst regs pinned.
342 // Keep track of whether we replace a use and/or def so that we can
343 // create the spill interval with the appropriate range.
346 bool HasUse = mop.isUse();
347 bool HasDef = mop.isDef();
348 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
349 if (MI->getOperand(j).isReg() &&
350 MI->getOperand(j).getReg() == li.reg) {
351 MI->getOperand(j).setReg(NewVReg);
352 HasUse |= MI->getOperand(j).isUse();
353 HasDef |= MI->getOperand(j).isDef();
357 // create a new register for this spill
359 vrm.assignVirt2StackSlot(NewVReg, slot);
360 LiveInterval &nI = getOrCreateInterval(NewVReg);
363 // the spill weight is now infinity as it
364 // cannot be spilled again
365 nI.weight = HUGE_VALF;
368 LiveRange LR(getLoadIndex(index), getUseIndex(index),
369 nI.getNextValue(~0U, 0));
374 LiveRange LR(getDefIndex(index), getStoreIndex(index),
375 nI.getNextValue(~0U, 0));
380 added.push_back(&nI);
382 // update live variables if it is available
384 lv_->addVirtualRegisterKilled(NewVReg, MI);
386 DOUT << "\t\t\t\tadded new interval: ";
387 nI.print(DOUT, mri_);
398 void LiveIntervals::printRegName(unsigned reg) const {
399 if (MRegisterInfo::isPhysicalRegister(reg))
400 cerr << mri_->getName(reg);
402 cerr << "%reg" << reg;
405 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
406 /// two addr elimination.
407 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
408 const TargetInstrInfo *TII) {
409 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
410 MachineOperand &MO1 = MI->getOperand(i);
411 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
412 for (unsigned j = i+1; j < e; ++j) {
413 MachineOperand &MO2 = MI->getOperand(j);
414 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
415 MI->getInstrDescriptor()->
416 getOperandConstraint(j, TOI::TIED_TO) == (int)i)
424 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
425 MachineBasicBlock::iterator mi,
427 LiveInterval &interval) {
428 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
429 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
431 // Virtual registers may be defined multiple times (due to phi
432 // elimination and 2-addr elimination). Much of what we do only has to be
433 // done once for the vreg. We use an empty interval to detect the first
434 // time we see a vreg.
435 if (interval.empty()) {
436 // Get the Idx of the defining instructions.
437 unsigned defIndex = getDefIndex(MIIdx);
440 unsigned SrcReg, DstReg;
441 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
442 ValNum = interval.getNextValue(~0U, 0);
444 ValNum = interval.getNextValue(defIndex, SrcReg);
446 assert(ValNum == 0 && "First value in interval is not 0?");
447 ValNum = 0; // Clue in the optimizer.
449 // Loop over all of the blocks that the vreg is defined in. There are
450 // two cases we have to handle here. The most common case is a vreg
451 // whose lifetime is contained within a basic block. In this case there
452 // will be a single kill, in MBB, which comes after the definition.
453 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
454 // FIXME: what about dead vars?
456 if (vi.Kills[0] != mi)
457 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
459 killIdx = defIndex+1;
461 // If the kill happens after the definition, we have an intra-block
463 if (killIdx > defIndex) {
464 assert(vi.AliveBlocks.empty() &&
465 "Shouldn't be alive across any blocks!");
466 LiveRange LR(defIndex, killIdx, ValNum);
467 interval.addRange(LR);
468 DOUT << " +" << LR << "\n";
473 // The other case we handle is when a virtual register lives to the end
474 // of the defining block, potentially live across some blocks, then is
475 // live into some number of blocks, but gets killed. Start by adding a
476 // range that goes from this definition to the end of the defining block.
477 LiveRange NewLR(defIndex,
478 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
480 DOUT << " +" << NewLR;
481 interval.addRange(NewLR);
483 // Iterate over all of the blocks that the variable is completely
484 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
486 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
487 if (vi.AliveBlocks[i]) {
488 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
490 LiveRange LR(getMBBStartIdx(i),
491 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
493 interval.addRange(LR);
499 // Finally, this virtual register is live from the start of any killing
500 // block to the 'use' slot of the killing instruction.
501 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
502 MachineInstr *Kill = vi.Kills[i];
503 LiveRange LR(getMBBStartIdx(Kill->getParent()),
504 getUseIndex(getInstructionIndex(Kill))+1,
506 interval.addRange(LR);
511 // If this is the second time we see a virtual register definition, it
512 // must be due to phi elimination or two addr elimination. If this is
513 // the result of two address elimination, then the vreg is one of the
514 // def-and-use register operand.
515 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
516 // If this is a two-address definition, then we have already processed
517 // the live range. The only problem is that we didn't realize there
518 // are actually two values in the live interval. Because of this we
519 // need to take the LiveRegion that defines this register and split it
521 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
522 unsigned RedefIndex = getDefIndex(MIIdx);
524 // Delete the initial value, which should be short and continuous,
525 // because the 2-addr copy must be in the same MBB as the redef.
526 interval.removeRange(DefIndex, RedefIndex);
528 // Two-address vregs should always only be redefined once. This means
529 // that at this point, there should be exactly one value number in it.
530 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
532 // The new value number (#1) is defined by the instruction we claimed
534 unsigned ValNo = interval.getNextValue(0, 0);
535 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
537 // Value#0 is now defined by the 2-addr instruction.
538 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
540 // Add the new live interval which replaces the range for the input copy.
541 LiveRange LR(DefIndex, RedefIndex, ValNo);
542 DOUT << " replace range with " << LR;
543 interval.addRange(LR);
545 // If this redefinition is dead, we need to add a dummy unit live
546 // range covering the def slot.
547 if (lv_->RegisterDefIsDead(mi, interval.reg))
548 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
551 interval.print(DOUT, mri_);
554 // Otherwise, this must be because of phi elimination. If this is the
555 // first redefinition of the vreg that we have seen, go back and change
556 // the live range in the PHI block to be a different value number.
557 if (interval.containsOneValue()) {
558 assert(vi.Kills.size() == 1 &&
559 "PHI elimination vreg should have one kill, the PHI itself!");
561 // Remove the old range that we now know has an incorrect number.
562 MachineInstr *Killer = vi.Kills[0];
563 unsigned Start = getMBBStartIdx(Killer->getParent());
564 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
565 DOUT << "Removing [" << Start << "," << End << "] from: ";
566 interval.print(DOUT, mri_); DOUT << "\n";
567 interval.removeRange(Start, End);
568 DOUT << "RESULT: "; interval.print(DOUT, mri_);
570 // Replace the interval with one of a NEW value number. Note that this
571 // value number isn't actually defined by an instruction, weird huh? :)
572 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
573 DOUT << " replace range with " << LR;
574 interval.addRange(LR);
575 DOUT << "RESULT: "; interval.print(DOUT, mri_);
578 // In the case of PHI elimination, each variable definition is only
579 // live until the end of the block. We've already taken care of the
580 // rest of the live range.
581 unsigned defIndex = getDefIndex(MIIdx);
584 unsigned SrcReg, DstReg;
585 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
586 ValNum = interval.getNextValue(~0U, 0);
588 ValNum = interval.getNextValue(defIndex, SrcReg);
590 LiveRange LR(defIndex,
591 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
592 interval.addRange(LR);
600 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
601 MachineBasicBlock::iterator mi,
603 LiveInterval &interval,
605 // A physical register cannot be live across basic block, so its
606 // lifetime must end somewhere in its defining basic block.
607 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
609 unsigned baseIndex = MIIdx;
610 unsigned start = getDefIndex(baseIndex);
611 unsigned end = start;
613 // If it is not used after definition, it is considered dead at
614 // the instruction defining it. Hence its interval is:
615 // [defSlot(def), defSlot(def)+1)
616 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
618 end = getDefIndex(start) + 1;
622 // If it is not dead on definition, it must be killed by a
623 // subsequent instruction. Hence its interval is:
624 // [defSlot(def), useSlot(kill)+1)
625 while (++mi != MBB->end()) {
626 baseIndex += InstrSlots::NUM;
627 if (lv_->KillsRegister(mi, interval.reg)) {
629 end = getUseIndex(baseIndex) + 1;
631 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
632 // Another instruction redefines the register before it is ever read.
633 // Then the register is essentially dead at the instruction that defines
634 // it. Hence its interval is:
635 // [defSlot(def), defSlot(def)+1)
637 end = getDefIndex(start) + 1;
642 // The only case we should have a dead physreg here without a killing or
643 // instruction where we know it's dead is if it is live-in to the function
645 assert(!SrcReg && "physreg was not killed in defining block!");
646 end = getDefIndex(start) + 1; // It's dead.
649 assert(start < end && "did not find end of interval?");
651 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
653 interval.addRange(LR);
654 DOUT << " +" << LR << '\n';
657 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
658 MachineBasicBlock::iterator MI,
661 if (MRegisterInfo::isVirtualRegister(reg))
662 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
663 else if (allocatableRegs_[reg]) {
664 unsigned SrcReg, DstReg;
665 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
667 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
668 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
669 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
673 /// computeIntervals - computes the live intervals for virtual
674 /// registers. for some ordering of the machine instructions [1,N] a
675 /// live interval is an interval [i, j) where 1 <= i <= j < N for
676 /// which a variable is live
677 void LiveIntervals::computeIntervals() {
678 DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
679 << "********** Function: "
680 << ((Value*)mf_->getFunction())->getName() << '\n';
681 // Track the index of the current machine instr.
682 unsigned MIIndex = 0;
683 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
685 MachineBasicBlock *MBB = MBBI;
686 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
688 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
690 if (MBB->livein_begin() != MBB->livein_end()) {
691 // Process live-ins to this BB first.
692 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
693 LE = MBB->livein_end(); LI != LE; ++LI) {
694 handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
695 getOrCreateInterval(*LI), 0);
696 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
697 handlePhysicalRegisterDef(MBB, MBB->begin(), MIIndex,
698 getOrCreateInterval(*AS), 0);
701 MIIndex += InstrSlots::NUM;
704 for (; MI != miEnd; ++MI) {
705 DOUT << MIIndex << "\t" << *MI;
708 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
709 MachineOperand &MO = MI->getOperand(i);
710 // handle register defs - build intervals
711 if (MO.isRegister() && MO.getReg() && MO.isDef())
712 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
715 MIIndex += InstrSlots::NUM;
720 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
721 /// being the source and IntB being the dest, thus this defines a value number
722 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
723 /// see if we can merge these two pieces of B into a single value number,
724 /// eliminating a copy. For example:
728 /// B1 = A3 <- this copy
730 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
731 /// value number to be replaced with B0 (which simplifies the B liveinterval).
733 /// This returns true if an interval was modified.
735 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
736 MachineInstr *CopyMI) {
737 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
739 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
740 // the example above.
741 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
742 unsigned BValNo = BLR->ValId;
744 // Get the location that B is defined at. Two options: either this value has
745 // an unknown definition point or it is defined at CopyIdx. If unknown, we
747 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
748 if (BValNoDefIdx == ~0U) return false;
749 assert(BValNoDefIdx == CopyIdx &&
750 "Copy doesn't define the value?");
752 // AValNo is the value number in A that defines the copy, A0 in the example.
753 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
754 unsigned AValNo = AValLR->ValId;
756 // If AValNo is defined as a copy from IntB, we can potentially process this.
758 // Get the instruction that defines this value number.
759 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
760 if (!SrcReg) return false; // Not defined by a copy.
762 // If the value number is not defined by a copy instruction, ignore it.
764 // If the source register comes from an interval other than IntB, we can't
766 if (rep(SrcReg) != IntB.reg) return false;
768 // Get the LiveRange in IntB that this value number starts with.
769 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
770 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
772 // Make sure that the end of the live range is inside the same block as
774 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
776 ValLREndInst->getParent() != CopyMI->getParent()) return false;
778 // Okay, we now know that ValLR ends in the same block that the CopyMI
779 // live-range starts. If there are no intervening live ranges between them in
780 // IntB, we can merge them.
781 if (ValLR+1 != BLR) return false;
783 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
785 // We are about to delete CopyMI, so need to remove it as the 'instruction
786 // that defines this value #'.
787 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
789 // Okay, we can merge them. We need to insert a new liverange:
790 // [ValLR.end, BLR.begin) of either value number, then we merge the
791 // two value numbers.
792 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
793 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
795 // If the IntB live range is assigned to a physical register, and if that
796 // physreg has aliases,
797 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
798 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
799 LiveInterval &AliasLI = getInterval(*AS);
800 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
801 AliasLI.getNextValue(~0U, 0)));
805 // Okay, merge "B1" into the same value number as "B0".
806 if (BValNo != ValLR->ValId)
807 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
808 DOUT << " result = "; IntB.print(DOUT, mri_);
811 // Finally, delete the copy instruction.
812 RemoveMachineInstrFromMaps(CopyMI);
813 CopyMI->eraseFromParent();
819 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
820 /// which are the src/dst of the copy instruction CopyMI. This returns true
821 /// if the copy was successfully coallesced away, or if it is never possible
822 /// to coallesce these this copy, due to register constraints. It returns
823 /// false if it is not currently possible to coallesce this interval, but
824 /// it may be possible if other things get coallesced.
825 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
826 unsigned SrcReg, unsigned DstReg) {
827 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
829 // Get representative registers.
830 SrcReg = rep(SrcReg);
831 DstReg = rep(DstReg);
833 // If they are already joined we continue.
834 if (SrcReg == DstReg) {
835 DOUT << "\tCopy already coallesced.\n";
836 return true; // Not coallescable.
839 // If they are both physical registers, we cannot join them.
840 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
841 MRegisterInfo::isPhysicalRegister(DstReg)) {
842 DOUT << "\tCan not coallesce physregs.\n";
843 return true; // Not coallescable.
846 // We only join virtual registers with allocatable physical registers.
847 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
848 DOUT << "\tSrc reg is unallocatable physreg.\n";
849 return true; // Not coallescable.
851 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
852 DOUT << "\tDst reg is unallocatable physreg.\n";
853 return true; // Not coallescable.
856 // If they are not of the same register class, we cannot join them.
857 if (differingRegisterClasses(SrcReg, DstReg)) {
858 DOUT << "\tSrc/Dest are different register classes.\n";
859 return true; // Not coallescable.
862 LiveInterval &SrcInt = getInterval(SrcReg);
863 LiveInterval &DestInt = getInterval(DstReg);
864 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
865 "Register mapping is horribly broken!");
867 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
868 DOUT << " and "; DestInt.print(DOUT, mri_);
871 // Okay, attempt to join these two intervals. On failure, this returns false.
872 // Otherwise, if one of the intervals being joined is a physreg, this method
873 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
874 // been modified, so we can use this information below to update aliases.
875 if (!JoinIntervals(DestInt, SrcInt)) {
876 // Coallescing failed.
878 // If we can eliminate the copy without merging the live ranges, do so now.
879 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
882 // Otherwise, we are unable to join the intervals.
883 DOUT << "Interference!\n";
887 bool Swapped = SrcReg == DestInt.reg;
889 std::swap(SrcReg, DstReg);
890 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
891 "LiveInterval::join didn't work right!");
893 // If we're about to merge live ranges into a physical register live range,
894 // we have to update any aliased register's live ranges to indicate that they
895 // have clobbered values for this range.
896 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
897 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
898 getInterval(*AS).MergeInClobberRanges(SrcInt);
901 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_);
904 // If the intervals were swapped by Join, swap them back so that the register
905 // mapping (in the r2i map) is correct.
906 if (Swapped) SrcInt.swap(DestInt);
907 r2iMap_.erase(SrcReg);
908 r2rMap_[SrcReg] = DstReg;
910 // Finally, delete the copy instruction.
911 RemoveMachineInstrFromMaps(CopyMI);
912 CopyMI->eraseFromParent();
918 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
919 /// compute what the resultant value numbers for each value in the input two
920 /// ranges will be. This is complicated by copies between the two which can
921 /// and will commonly cause multiple value numbers to be merged into one.
923 /// VN is the value number that we're trying to resolve. InstDefiningValue
924 /// keeps track of the new InstDefiningValue assignment for the result
925 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
926 /// whether a value in this or other is a copy from the opposite set.
927 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
928 /// already been assigned.
930 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
931 /// contains the value number the copy is from.
933 static unsigned ComputeUltimateVN(unsigned VN,
934 SmallVector<std::pair<unsigned,
935 unsigned>, 16> &ValueNumberInfo,
936 SmallVector<int, 16> &ThisFromOther,
937 SmallVector<int, 16> &OtherFromThis,
938 SmallVector<int, 16> &ThisValNoAssignments,
939 SmallVector<int, 16> &OtherValNoAssignments,
940 LiveInterval &ThisLI, LiveInterval &OtherLI) {
941 // If the VN has already been computed, just return it.
942 if (ThisValNoAssignments[VN] >= 0)
943 return ThisValNoAssignments[VN];
944 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
946 // If this val is not a copy from the other val, then it must be a new value
947 // number in the destination.
948 int OtherValNo = ThisFromOther[VN];
949 if (OtherValNo == -1) {
950 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
951 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
954 // Otherwise, this *is* a copy from the RHS. If the other side has already
955 // been computed, return it.
956 if (OtherValNoAssignments[OtherValNo] >= 0)
957 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
959 // Mark this value number as currently being computed, then ask what the
960 // ultimate value # of the other value is.
961 ThisValNoAssignments[VN] = -2;
962 unsigned UltimateVN =
963 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
964 OtherFromThis, ThisFromOther,
965 OtherValNoAssignments, ThisValNoAssignments,
967 return ThisValNoAssignments[VN] = UltimateVN;
970 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
971 return std::find(V.begin(), V.end(), Val) != V.end();
974 /// SimpleJoin - Attempt to joint the specified interval into this one. The
975 /// caller of this method must guarantee that the RHS only contains a single
976 /// value number and that the RHS is not defined by a copy from this
977 /// interval. This returns false if the intervals are not joinable, or it
978 /// joins them and returns true.
979 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
980 assert(RHS.containsOneValue());
982 // Some number (potentially more than one) value numbers in the current
983 // interval may be defined as copies from the RHS. Scan the overlapping
984 // portions of the LHS and RHS, keeping track of this and looking for
985 // overlapping live ranges that are NOT defined as copies. If these exist, we
988 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
989 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
991 if (LHSIt->start < RHSIt->start) {
992 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
993 if (LHSIt != LHS.begin()) --LHSIt;
994 } else if (RHSIt->start < LHSIt->start) {
995 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
996 if (RHSIt != RHS.begin()) --RHSIt;
999 SmallVector<unsigned, 8> EliminatedLHSVals;
1002 // Determine if these live intervals overlap.
1003 bool Overlaps = false;
1004 if (LHSIt->start <= RHSIt->start)
1005 Overlaps = LHSIt->end > RHSIt->start;
1007 Overlaps = RHSIt->end > LHSIt->start;
1009 // If the live intervals overlap, there are two interesting cases: if the
1010 // LHS interval is defined by a copy from the RHS, it's ok and we record
1011 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1012 // coallesce these live ranges and we bail out.
1014 // If we haven't already recorded that this value # is safe, check it.
1015 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
1016 // Copy from the RHS?
1017 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
1018 if (rep(SrcReg) != RHS.reg)
1019 return false; // Nope, bail out.
1021 EliminatedLHSVals.push_back(LHSIt->ValId);
1024 // We know this entire LHS live range is okay, so skip it now.
1025 if (++LHSIt == LHSEnd) break;
1029 if (LHSIt->end < RHSIt->end) {
1030 if (++LHSIt == LHSEnd) break;
1032 // One interesting case to check here. It's possible that we have
1033 // something like "X3 = Y" which defines a new value number in the LHS,
1034 // and is the last use of this liverange of the RHS. In this case, we
1035 // want to notice this copy (so that it gets coallesced away) even though
1036 // the live ranges don't actually overlap.
1037 if (LHSIt->start == RHSIt->end) {
1038 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
1039 // We already know that this value number is going to be merged in
1040 // if coallescing succeeds. Just skip the liverange.
1041 if (++LHSIt == LHSEnd) break;
1043 // Otherwise, if this is a copy from the RHS, mark it as being merged
1045 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
1046 EliminatedLHSVals.push_back(LHSIt->ValId);
1048 // We know this entire LHS live range is okay, so skip it now.
1049 if (++LHSIt == LHSEnd) break;
1054 if (++RHSIt == RHSEnd) break;
1058 // If we got here, we know that the coallescing will be successful and that
1059 // the value numbers in EliminatedLHSVals will all be merged together. Since
1060 // the most common case is that EliminatedLHSVals has a single number, we
1061 // optimize for it: if there is more than one value, we merge them all into
1062 // the lowest numbered one, then handle the interval as if we were merging
1063 // with one value number.
1065 if (EliminatedLHSVals.size() > 1) {
1066 // Loop through all the equal value numbers merging them into the smallest
1068 unsigned Smallest = EliminatedLHSVals[0];
1069 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1070 if (EliminatedLHSVals[i] < Smallest) {
1071 // Merge the current notion of the smallest into the smaller one.
1072 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1073 Smallest = EliminatedLHSVals[i];
1075 // Merge into the smallest.
1076 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1079 LHSValNo = Smallest;
1081 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1082 LHSValNo = EliminatedLHSVals[0];
1085 // Okay, now that there is a single LHS value number that we're merging the
1086 // RHS into, update the value number info for the LHS to indicate that the
1087 // value number is defined where the RHS value number was.
1088 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1090 // Okay, the final step is to loop over the RHS live intervals, adding them to
1092 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1093 LHS.weight += RHS.weight;
1098 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1099 /// returns false. Otherwise, if one of the intervals being joined is a
1100 /// physreg, this method always canonicalizes LHS to be it. The output
1101 /// "RHS" will not have been modified, so we can use this information
1102 /// below to update aliases.
1103 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1104 // Compute the final value assignment, assuming that the live ranges can be
1106 SmallVector<int, 16> LHSValNoAssignments;
1107 SmallVector<int, 16> RHSValNoAssignments;
1108 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1110 // Compute ultimate value numbers for the LHS and RHS values.
1111 if (RHS.containsOneValue()) {
1112 // Copies from a liveinterval with a single value are simple to handle and
1113 // very common, handle the special case here. This is important, because
1114 // often RHS is small and LHS is large (e.g. a physreg).
1116 // Find out if the RHS is defined as a copy from some value in the LHS.
1118 std::pair<unsigned,unsigned> RHSValNoInfo;
1119 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1120 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1121 // If RHS is not defined as a copy from the LHS, we can use simpler and
1122 // faster checks to see if the live ranges are coallescable. This joiner
1123 // can't swap the LHS/RHS intervals though.
1124 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1125 return SimpleJoin(LHS, RHS);
1127 RHSValNoInfo = RHS.getValNumInfo(0);
1130 // It was defined as a copy from the LHS, find out what value # it is.
1131 unsigned ValInst = RHS.getInstForValNum(0);
1132 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1133 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1136 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1137 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1138 ValueNumberInfo.resize(LHS.getNumValNums());
1140 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1141 // should now get updated.
1142 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1143 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1144 if (rep(LHSSrcReg) != RHS.reg) {
1145 // If this is not a copy from the RHS, its value number will be
1146 // unmodified by the coallescing.
1147 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1148 LHSValNoAssignments[VN] = VN;
1149 } else if (RHSValID == -1) {
1150 // Otherwise, it is a copy from the RHS, and we don't already have a
1151 // value# for it. Keep the current value number, but remember it.
1152 LHSValNoAssignments[VN] = RHSValID = VN;
1153 ValueNumberInfo[VN] = RHSValNoInfo;
1155 // Otherwise, use the specified value #.
1156 LHSValNoAssignments[VN] = RHSValID;
1157 if (VN != (unsigned)RHSValID)
1158 ValueNumberInfo[VN].first = ~1U;
1160 ValueNumberInfo[VN] = RHSValNoInfo;
1163 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1164 LHSValNoAssignments[VN] = VN;
1168 assert(RHSValID != -1 && "Didn't find value #?");
1169 RHSValNoAssignments[0] = RHSValID;
1172 // Loop over the value numbers of the LHS, seeing if any are defined from
1174 SmallVector<int, 16> LHSValsDefinedFromRHS;
1175 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1176 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1177 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1178 if (ValSrcReg == 0) // Src not defined by a copy?
1181 // DstReg is known to be a register in the LHS interval. If the src is
1182 // from the RHS interval, we can use its value #.
1183 if (rep(ValSrcReg) != RHS.reg)
1186 // Figure out the value # from the RHS.
1187 unsigned ValInst = LHS.getInstForValNum(VN);
1188 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1191 // Loop over the value numbers of the RHS, seeing if any are defined from
1193 SmallVector<int, 16> RHSValsDefinedFromLHS;
1194 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1195 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1196 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1197 if (ValSrcReg == 0) // Src not defined by a copy?
1200 // DstReg is known to be a register in the RHS interval. If the src is
1201 // from the LHS interval, we can use its value #.
1202 if (rep(ValSrcReg) != LHS.reg)
1205 // Figure out the value # from the LHS.
1206 unsigned ValInst = RHS.getInstForValNum(VN);
1207 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1210 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1211 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1212 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1214 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1215 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1217 ComputeUltimateVN(VN, ValueNumberInfo,
1218 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1219 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1221 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1222 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1224 // If this value number isn't a copy from the LHS, it's a new number.
1225 if (RHSValsDefinedFromLHS[VN] == -1) {
1226 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1227 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1231 ComputeUltimateVN(VN, ValueNumberInfo,
1232 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1233 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1237 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1238 // interval lists to see if these intervals are coallescable.
1239 LiveInterval::const_iterator I = LHS.begin();
1240 LiveInterval::const_iterator IE = LHS.end();
1241 LiveInterval::const_iterator J = RHS.begin();
1242 LiveInterval::const_iterator JE = RHS.end();
1244 // Skip ahead until the first place of potential sharing.
1245 if (I->start < J->start) {
1246 I = std::upper_bound(I, IE, J->start);
1247 if (I != LHS.begin()) --I;
1248 } else if (J->start < I->start) {
1249 J = std::upper_bound(J, JE, I->start);
1250 if (J != RHS.begin()) --J;
1254 // Determine if these two live ranges overlap.
1256 if (I->start < J->start) {
1257 Overlaps = I->end > J->start;
1259 Overlaps = J->end > I->start;
1262 // If so, check value # info to determine if they are really different.
1264 // If the live range overlap will map to the same value number in the
1265 // result liverange, we can still coallesce them. If not, we can't.
1266 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1270 if (I->end < J->end) {
1279 // If we get here, we know that we can coallesce the live ranges. Ask the
1280 // intervals to coallesce themselves now.
1281 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1288 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1289 // depth of the basic block (the unsigned), and then on the MBB number.
1290 struct DepthMBBCompare {
1291 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1292 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1293 if (LHS.first > RHS.first) return true; // Deeper loops first
1294 return LHS.first == RHS.first &&
1295 LHS.second->getNumber() < RHS.second->getNumber();
1301 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1302 std::vector<CopyRec> &TryAgain) {
1303 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1305 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1307 MachineInstr *Inst = MII++;
1309 // If this isn't a copy, we can't join intervals.
1310 unsigned SrcReg, DstReg;
1311 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1313 if (!JoinCopy(Inst, SrcReg, DstReg))
1314 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
1319 void LiveIntervals::joinIntervals() {
1320 DOUT << "********** JOINING INTERVALS ***********\n";
1322 std::vector<CopyRec> TryAgainList;
1324 const LoopInfo &LI = getAnalysis<LoopInfo>();
1325 if (LI.begin() == LI.end()) {
1326 // If there are no loops in the function, join intervals in function order.
1327 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1329 CopyCoallesceInMBB(I, TryAgainList);
1331 // Otherwise, join intervals in inner loops before other intervals.
1332 // Unfortunately we can't just iterate over loop hierarchy here because
1333 // there may be more MBB's than BB's. Collect MBB's for sorting.
1334 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1335 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1337 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1339 // Sort by loop depth.
1340 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1342 // Finally, join intervals in loop nest order.
1343 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1344 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
1347 // Joining intervals can allow other intervals to be joined. Iteratively join
1348 // until we make no progress.
1349 bool ProgressMade = true;
1350 while (ProgressMade) {
1351 ProgressMade = false;
1353 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1354 CopyRec &TheCopy = TryAgainList[i];
1356 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1357 TheCopy.MI = 0; // Mark this one as done.
1358 ProgressMade = true;
1363 DOUT << "*** Register mapping ***\n";
1364 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1366 DOUT << " reg " << i << " -> ";
1367 DEBUG(printRegName(r2rMap_[i]));
1372 /// Return true if the two specified registers belong to different register
1373 /// classes. The registers may be either phys or virt regs.
1374 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1375 unsigned RegB) const {
1377 // Get the register classes for the first reg.
1378 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1379 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1380 "Shouldn't consider two physregs!");
1381 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1384 // Compare against the regclass for the second reg.
1385 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1386 if (MRegisterInfo::isVirtualRegister(RegB))
1387 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1389 return !RegClass->contains(RegB);
1392 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1393 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1395 return LiveInterval(reg, Weight);