1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
40 STATISTIC(numIntervals, "Number of original intervals");
41 STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numFolded , "Number of loads/stores folded into instructions");
45 STATISTIC(numAborts , "Number of times interval joining aborted");
47 char LiveIntervals::ID = 0;
49 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
52 EnableJoining("join-liveintervals",
53 cl::desc("Coallesce copies (default=true)"),
57 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
58 AU.addRequired<LiveVariables>();
59 AU.addPreservedID(PHIEliminationID);
60 AU.addRequiredID(PHIEliminationID);
61 AU.addRequiredID(TwoAddressInstructionPassID);
62 AU.addRequired<LoopInfo>();
63 MachineFunctionPass::getAnalysisUsage(AU);
66 void LiveIntervals::releaseMemory() {
75 static bool isZeroLengthInterval(LiveInterval *li) {
76 for (LiveInterval::Ranges::const_iterator
77 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
78 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
84 /// runOnMachineFunction - Register allocate the whole function
86 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
88 tm_ = &fn.getTarget();
89 mri_ = tm_->getRegisterInfo();
90 tii_ = tm_->getInstrInfo();
91 lv_ = &getAnalysis<LiveVariables>();
92 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
93 allocatableRegs_ = mri_->getAllocatableSet(fn);
94 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
95 E = mri_->regclass_end(); I != E; ++I)
96 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
98 // Number MachineInstrs and MachineBasicBlocks.
99 // Initialize MBB indexes to a sentinal.
100 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
102 unsigned MIIndex = 0;
103 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
105 // Set the MBB2IdxMap entry for this MBB.
106 MBB2IdxMap[MBB->getNumber()] = MIIndex;
108 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
110 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
111 assert(inserted && "multiple MachineInstr -> index mappings");
112 i2miMap_.push_back(I);
113 MIIndex += InstrSlots::NUM;
119 numIntervals += getNumIntervals();
121 DOUT << "********** INTERVALS **********\n";
122 for (iterator I = begin(), E = end(); I != E; ++I) {
123 I->second.print(DOUT, mri_);
127 // Join (coallesce) intervals if requested.
130 DOUT << "********** INTERVALS POST JOINING **********\n";
131 for (iterator I = begin(), E = end(); I != E; ++I) {
132 I->second.print(DOUT, mri_);
137 numIntervalsAfter += getNumIntervals();
139 // perform a final pass over the instructions and compute spill
140 // weights, coalesce virtual registers and remove identity moves.
141 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
143 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
144 mbbi != mbbe; ++mbbi) {
145 MachineBasicBlock* mbb = mbbi;
146 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
148 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
150 // if the move will be an identity move delete it
151 unsigned srcReg, dstReg, RegRep;
152 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
153 (RegRep = rep(srcReg)) == rep(dstReg)) {
154 // remove from def list
155 LiveInterval &RegInt = getOrCreateInterval(RegRep);
156 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
157 // If def of this move instruction is dead, remove its live range from
158 // the dstination register's live interval.
160 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
161 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
162 RegInt.removeRange(MLR->start, MoveIdx+1);
164 removeInterval(RegRep);
166 RemoveMachineInstrFromMaps(mii);
167 mii = mbbi->erase(mii);
170 SmallSet<unsigned, 4> UniqueUses;
171 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
172 const MachineOperand &mop = mii->getOperand(i);
173 if (mop.isRegister() && mop.getReg() &&
174 MRegisterInfo::isVirtualRegister(mop.getReg())) {
175 // replace register with representative register
176 unsigned reg = rep(mop.getReg());
177 mii->getOperand(i).setReg(reg);
179 // Multiple uses of reg by the same instruction. It should not
180 // contribute to spill weight again.
181 if (UniqueUses.count(reg) != 0)
183 LiveInterval &RegInt = getInterval(reg);
184 float w = (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
185 // If the definition instruction is re-materializable, its spill
186 // weight is half of what it would have been normally unless it's
187 // a load from fixed stack slot.
189 if (RegInt.remat && !tii_->isLoadFromStackSlot(RegInt.remat, Dummy))
192 UniqueUses.insert(reg);
200 for (iterator I = begin(), E = end(); I != E; ++I) {
201 LiveInterval &LI = I->second;
202 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
203 // If the live interval length is essentially zero, i.e. in every live
204 // range the use follows def immediately, it doesn't make sense to spill
205 // it and hope it will be easier to allocate for this li.
206 if (isZeroLengthInterval(&LI))
207 LI.weight = HUGE_VALF;
209 // Slightly prefer live interval that has been assigned a preferred reg.
213 // Divide the weight of the interval by its size. This encourages
214 // spilling of intervals that are large and have few uses, and
215 // discourages spilling of small intervals with many uses.
216 LI.weight /= LI.getSize();
224 /// print - Implement the dump method.
225 void LiveIntervals::print(std::ostream &O, const Module* ) const {
226 O << "********** INTERVALS **********\n";
227 for (const_iterator I = begin(), E = end(); I != E; ++I) {
228 I->second.print(DOUT, mri_);
232 O << "********** MACHINEINSTRS **********\n";
233 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
234 mbbi != mbbe; ++mbbi) {
235 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
236 for (MachineBasicBlock::iterator mii = mbbi->begin(),
237 mie = mbbi->end(); mii != mie; ++mii) {
238 O << getInstructionIndex(mii) << '\t' << *mii;
243 /// CreateNewLiveInterval - Create a new live interval with the given live
244 /// ranges. The new live interval will have an infinite spill weight.
246 LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
247 const std::vector<LiveRange> &LRs) {
248 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
250 // Create a new virtual register for the spill interval.
251 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
253 // Replace the old virtual registers in the machine operands with the shiny
255 for (std::vector<LiveRange>::const_iterator
256 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
257 unsigned Index = getBaseIndex(I->start);
258 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
260 for (; Index != End; Index += InstrSlots::NUM) {
261 // Skip deleted instructions
262 while (Index != End && !getInstructionFromIndex(Index))
263 Index += InstrSlots::NUM;
265 if (Index == End) break;
267 MachineInstr *MI = getInstructionFromIndex(Index);
269 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
270 MachineOperand &MOp = MI->getOperand(J);
271 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg)
277 LiveInterval &NewLI = getOrCreateInterval(NewVReg);
279 // The spill weight is now infinity as it cannot be spilled again
280 NewLI.weight = float(HUGE_VAL);
282 for (std::vector<LiveRange>::const_iterator
283 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
284 DOUT << " Adding live range " << *I << " to new interval\n";
288 DOUT << "Created new live interval " << NewLI << "\n";
292 std::vector<LiveInterval*> LiveIntervals::
293 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
294 // since this is called after the analysis is done we don't know if
295 // LiveVariables is available
296 lv_ = getAnalysisToUpdate<LiveVariables>();
298 std::vector<LiveInterval*> added;
300 assert(li.weight != HUGE_VALF &&
301 "attempt to spill already spilled interval!");
303 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
304 li.print(DOUT, mri_);
307 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
309 for (LiveInterval::Ranges::const_iterator
310 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
311 unsigned index = getBaseIndex(i->start);
312 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
313 for (; index != end; index += InstrSlots::NUM) {
314 // skip deleted instructions
315 while (index != end && !getInstructionFromIndex(index))
316 index += InstrSlots::NUM;
317 if (index == end) break;
319 MachineInstr *MI = getInstructionFromIndex(index);
322 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
323 MachineOperand& mop = MI->getOperand(i);
324 if (mop.isRegister() && mop.getReg() == li.reg) {
325 MachineInstr *fmi = li.remat ? NULL
326 : mri_->foldMemoryOperand(MI, i, slot);
328 // Attempt to fold the memory reference into the instruction. If we
329 // can do this, we don't need to insert spill code.
331 lv_->instructionChanged(MI, fmi);
332 MachineBasicBlock &MBB = *MI->getParent();
333 vrm.virtFolded(li.reg, MI, i, fmi);
335 i2miMap_[index/InstrSlots::NUM] = fmi;
336 mi2iMap_[fmi] = index;
337 MI = MBB.insert(MBB.erase(MI), fmi);
339 // Folding the load/store can completely change the instruction in
340 // unpredictable ways, rescan it from the beginning.
341 goto RestartInstruction;
343 // Create a new virtual register for the spill interval.
344 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
346 // Scan all of the operands of this instruction rewriting operands
347 // to use NewVReg instead of li.reg as appropriate. We do this for
350 // 1. If the instr reads the same spilled vreg multiple times, we
351 // want to reuse the NewVReg.
352 // 2. If the instr is a two-addr instruction, we are required to
353 // keep the src/dst regs pinned.
355 // Keep track of whether we replace a use and/or def so that we can
356 // create the spill interval with the appropriate range.
359 bool HasUse = mop.isUse();
360 bool HasDef = mop.isDef();
361 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
362 if (MI->getOperand(j).isReg() &&
363 MI->getOperand(j).getReg() == li.reg) {
364 MI->getOperand(j).setReg(NewVReg);
365 HasUse |= MI->getOperand(j).isUse();
366 HasDef |= MI->getOperand(j).isDef();
370 // create a new register for this spill
373 vrm.setVirtIsReMaterialized(NewVReg, li.remat);
374 vrm.assignVirt2StackSlot(NewVReg, slot);
375 LiveInterval &nI = getOrCreateInterval(NewVReg);
379 // the spill weight is now infinity as it
380 // cannot be spilled again
381 nI.weight = HUGE_VALF;
384 LiveRange LR(getLoadIndex(index), getUseIndex(index),
385 nI.getNextValue(~0U, 0));
390 LiveRange LR(getDefIndex(index), getStoreIndex(index),
391 nI.getNextValue(~0U, 0));
396 added.push_back(&nI);
398 // update live variables if it is available
400 lv_->addVirtualRegisterKilled(NewVReg, MI);
402 DOUT << "\t\t\t\tadded new interval: ";
403 nI.print(DOUT, mri_);
414 void LiveIntervals::printRegName(unsigned reg) const {
415 if (MRegisterInfo::isPhysicalRegister(reg))
416 cerr << mri_->getName(reg);
418 cerr << "%reg" << reg;
421 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
422 /// two addr elimination.
423 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
424 const TargetInstrInfo *TII) {
425 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
426 MachineOperand &MO1 = MI->getOperand(i);
427 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
428 for (unsigned j = i+1; j < e; ++j) {
429 MachineOperand &MO2 = MI->getOperand(j);
430 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
431 MI->getInstrDescriptor()->
432 getOperandConstraint(j, TOI::TIED_TO) == (int)i)
440 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
441 MachineBasicBlock::iterator mi,
443 LiveInterval &interval) {
444 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
445 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
447 // Virtual registers may be defined multiple times (due to phi
448 // elimination and 2-addr elimination). Much of what we do only has to be
449 // done once for the vreg. We use an empty interval to detect the first
450 // time we see a vreg.
451 if (interval.empty()) {
452 // Remember if the definition can be rematerialized. All load's from fixed
453 // stack slots are re-materializable.
456 (tii_->isReMaterializable(vi.DefInst->getOpcode()) ||
457 (tii_->isLoadFromStackSlot(vi.DefInst, FrameIdx) &&
458 mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx))))
459 interval.remat = vi.DefInst;
461 // Get the Idx of the defining instructions.
462 unsigned defIndex = getDefIndex(MIIdx);
465 unsigned SrcReg, DstReg;
466 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
467 ValNum = interval.getNextValue(~0U, 0);
469 ValNum = interval.getNextValue(defIndex, SrcReg);
471 assert(ValNum == 0 && "First value in interval is not 0?");
472 ValNum = 0; // Clue in the optimizer.
474 // Loop over all of the blocks that the vreg is defined in. There are
475 // two cases we have to handle here. The most common case is a vreg
476 // whose lifetime is contained within a basic block. In this case there
477 // will be a single kill, in MBB, which comes after the definition.
478 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
479 // FIXME: what about dead vars?
481 if (vi.Kills[0] != mi)
482 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
484 killIdx = defIndex+1;
486 // If the kill happens after the definition, we have an intra-block
488 if (killIdx > defIndex) {
489 assert(vi.AliveBlocks.none() &&
490 "Shouldn't be alive across any blocks!");
491 LiveRange LR(defIndex, killIdx, ValNum);
492 interval.addRange(LR);
493 DOUT << " +" << LR << "\n";
498 // The other case we handle is when a virtual register lives to the end
499 // of the defining block, potentially live across some blocks, then is
500 // live into some number of blocks, but gets killed. Start by adding a
501 // range that goes from this definition to the end of the defining block.
502 LiveRange NewLR(defIndex,
503 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
505 DOUT << " +" << NewLR;
506 interval.addRange(NewLR);
508 // Iterate over all of the blocks that the variable is completely
509 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
511 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
512 if (vi.AliveBlocks[i]) {
513 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
515 LiveRange LR(getMBBStartIdx(i),
516 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
518 interval.addRange(LR);
524 // Finally, this virtual register is live from the start of any killing
525 // block to the 'use' slot of the killing instruction.
526 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
527 MachineInstr *Kill = vi.Kills[i];
528 LiveRange LR(getMBBStartIdx(Kill->getParent()),
529 getUseIndex(getInstructionIndex(Kill))+1,
531 interval.addRange(LR);
536 // Can no longer safely assume definition is rematerializable.
537 interval.remat = NULL;
539 // If this is the second time we see a virtual register definition, it
540 // must be due to phi elimination or two addr elimination. If this is
541 // the result of two address elimination, then the vreg is one of the
542 // def-and-use register operand.
543 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
544 // If this is a two-address definition, then we have already processed
545 // the live range. The only problem is that we didn't realize there
546 // are actually two values in the live interval. Because of this we
547 // need to take the LiveRegion that defines this register and split it
549 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
550 unsigned RedefIndex = getDefIndex(MIIdx);
552 // Delete the initial value, which should be short and continuous,
553 // because the 2-addr copy must be in the same MBB as the redef.
554 interval.removeRange(DefIndex, RedefIndex);
556 // Two-address vregs should always only be redefined once. This means
557 // that at this point, there should be exactly one value number in it.
558 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
560 // The new value number (#1) is defined by the instruction we claimed
562 unsigned ValNo = interval.getNextValue(0, 0);
563 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
565 // Value#0 is now defined by the 2-addr instruction.
566 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
568 // Add the new live interval which replaces the range for the input copy.
569 LiveRange LR(DefIndex, RedefIndex, ValNo);
570 DOUT << " replace range with " << LR;
571 interval.addRange(LR);
573 // If this redefinition is dead, we need to add a dummy unit live
574 // range covering the def slot.
575 if (lv_->RegisterDefIsDead(mi, interval.reg))
576 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
579 interval.print(DOUT, mri_);
582 // Otherwise, this must be because of phi elimination. If this is the
583 // first redefinition of the vreg that we have seen, go back and change
584 // the live range in the PHI block to be a different value number.
585 if (interval.containsOneValue()) {
586 assert(vi.Kills.size() == 1 &&
587 "PHI elimination vreg should have one kill, the PHI itself!");
589 // Remove the old range that we now know has an incorrect number.
590 MachineInstr *Killer = vi.Kills[0];
591 unsigned Start = getMBBStartIdx(Killer->getParent());
592 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
593 DOUT << " Removing [" << Start << "," << End << "] from: ";
594 interval.print(DOUT, mri_); DOUT << "\n";
595 interval.removeRange(Start, End);
596 DOUT << " RESULT: "; interval.print(DOUT, mri_);
598 // Replace the interval with one of a NEW value number. Note that this
599 // value number isn't actually defined by an instruction, weird huh? :)
600 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
601 DOUT << " replace range with " << LR;
602 interval.addRange(LR);
603 DOUT << " RESULT: "; interval.print(DOUT, mri_);
606 // In the case of PHI elimination, each variable definition is only
607 // live until the end of the block. We've already taken care of the
608 // rest of the live range.
609 unsigned defIndex = getDefIndex(MIIdx);
612 unsigned SrcReg, DstReg;
613 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
614 ValNum = interval.getNextValue(~0U, 0);
616 ValNum = interval.getNextValue(defIndex, SrcReg);
618 LiveRange LR(defIndex,
619 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
620 interval.addRange(LR);
628 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
629 MachineBasicBlock::iterator mi,
631 LiveInterval &interval,
633 // A physical register cannot be live across basic block, so its
634 // lifetime must end somewhere in its defining basic block.
635 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
637 unsigned baseIndex = MIIdx;
638 unsigned start = getDefIndex(baseIndex);
639 unsigned end = start;
641 // If it is not used after definition, it is considered dead at
642 // the instruction defining it. Hence its interval is:
643 // [defSlot(def), defSlot(def)+1)
644 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
646 end = getDefIndex(start) + 1;
650 // If it is not dead on definition, it must be killed by a
651 // subsequent instruction. Hence its interval is:
652 // [defSlot(def), useSlot(kill)+1)
653 while (++mi != MBB->end()) {
654 baseIndex += InstrSlots::NUM;
655 if (lv_->KillsRegister(mi, interval.reg)) {
657 end = getUseIndex(baseIndex) + 1;
659 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
660 // Another instruction redefines the register before it is ever read.
661 // Then the register is essentially dead at the instruction that defines
662 // it. Hence its interval is:
663 // [defSlot(def), defSlot(def)+1)
665 end = getDefIndex(start) + 1;
670 // The only case we should have a dead physreg here without a killing or
671 // instruction where we know it's dead is if it is live-in to the function
673 assert(!SrcReg && "physreg was not killed in defining block!");
674 end = getDefIndex(start) + 1; // It's dead.
677 assert(start < end && "did not find end of interval?");
679 // Already exists? Extend old live interval.
680 LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
681 unsigned Id = (OldLR != interval.end())
683 : interval.getNextValue(SrcReg != 0 ? start : ~0U, SrcReg);
684 LiveRange LR(start, end, Id);
685 interval.addRange(LR);
686 DOUT << " +" << LR << '\n';
689 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
690 MachineBasicBlock::iterator MI,
693 if (MRegisterInfo::isVirtualRegister(reg))
694 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
695 else if (allocatableRegs_[reg]) {
696 unsigned SrcReg, DstReg;
697 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
699 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
700 // Def of a register also defines its sub-registers.
701 for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
702 // Avoid processing some defs more than once.
703 if (!MI->findRegisterDefOperand(*AS))
704 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
708 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
710 LiveInterval &interval, bool isAlias) {
711 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
713 // Look for kills, if it reaches a def before it's killed, then it shouldn't
714 // be considered a livein.
715 MachineBasicBlock::iterator mi = MBB->begin();
716 unsigned baseIndex = MIIdx;
717 unsigned start = baseIndex;
718 unsigned end = start;
719 while (mi != MBB->end()) {
720 if (lv_->KillsRegister(mi, interval.reg)) {
722 end = getUseIndex(baseIndex) + 1;
724 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
725 // Another instruction redefines the register before it is ever read.
726 // Then the register is essentially dead at the instruction that defines
727 // it. Hence its interval is:
728 // [defSlot(def), defSlot(def)+1)
730 end = getDefIndex(start) + 1;
734 baseIndex += InstrSlots::NUM;
739 // Alias of a live-in register might not be used at all.
740 if (isAlias && end == 0) {
742 end = getDefIndex(start) + 1;
745 assert(start < end && "did not find end of interval?");
747 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
748 DOUT << " +" << LR << '\n';
749 interval.addRange(LR);
752 /// computeIntervals - computes the live intervals for virtual
753 /// registers. for some ordering of the machine instructions [1,N] a
754 /// live interval is an interval [i, j) where 1 <= i <= j < N for
755 /// which a variable is live
756 void LiveIntervals::computeIntervals() {
757 DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
758 << "********** Function: "
759 << ((Value*)mf_->getFunction())->getName() << '\n';
760 // Track the index of the current machine instr.
761 unsigned MIIndex = 0;
762 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
764 MachineBasicBlock *MBB = MBBI;
765 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
767 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
769 if (MBB->livein_begin() != MBB->livein_end()) {
770 // Create intervals for live-ins to this BB first.
771 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
772 LE = MBB->livein_end(); LI != LE; ++LI) {
773 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
774 // Multiple live-ins can alias the same register.
775 for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
776 if (!hasInterval(*AS))
777 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true);
781 for (; MI != miEnd; ++MI) {
782 DOUT << MIIndex << "\t" << *MI;
785 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
786 MachineOperand &MO = MI->getOperand(i);
787 // handle register defs - build intervals
788 if (MO.isRegister() && MO.getReg() && MO.isDef())
789 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
792 MIIndex += InstrSlots::NUM;
797 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
798 /// being the source and IntB being the dest, thus this defines a value number
799 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
800 /// see if we can merge these two pieces of B into a single value number,
801 /// eliminating a copy. For example:
805 /// B1 = A3 <- this copy
807 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
808 /// value number to be replaced with B0 (which simplifies the B liveinterval).
810 /// This returns true if an interval was modified.
812 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
813 MachineInstr *CopyMI) {
814 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
816 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
817 // the example above.
818 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
819 unsigned BValNo = BLR->ValId;
821 // Get the location that B is defined at. Two options: either this value has
822 // an unknown definition point or it is defined at CopyIdx. If unknown, we
824 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
825 if (BValNoDefIdx == ~0U) return false;
826 assert(BValNoDefIdx == CopyIdx &&
827 "Copy doesn't define the value?");
829 // AValNo is the value number in A that defines the copy, A0 in the example.
830 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
831 unsigned AValNo = AValLR->ValId;
833 // If AValNo is defined as a copy from IntB, we can potentially process this.
835 // Get the instruction that defines this value number.
836 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
837 if (!SrcReg) return false; // Not defined by a copy.
839 // If the value number is not defined by a copy instruction, ignore it.
841 // If the source register comes from an interval other than IntB, we can't
843 if (rep(SrcReg) != IntB.reg) return false;
845 // Get the LiveRange in IntB that this value number starts with.
846 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
847 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
849 // Make sure that the end of the live range is inside the same block as
851 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
853 ValLREndInst->getParent() != CopyMI->getParent()) return false;
855 // Okay, we now know that ValLR ends in the same block that the CopyMI
856 // live-range starts. If there are no intervening live ranges between them in
857 // IntB, we can merge them.
858 if (ValLR+1 != BLR) return false;
860 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
862 // We are about to delete CopyMI, so need to remove it as the 'instruction
863 // that defines this value #'.
864 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
866 // Okay, we can merge them. We need to insert a new liverange:
867 // [ValLR.end, BLR.begin) of either value number, then we merge the
868 // two value numbers.
869 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
870 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
872 // If the IntB live range is assigned to a physical register, and if that
873 // physreg has aliases,
874 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
875 // Update the liveintervals of sub-registers.
876 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
877 LiveInterval &AliasLI = getInterval(*AS);
878 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
879 AliasLI.getNextValue(~0U, 0)));
883 // Okay, merge "B1" into the same value number as "B0".
884 if (BValNo != ValLR->ValId)
885 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
886 DOUT << " result = "; IntB.print(DOUT, mri_);
889 // If the source instruction was killing the source register before the
890 // merge, unset the isKill marker given the live range has been extended.
891 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
893 ValLREndInst->getOperand(UIdx).unsetIsKill();
895 // Finally, delete the copy instruction.
896 RemoveMachineInstrFromMaps(CopyMI);
897 CopyMI->eraseFromParent();
903 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
904 /// which are the src/dst of the copy instruction CopyMI. This returns true
905 /// if the copy was successfully coallesced away, or if it is never possible
906 /// to coallesce this copy, due to register constraints. It returns
907 /// false if it is not currently possible to coallesce this interval, but
908 /// it may be possible if other things get coallesced.
909 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
910 unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
911 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
913 // Get representative registers.
914 unsigned repSrcReg = rep(SrcReg);
915 unsigned repDstReg = rep(DstReg);
917 // If they are already joined we continue.
918 if (repSrcReg == repDstReg) {
919 DOUT << "\tCopy already coallesced.\n";
920 return true; // Not coallescable.
923 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
924 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
925 if (PhysOnly && !SrcIsPhys && !DstIsPhys)
926 // Only joining physical registers with virtual registers in this round.
929 // If they are both physical registers, we cannot join them.
930 if (SrcIsPhys && DstIsPhys) {
931 DOUT << "\tCan not coallesce physregs.\n";
932 return true; // Not coallescable.
935 // We only join virtual registers with allocatable physical registers.
936 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
937 DOUT << "\tSrc reg is unallocatable physreg.\n";
938 return true; // Not coallescable.
940 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
941 DOUT << "\tDst reg is unallocatable physreg.\n";
942 return true; // Not coallescable.
945 // If they are not of the same register class, we cannot join them.
946 if (differingRegisterClasses(repSrcReg, repDstReg)) {
947 DOUT << "\tSrc/Dest are different register classes.\n";
948 return true; // Not coallescable.
951 LiveInterval &SrcInt = getInterval(repSrcReg);
952 LiveInterval &DstInt = getInterval(repDstReg);
953 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
954 "Register mapping is horribly broken!");
956 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
957 DOUT << " and "; DstInt.print(DOUT, mri_);
960 // Check if it is necessary to propagate "isDead" property before intervals
962 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
963 bool isDead = mopd->isDead();
964 bool isShorten = false;
965 unsigned SrcStart = 0, RemoveStart = 0;
966 unsigned SrcEnd = 0, RemoveEnd = 0;
968 unsigned CopyIdx = getInstructionIndex(CopyMI);
969 LiveInterval::iterator SrcLR =
970 SrcInt.FindLiveRangeContaining(getUseIndex(CopyIdx));
971 RemoveStart = SrcStart = SrcLR->start;
972 RemoveEnd = SrcEnd = SrcLR->end;
973 // The instruction which defines the src is only truly dead if there are
974 // no intermediate uses and there isn't a use beyond the copy.
975 // FIXME: find the last use, mark is kill and shorten the live range.
976 if (SrcEnd > getDefIndex(CopyIdx)) {
980 MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
982 // Shorten the liveinterval to the end of last use.
986 RemoveStart = getDefIndex(getInstructionIndex(LastUse));
989 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
991 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
993 // A dead def should have a single cycle interval.
1000 // We need to be careful about coalescing a source physical register with a
1001 // virtual register. Once the coalescing is done, it cannot be broken and
1002 // these are not spillable! If the destination interval uses are far away,
1003 // think twice about coalescing them!
1004 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys)) {
1005 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1006 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
1007 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
1008 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
1009 unsigned Threshold = allocatableRCRegs_[RC].count();
1011 // If the virtual register live interval is long has it has low use desity,
1012 // do not join them, instead mark the physical register as its allocation
1014 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
1015 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
1016 if (Length > Threshold &&
1017 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
1018 JoinVInt.preference = JoinPReg;
1020 DOUT << "\tMay tie down a physical register, abort!\n";
1025 // Okay, attempt to join these two intervals. On failure, this returns false.
1026 // Otherwise, if one of the intervals being joined is a physreg, this method
1027 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1028 // been modified, so we can use this information below to update aliases.
1029 if (JoinIntervals(DstInt, SrcInt)) {
1031 // Result of the copy is dead. Propagate this property.
1032 if (SrcStart == 0) {
1033 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
1034 "Live-in must be a physical register!");
1035 // Live-in to the function but dead. Remove it from entry live-in set.
1036 // JoinIntervals may end up swapping the two intervals.
1037 mf_->begin()->removeLiveIn(repSrcReg);
1039 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
1041 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
1048 if (isShorten || isDead) {
1049 // Shorten the live interval.
1050 LiveInterval &LiveInInt = (repSrcReg == DstInt.reg) ? DstInt : SrcInt;
1051 LiveInInt.removeRange(RemoveStart, RemoveEnd);
1054 // Coallescing failed.
1056 // If we can eliminate the copy without merging the live ranges, do so now.
1057 if (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI))
1060 // Otherwise, we are unable to join the intervals.
1061 DOUT << "Interference!\n";
1065 bool Swapped = repSrcReg == DstInt.reg;
1067 std::swap(repSrcReg, repDstReg);
1068 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
1069 "LiveInterval::join didn't work right!");
1071 // If we're about to merge live ranges into a physical register live range,
1072 // we have to update any aliased register's live ranges to indicate that they
1073 // have clobbered values for this range.
1074 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
1075 // Unset unnecessary kills.
1076 for (LiveInterval::Ranges::const_iterator I = SrcInt.begin(),
1077 E = SrcInt.end(); I != E; ++I)
1078 unsetRegisterKills(I->start, I->end, repDstReg);
1080 // Update the liveintervals of sub-registers.
1081 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
1082 getInterval(*AS).MergeInClobberRanges(SrcInt);
1084 // Merge use info if the destination is a virtual register.
1085 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
1086 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
1087 dVI.NumUses += sVI.NumUses;
1090 DOUT << "\n\t\tJoined. Result = "; DstInt.print(DOUT, mri_);
1093 // Remember these liveintervals have been joined.
1094 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
1095 if (MRegisterInfo::isVirtualRegister(repDstReg))
1096 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
1098 // If the intervals were swapped by Join, swap them back so that the register
1099 // mapping (in the r2i map) is correct.
1100 if (Swapped) SrcInt.swap(DstInt);
1101 removeInterval(repSrcReg);
1102 r2rMap_[repSrcReg] = repDstReg;
1104 // Finally, delete the copy instruction.
1105 RemoveMachineInstrFromMaps(CopyMI);
1106 CopyMI->eraseFromParent();
1112 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1113 /// compute what the resultant value numbers for each value in the input two
1114 /// ranges will be. This is complicated by copies between the two which can
1115 /// and will commonly cause multiple value numbers to be merged into one.
1117 /// VN is the value number that we're trying to resolve. InstDefiningValue
1118 /// keeps track of the new InstDefiningValue assignment for the result
1119 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1120 /// whether a value in this or other is a copy from the opposite set.
1121 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1122 /// already been assigned.
1124 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1125 /// contains the value number the copy is from.
1127 static unsigned ComputeUltimateVN(unsigned VN,
1128 SmallVector<std::pair<unsigned,
1129 unsigned>, 16> &ValueNumberInfo,
1130 SmallVector<int, 16> &ThisFromOther,
1131 SmallVector<int, 16> &OtherFromThis,
1132 SmallVector<int, 16> &ThisValNoAssignments,
1133 SmallVector<int, 16> &OtherValNoAssignments,
1134 LiveInterval &ThisLI, LiveInterval &OtherLI) {
1135 // If the VN has already been computed, just return it.
1136 if (ThisValNoAssignments[VN] >= 0)
1137 return ThisValNoAssignments[VN];
1138 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1140 // If this val is not a copy from the other val, then it must be a new value
1141 // number in the destination.
1142 int OtherValNo = ThisFromOther[VN];
1143 if (OtherValNo == -1) {
1144 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
1145 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
1148 // Otherwise, this *is* a copy from the RHS. If the other side has already
1149 // been computed, return it.
1150 if (OtherValNoAssignments[OtherValNo] >= 0)
1151 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
1153 // Mark this value number as currently being computed, then ask what the
1154 // ultimate value # of the other value is.
1155 ThisValNoAssignments[VN] = -2;
1156 unsigned UltimateVN =
1157 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
1158 OtherFromThis, ThisFromOther,
1159 OtherValNoAssignments, ThisValNoAssignments,
1161 return ThisValNoAssignments[VN] = UltimateVN;
1164 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
1165 return std::find(V.begin(), V.end(), Val) != V.end();
1168 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1169 /// caller of this method must guarantee that the RHS only contains a single
1170 /// value number and that the RHS is not defined by a copy from this
1171 /// interval. This returns false if the intervals are not joinable, or it
1172 /// joins them and returns true.
1173 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
1174 assert(RHS.containsOneValue());
1176 // Some number (potentially more than one) value numbers in the current
1177 // interval may be defined as copies from the RHS. Scan the overlapping
1178 // portions of the LHS and RHS, keeping track of this and looking for
1179 // overlapping live ranges that are NOT defined as copies. If these exist, we
1180 // cannot coallesce.
1182 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1183 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1185 if (LHSIt->start < RHSIt->start) {
1186 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1187 if (LHSIt != LHS.begin()) --LHSIt;
1188 } else if (RHSIt->start < LHSIt->start) {
1189 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1190 if (RHSIt != RHS.begin()) --RHSIt;
1193 SmallVector<unsigned, 8> EliminatedLHSVals;
1196 // Determine if these live intervals overlap.
1197 bool Overlaps = false;
1198 if (LHSIt->start <= RHSIt->start)
1199 Overlaps = LHSIt->end > RHSIt->start;
1201 Overlaps = RHSIt->end > LHSIt->start;
1203 // If the live intervals overlap, there are two interesting cases: if the
1204 // LHS interval is defined by a copy from the RHS, it's ok and we record
1205 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1206 // coallesce these live ranges and we bail out.
1208 // If we haven't already recorded that this value # is safe, check it.
1209 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
1210 // Copy from the RHS?
1211 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
1212 if (rep(SrcReg) != RHS.reg)
1213 return false; // Nope, bail out.
1215 EliminatedLHSVals.push_back(LHSIt->ValId);
1218 // We know this entire LHS live range is okay, so skip it now.
1219 if (++LHSIt == LHSEnd) break;
1223 if (LHSIt->end < RHSIt->end) {
1224 if (++LHSIt == LHSEnd) break;
1226 // One interesting case to check here. It's possible that we have
1227 // something like "X3 = Y" which defines a new value number in the LHS,
1228 // and is the last use of this liverange of the RHS. In this case, we
1229 // want to notice this copy (so that it gets coallesced away) even though
1230 // the live ranges don't actually overlap.
1231 if (LHSIt->start == RHSIt->end) {
1232 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
1233 // We already know that this value number is going to be merged in
1234 // if coallescing succeeds. Just skip the liverange.
1235 if (++LHSIt == LHSEnd) break;
1237 // Otherwise, if this is a copy from the RHS, mark it as being merged
1239 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
1240 EliminatedLHSVals.push_back(LHSIt->ValId);
1242 // We know this entire LHS live range is okay, so skip it now.
1243 if (++LHSIt == LHSEnd) break;
1248 if (++RHSIt == RHSEnd) break;
1252 // If we got here, we know that the coallescing will be successful and that
1253 // the value numbers in EliminatedLHSVals will all be merged together. Since
1254 // the most common case is that EliminatedLHSVals has a single number, we
1255 // optimize for it: if there is more than one value, we merge them all into
1256 // the lowest numbered one, then handle the interval as if we were merging
1257 // with one value number.
1259 if (EliminatedLHSVals.size() > 1) {
1260 // Loop through all the equal value numbers merging them into the smallest
1262 unsigned Smallest = EliminatedLHSVals[0];
1263 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1264 if (EliminatedLHSVals[i] < Smallest) {
1265 // Merge the current notion of the smallest into the smaller one.
1266 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1267 Smallest = EliminatedLHSVals[i];
1269 // Merge into the smallest.
1270 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1273 LHSValNo = Smallest;
1275 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1276 LHSValNo = EliminatedLHSVals[0];
1279 // Okay, now that there is a single LHS value number that we're merging the
1280 // RHS into, update the value number info for the LHS to indicate that the
1281 // value number is defined where the RHS value number was.
1282 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1284 // Okay, the final step is to loop over the RHS live intervals, adding them to
1286 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1287 LHS.weight += RHS.weight;
1288 if (RHS.preference && !LHS.preference)
1289 LHS.preference = RHS.preference;
1294 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1295 /// returns false. Otherwise, if one of the intervals being joined is a
1296 /// physreg, this method always canonicalizes LHS to be it. The output
1297 /// "RHS" will not have been modified, so we can use this information
1298 /// below to update aliases.
1299 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1300 // Compute the final value assignment, assuming that the live ranges can be
1302 SmallVector<int, 16> LHSValNoAssignments;
1303 SmallVector<int, 16> RHSValNoAssignments;
1304 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1306 // If a live interval is a physical register, conservatively check if any
1307 // of its sub-registers is overlapping the live interval of the virtual
1308 // register. If so, do not coalesce.
1309 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
1310 *mri_->getSubRegisters(LHS.reg)) {
1311 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
1312 if (hasInterval(*SR) && RHS.overlaps(getInterval(*SR))) {
1313 DOUT << "Interfere with sub-register ";
1314 DEBUG(getInterval(*SR).print(DOUT, mri_));
1317 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
1318 *mri_->getSubRegisters(RHS.reg)) {
1319 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
1320 if (hasInterval(*SR) && LHS.overlaps(getInterval(*SR))) {
1321 DOUT << "Interfere with sub-register ";
1322 DEBUG(getInterval(*SR).print(DOUT, mri_));
1327 // Compute ultimate value numbers for the LHS and RHS values.
1328 if (RHS.containsOneValue()) {
1329 // Copies from a liveinterval with a single value are simple to handle and
1330 // very common, handle the special case here. This is important, because
1331 // often RHS is small and LHS is large (e.g. a physreg).
1333 // Find out if the RHS is defined as a copy from some value in the LHS.
1335 std::pair<unsigned,unsigned> RHSValNoInfo;
1336 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1337 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1338 // If RHS is not defined as a copy from the LHS, we can use simpler and
1339 // faster checks to see if the live ranges are coallescable. This joiner
1340 // can't swap the LHS/RHS intervals though.
1341 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1342 return SimpleJoin(LHS, RHS);
1344 RHSValNoInfo = RHS.getValNumInfo(0);
1347 // It was defined as a copy from the LHS, find out what value # it is.
1348 unsigned ValInst = RHS.getInstForValNum(0);
1349 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1350 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1353 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1354 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1355 ValueNumberInfo.resize(LHS.getNumValNums());
1357 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1358 // should now get updated.
1359 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1360 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1361 if (rep(LHSSrcReg) != RHS.reg) {
1362 // If this is not a copy from the RHS, its value number will be
1363 // unmodified by the coallescing.
1364 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1365 LHSValNoAssignments[VN] = VN;
1366 } else if (RHSValID == -1) {
1367 // Otherwise, it is a copy from the RHS, and we don't already have a
1368 // value# for it. Keep the current value number, but remember it.
1369 LHSValNoAssignments[VN] = RHSValID = VN;
1370 ValueNumberInfo[VN] = RHSValNoInfo;
1372 // Otherwise, use the specified value #.
1373 LHSValNoAssignments[VN] = RHSValID;
1374 if (VN != (unsigned)RHSValID)
1375 ValueNumberInfo[VN].first = ~1U;
1377 ValueNumberInfo[VN] = RHSValNoInfo;
1380 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1381 LHSValNoAssignments[VN] = VN;
1385 assert(RHSValID != -1 && "Didn't find value #?");
1386 RHSValNoAssignments[0] = RHSValID;
1389 // Loop over the value numbers of the LHS, seeing if any are defined from
1391 SmallVector<int, 16> LHSValsDefinedFromRHS;
1392 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1393 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1394 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1395 if (ValSrcReg == 0) // Src not defined by a copy?
1398 // DstReg is known to be a register in the LHS interval. If the src is
1399 // from the RHS interval, we can use its value #.
1400 if (rep(ValSrcReg) != RHS.reg)
1403 // Figure out the value # from the RHS.
1404 unsigned ValInst = LHS.getInstForValNum(VN);
1405 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1408 // Loop over the value numbers of the RHS, seeing if any are defined from
1410 SmallVector<int, 16> RHSValsDefinedFromLHS;
1411 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1412 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1413 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1414 if (ValSrcReg == 0) // Src not defined by a copy?
1417 // DstReg is known to be a register in the RHS interval. If the src is
1418 // from the LHS interval, we can use its value #.
1419 if (rep(ValSrcReg) != LHS.reg)
1422 // Figure out the value # from the LHS.
1423 unsigned ValInst = RHS.getInstForValNum(VN);
1424 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1427 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1428 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1429 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1431 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1432 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1434 ComputeUltimateVN(VN, ValueNumberInfo,
1435 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1436 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1438 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1439 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1441 // If this value number isn't a copy from the LHS, it's a new number.
1442 if (RHSValsDefinedFromLHS[VN] == -1) {
1443 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1444 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1448 ComputeUltimateVN(VN, ValueNumberInfo,
1449 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1450 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1454 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1455 // interval lists to see if these intervals are coallescable.
1456 LiveInterval::const_iterator I = LHS.begin();
1457 LiveInterval::const_iterator IE = LHS.end();
1458 LiveInterval::const_iterator J = RHS.begin();
1459 LiveInterval::const_iterator JE = RHS.end();
1461 // Skip ahead until the first place of potential sharing.
1462 if (I->start < J->start) {
1463 I = std::upper_bound(I, IE, J->start);
1464 if (I != LHS.begin()) --I;
1465 } else if (J->start < I->start) {
1466 J = std::upper_bound(J, JE, I->start);
1467 if (J != RHS.begin()) --J;
1471 // Determine if these two live ranges overlap.
1473 if (I->start < J->start) {
1474 Overlaps = I->end > J->start;
1476 Overlaps = J->end > I->start;
1479 // If so, check value # info to determine if they are really different.
1481 // If the live range overlap will map to the same value number in the
1482 // result liverange, we can still coallesce them. If not, we can't.
1483 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1487 if (I->end < J->end) {
1496 // If we get here, we know that we can coallesce the live ranges. Ask the
1497 // intervals to coallesce themselves now.
1498 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1505 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1506 // depth of the basic block (the unsigned), and then on the MBB number.
1507 struct DepthMBBCompare {
1508 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1509 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1510 if (LHS.first > RHS.first) return true; // Deeper loops first
1511 return LHS.first == RHS.first &&
1512 LHS.second->getNumber() < RHS.second->getNumber();
1518 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1519 std::vector<CopyRec> *TryAgain, bool PhysOnly) {
1520 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1522 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1524 MachineInstr *Inst = MII++;
1526 // If this isn't a copy, we can't join intervals.
1527 unsigned SrcReg, DstReg;
1528 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1530 if (TryAgain && !JoinCopy(Inst, SrcReg, DstReg, PhysOnly))
1531 TryAgain->push_back(getCopyRec(Inst, SrcReg, DstReg));
1536 void LiveIntervals::joinIntervals() {
1537 DOUT << "********** JOINING INTERVALS ***********\n";
1539 JoinedLIs.resize(getNumIntervals());
1542 std::vector<CopyRec> TryAgainList;
1543 const LoopInfo &LI = getAnalysis<LoopInfo>();
1544 if (LI.begin() == LI.end()) {
1545 // If there are no loops in the function, join intervals in function order.
1546 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1548 CopyCoallesceInMBB(I, &TryAgainList);
1550 // Otherwise, join intervals in inner loops before other intervals.
1551 // Unfortunately we can't just iterate over loop hierarchy here because
1552 // there may be more MBB's than BB's. Collect MBB's for sorting.
1554 // Join intervals in the function prolog first. We want to join physical
1555 // registers with virtual registers before the intervals got too long.
1556 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1557 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
1558 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1560 // Sort by loop depth.
1561 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1563 // Finally, join intervals in loop nest order.
1564 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1565 CopyCoallesceInMBB(MBBs[i].second, NULL, true);
1566 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1567 CopyCoallesceInMBB(MBBs[i].second, &TryAgainList, false);
1570 // Joining intervals can allow other intervals to be joined. Iteratively join
1571 // until we make no progress.
1572 bool ProgressMade = true;
1573 while (ProgressMade) {
1574 ProgressMade = false;
1576 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1577 CopyRec &TheCopy = TryAgainList[i];
1579 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1580 TheCopy.MI = 0; // Mark this one as done.
1581 ProgressMade = true;
1586 // Some live range has been lengthened due to colaescing, eliminate the
1587 // unnecessary kills.
1588 int RegNum = JoinedLIs.find_first();
1589 while (RegNum != -1) {
1590 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
1591 unsigned repReg = rep(Reg);
1592 LiveInterval &LI = getInterval(repReg);
1593 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
1594 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
1595 MachineInstr *Kill = svi.Kills[i];
1596 // Suppose vr1 = op vr2, x
1597 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
1598 // unless it is a two-address operand.
1599 if (isRemoved(Kill) || hasRegisterDef(Kill, repReg))
1601 if (LI.liveAt(getInstructionIndex(Kill) + InstrSlots::NUM))
1602 unsetRegisterKill(Kill, repReg);
1604 RegNum = JoinedLIs.find_next(RegNum);
1607 DOUT << "*** Register mapping ***\n";
1608 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1610 DOUT << " reg " << i << " -> ";
1611 DEBUG(printRegName(r2rMap_[i]));
1616 /// Return true if the two specified registers belong to different register
1617 /// classes. The registers may be either phys or virt regs.
1618 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1619 unsigned RegB) const {
1621 // Get the register classes for the first reg.
1622 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1623 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1624 "Shouldn't consider two physregs!");
1625 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1628 // Compare against the regclass for the second reg.
1629 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1630 if (MRegisterInfo::isVirtualRegister(RegB))
1631 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1633 return !RegClass->contains(RegB);
1636 /// lastRegisterUse - Returns the last use of the specific register between
1637 /// cycles Start and End. It also returns the use operand by reference. It
1638 /// returns NULL if there are no uses.
1640 LiveIntervals::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
1641 MachineOperand *&MOU) {
1642 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1645 // Skip deleted instructions
1646 MachineInstr *MI = getInstructionFromIndex(e);
1647 while ((e - InstrSlots::NUM) >= s && !MI) {
1648 e -= InstrSlots::NUM;
1649 MI = getInstructionFromIndex(e);
1651 if (e < s || MI == NULL)
1654 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1655 MachineOperand &MO = MI->getOperand(i);
1656 if (MO.isReg() && MO.isUse() && MO.getReg() &&
1657 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1663 e -= InstrSlots::NUM;
1670 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1671 /// register. It returns NULL if the def is not found.
1672 MachineOperand *LiveIntervals::findDefOperand(MachineInstr *MI, unsigned Reg) {
1673 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1674 MachineOperand &MO = MI->getOperand(i);
1675 if (MO.isReg() && MO.isDef() &&
1676 mri_->regsOverlap(rep(MO.getReg()), Reg))
1682 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1683 /// of the specific instruction.
1684 void LiveIntervals::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1685 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1686 MachineOperand &MO = MI->getOperand(i);
1687 if (MO.isReg() && MO.isUse() && MO.isKill() && MO.getReg() &&
1688 mri_->regsOverlap(rep(MO.getReg()), Reg))
1693 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1694 /// between cycles Start and End.
1695 void LiveIntervals::unsetRegisterKills(unsigned Start, unsigned End,
1697 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1700 // Skip deleted instructions
1701 MachineInstr *MI = getInstructionFromIndex(e);
1702 while ((e - InstrSlots::NUM) >= s && !MI) {
1703 e -= InstrSlots::NUM;
1704 MI = getInstructionFromIndex(e);
1706 if (e < s || MI == NULL)
1709 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1710 MachineOperand &MO = MI->getOperand(i);
1711 if (MO.isReg() && MO.isUse() && MO.isKill() && MO.getReg() &&
1712 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1717 e -= InstrSlots::NUM;
1721 /// hasRegisterDef - True if the instruction defines the specific register.
1723 bool LiveIntervals::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1724 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1725 MachineOperand &MO = MI->getOperand(i);
1726 if (MO.isReg() && MO.isDef() &&
1727 mri_->regsOverlap(rep(MO.getReg()), Reg))
1733 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1734 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1736 return LiveInterval(reg, Weight);