1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "LiveRangeCalc.h"
42 // Switch to the new experimental algorithm for computing live intervals.
44 NewLiveIntervals("new-live-intervals", cl::Hidden,
45 cl::desc("Use new algorithm forcomputing live intervals"));
47 char LiveIntervals::ID = 0;
48 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
50 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
53 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
54 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
55 "Live Interval Analysis", false, false)
57 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<AliasAnalysis>();
60 AU.addPreserved<AliasAnalysis>();
61 AU.addRequired<LiveVariables>();
62 AU.addPreserved<LiveVariables>();
63 AU.addPreservedID(MachineLoopInfoID);
64 AU.addRequiredTransitiveID(MachineDominatorsID);
65 AU.addPreservedID(MachineDominatorsID);
66 AU.addPreserved<SlotIndexes>();
67 AU.addRequiredTransitive<SlotIndexes>();
68 MachineFunctionPass::getAnalysisUsage(AU);
71 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
72 DomTree(0), LRCalc(0) {
73 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
76 LiveIntervals::~LiveIntervals() {
80 void LiveIntervals::releaseMemory() {
81 // Free the live intervals themselves.
82 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
83 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
84 VirtRegIntervals.clear();
87 RegMaskBlocks.clear();
89 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
90 delete RegUnitIntervals[i];
91 RegUnitIntervals.clear();
93 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
94 VNInfoAllocator.Reset();
97 /// runOnMachineFunction - Register allocate the whole function
99 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
101 MRI = &MF->getRegInfo();
102 TM = &fn.getTarget();
103 TRI = TM->getRegisterInfo();
104 TII = TM->getInstrInfo();
105 AA = &getAnalysis<AliasAnalysis>();
106 LV = &getAnalysis<LiveVariables>();
107 Indexes = &getAnalysis<SlotIndexes>();
108 DomTree = &getAnalysis<MachineDominatorTree>();
110 LRCalc = new LiveRangeCalc();
111 AllocatableRegs = TRI->getAllocatableSet(fn);
112 ReservedRegs = TRI->getReservedRegs(fn);
114 // Allocate space for all virtual registers.
115 VirtRegIntervals.resize(MRI->getNumVirtRegs());
117 if (NewLiveIntervals) {
118 // This is the new way of computing live intervals.
119 // It is independent of LiveVariables, and it can run at any time.
120 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
121 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
122 if (MRI->reg_nodbg_empty(Reg))
124 LiveInterval *LI = createInterval(Reg);
125 VirtRegIntervals[Reg] = LI;
126 computeVirtRegInterval(LI);
129 // This is the old way of computing live intervals.
130 // It depends on LiveVariables.
133 computeLiveInRegUnits();
139 /// print - Implement the dump method.
140 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
141 OS << "********** INTERVALS **********\n";
143 // Dump the regunits.
144 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
145 if (LiveInterval *LI = RegUnitIntervals[i])
146 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
148 // Dump the virtregs.
149 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
150 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
151 if (hasInterval(Reg))
152 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
158 void LiveIntervals::printInstrs(raw_ostream &OS) const {
159 OS << "********** MACHINEINSTRS **********\n";
160 MF->print(OS, Indexes);
163 void LiveIntervals::dumpInstrs() const {
168 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
169 unsigned Reg = MI.getOperand(MOIdx).getReg();
170 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
171 const MachineOperand &MO = MI.getOperand(i);
174 if (MO.getReg() == Reg && MO.isDef()) {
175 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
176 MI.getOperand(MOIdx).getSubReg() &&
177 (MO.getSubReg() || MO.isImplicit()));
184 /// isPartialRedef - Return true if the specified def at the specific index is
185 /// partially re-defining the specified live interval. A common case of this is
186 /// a definition of the sub-register.
187 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
188 LiveInterval &interval) {
189 if (!MO.getSubReg() || MO.isEarlyClobber())
192 SlotIndex RedefIndex = MIIdx.getRegSlot();
193 const LiveRange *OldLR =
194 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
195 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
197 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
202 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
203 MachineBasicBlock::iterator mi,
207 LiveInterval &interval) {
208 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
210 // Virtual registers may be defined multiple times (due to phi
211 // elimination and 2-addr elimination). Much of what we do only has to be
212 // done once for the vreg. We use an empty interval to detect the first
213 // time we see a vreg.
214 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
215 if (interval.empty()) {
216 // Get the Idx of the defining instructions.
217 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
219 // Make sure the first definition is not a partial redefinition.
220 assert(!MO.readsReg() && "First def cannot also read virtual register "
221 "missing <undef> flag?");
223 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
224 assert(ValNo->id == 0 && "First value in interval is not 0?");
226 // Loop over all of the blocks that the vreg is defined in. There are
227 // two cases we have to handle here. The most common case is a vreg
228 // whose lifetime is contained within a basic block. In this case there
229 // will be a single kill, in MBB, which comes after the definition.
230 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
231 // FIXME: what about dead vars?
233 if (vi.Kills[0] != mi)
234 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
236 killIdx = defIndex.getDeadSlot();
238 // If the kill happens after the definition, we have an intra-block
240 if (killIdx > defIndex) {
241 assert(vi.AliveBlocks.empty() &&
242 "Shouldn't be alive across any blocks!");
243 LiveRange LR(defIndex, killIdx, ValNo);
244 interval.addRange(LR);
245 DEBUG(dbgs() << " +" << LR << "\n");
250 // The other case we handle is when a virtual register lives to the end
251 // of the defining block, potentially live across some blocks, then is
252 // live into some number of blocks, but gets killed. Start by adding a
253 // range that goes from this definition to the end of the defining block.
254 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
255 DEBUG(dbgs() << " +" << NewLR);
256 interval.addRange(NewLR);
258 bool PHIJoin = LV->isPHIJoin(interval.reg);
261 // A phi join register is killed at the end of the MBB and revived as a
262 // new valno in the killing blocks.
263 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
264 DEBUG(dbgs() << " phi-join");
265 ValNo->setHasPHIKill(true);
267 // Iterate over all of the blocks that the variable is completely
268 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
270 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
271 E = vi.AliveBlocks.end(); I != E; ++I) {
272 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
273 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
275 interval.addRange(LR);
276 DEBUG(dbgs() << " +" << LR);
280 // Finally, this virtual register is live from the start of any killing
281 // block to the 'use' slot of the killing instruction.
282 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
283 MachineInstr *Kill = vi.Kills[i];
284 SlotIndex Start = getMBBStartIdx(Kill->getParent());
285 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
287 // Create interval with one of a NEW value number. Note that this value
288 // number isn't actually defined by an instruction, weird huh? :)
290 assert(getInstructionFromIndex(Start) == 0 &&
291 "PHI def index points at actual instruction.");
292 ValNo = interval.getNextValue(Start, VNInfoAllocator);
293 ValNo->setIsPHIDef(true);
295 LiveRange LR(Start, killIdx, ValNo);
296 interval.addRange(LR);
297 DEBUG(dbgs() << " +" << LR);
301 if (MultipleDefsBySameMI(*mi, MOIdx))
302 // Multiple defs of the same virtual register by the same instruction.
303 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
304 // This is likely due to elimination of REG_SEQUENCE instructions. Return
305 // here since there is nothing to do.
308 // If this is the second time we see a virtual register definition, it
309 // must be due to phi elimination or two addr elimination. If this is
310 // the result of two address elimination, then the vreg is one of the
311 // def-and-use register operand.
313 // It may also be partial redef like this:
314 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
315 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
316 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
317 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
318 // If this is a two-address definition, then we have already processed
319 // the live range. The only problem is that we didn't realize there
320 // are actually two values in the live interval. Because of this we
321 // need to take the LiveRegion that defines this register and split it
323 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
325 const LiveRange *OldLR =
326 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
327 VNInfo *OldValNo = OldLR->valno;
328 SlotIndex DefIndex = OldValNo->def.getRegSlot();
330 // Delete the previous value, which should be short and continuous,
331 // because the 2-addr copy must be in the same MBB as the redef.
332 interval.removeRange(DefIndex, RedefIndex);
334 // The new value number (#1) is defined by the instruction we claimed
336 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
338 // Value#0 is now defined by the 2-addr instruction.
339 OldValNo->def = RedefIndex;
341 // Add the new live interval which replaces the range for the input copy.
342 LiveRange LR(DefIndex, RedefIndex, ValNo);
343 DEBUG(dbgs() << " replace range with " << LR);
344 interval.addRange(LR);
346 // If this redefinition is dead, we need to add a dummy unit live
347 // range covering the def slot.
349 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
352 DEBUG(dbgs() << " RESULT: " << interval);
353 } else if (LV->isPHIJoin(interval.reg)) {
354 // In the case of PHI elimination, each variable definition is only
355 // live until the end of the block. We've already taken care of the
356 // rest of the live range.
358 SlotIndex defIndex = MIIdx.getRegSlot();
359 if (MO.isEarlyClobber())
360 defIndex = MIIdx.getRegSlot(true);
362 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
364 SlotIndex killIndex = getMBBEndIdx(mbb);
365 LiveRange LR(defIndex, killIndex, ValNo);
366 interval.addRange(LR);
367 ValNo->setHasPHIKill(true);
368 DEBUG(dbgs() << " phi-join +" << LR);
370 llvm_unreachable("Multiply defined register");
374 DEBUG(dbgs() << '\n');
377 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
378 MachineBasicBlock::iterator MI,
382 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
383 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
384 getOrCreateInterval(MO.getReg()));
387 /// computeIntervals - computes the live intervals for virtual
388 /// registers. for some ordering of the machine instructions [1,N] a
389 /// live interval is an interval [i, j) where 1 <= i <= j < N for
390 /// which a variable is live
391 void LiveIntervals::computeIntervals() {
392 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
393 << "********** Function: "
394 << ((Value*)MF->getFunction())->getName() << '\n');
396 RegMaskBlocks.resize(MF->getNumBlockIDs());
398 SmallVector<unsigned, 8> UndefUses;
399 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
401 MachineBasicBlock *MBB = MBBI;
402 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
407 // Track the index of the current machine instr.
408 SlotIndex MIIndex = getMBBStartIdx(MBB);
409 DEBUG(dbgs() << "BB#" << MBB->getNumber()
410 << ":\t\t# derived from " << MBB->getName() << "\n");
412 // Skip over empty initial indices.
413 if (getInstructionFromIndex(MIIndex) == 0)
414 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
416 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
418 DEBUG(dbgs() << MIIndex << "\t" << *MI);
419 if (MI->isDebugValue())
421 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
422 "Lost SlotIndex synchronization");
425 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
426 MachineOperand &MO = MI->getOperand(i);
428 // Collect register masks.
429 if (MO.isRegMask()) {
430 RegMaskSlots.push_back(MIIndex.getRegSlot());
431 RegMaskBits.push_back(MO.getRegMask());
435 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
438 // handle register defs - build intervals
440 handleRegisterDef(MBB, MI, MIIndex, MO, i);
441 else if (MO.isUndef())
442 UndefUses.push_back(MO.getReg());
445 // Move to the next instr slot.
446 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
449 // Compute the number of register mask instructions in this block.
450 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
451 RMB.second = RegMaskSlots.size() - RMB.first;;
454 // Create empty intervals for registers defined by implicit_def's (except
455 // for those implicit_def that define values which are liveout of their
457 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
458 unsigned UndefReg = UndefUses[i];
459 (void)getOrCreateInterval(UndefReg);
463 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
464 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
465 return new LiveInterval(reg, Weight);
469 /// computeVirtRegInterval - Compute the live interval of a virtual register,
470 /// based on defs and uses.
471 void LiveIntervals::computeVirtRegInterval(LiveInterval *LI) {
472 assert(LRCalc && "LRCalc not initialized.");
473 assert(LI->empty() && "Should only compute empty intervals.");
474 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
475 LRCalc->createDeadDefs(LI);
476 LRCalc->extendToUses(LI);
480 //===----------------------------------------------------------------------===//
481 // Register Unit Liveness
482 //===----------------------------------------------------------------------===//
484 // Fixed interference typically comes from ABI boundaries: Function arguments
485 // and return values are passed in fixed registers, and so are exception
486 // pointers entering landing pads. Certain instructions require values to be
487 // present in specific registers. That is also represented through fixed
491 /// computeRegUnitInterval - Compute the live interval of a register unit, based
492 /// on the uses and defs of aliasing registers. The interval should be empty,
493 /// or contain only dead phi-defs from ABI blocks.
494 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
495 unsigned Unit = LI->reg;
497 assert(LRCalc && "LRCalc not initialized.");
498 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
500 // The physregs aliasing Unit are the roots and their super-registers.
501 // Create all values as dead defs before extending to uses. Note that roots
502 // may share super-registers. That's OK because createDeadDefs() is
503 // idempotent. It is very rare for a register unit to have multiple roots, so
504 // uniquing super-registers is probably not worthwhile.
505 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
506 unsigned Root = *Roots;
507 if (!MRI->reg_empty(Root))
508 LRCalc->createDeadDefs(LI, Root);
509 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
510 if (!MRI->reg_empty(*Supers))
511 LRCalc->createDeadDefs(LI, *Supers);
515 // Now extend LI to reach all uses.
516 // Ignore uses of reserved registers. We only track defs of those.
517 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
518 unsigned Root = *Roots;
519 if (!isReserved(Root) && !MRI->reg_empty(Root))
520 LRCalc->extendToUses(LI, Root);
521 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
522 unsigned Reg = *Supers;
523 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
524 LRCalc->extendToUses(LI, Reg);
530 /// computeLiveInRegUnits - Precompute the live ranges of any register units
531 /// that are live-in to an ABI block somewhere. Register values can appear
532 /// without a corresponding def when entering the entry block or a landing pad.
534 void LiveIntervals::computeLiveInRegUnits() {
535 RegUnitIntervals.resize(TRI->getNumRegUnits());
536 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
538 // Keep track of the intervals allocated.
539 SmallVector<LiveInterval*, 8> NewIntvs;
541 // Check all basic blocks for live-ins.
542 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
544 const MachineBasicBlock *MBB = MFI;
546 // We only care about ABI blocks: Entry + landing pads.
547 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
550 // Create phi-defs at Begin for all live-in registers.
551 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
552 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
553 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
554 LIE = MBB->livein_end(); LII != LIE; ++LII) {
555 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
556 unsigned Unit = *Units;
557 LiveInterval *Intv = RegUnitIntervals[Unit];
559 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
560 NewIntvs.push_back(Intv);
562 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
564 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
567 DEBUG(dbgs() << '\n');
569 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
571 // Compute the 'normal' part of the intervals.
572 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
573 computeRegUnitInterval(NewIntvs[i]);
577 /// shrinkToUses - After removing some uses of a register, shrink its live
578 /// range to just the remaining uses. This method does not compute reaching
579 /// defs for new uses, and it doesn't remove dead defs.
580 bool LiveIntervals::shrinkToUses(LiveInterval *li,
581 SmallVectorImpl<MachineInstr*> *dead) {
582 DEBUG(dbgs() << "Shrink: " << *li << '\n');
583 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
584 && "Can only shrink virtual registers");
585 // Find all the values used, including PHI kills.
586 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
588 // Blocks that have already been added to WorkList as live-out.
589 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
591 // Visit all instructions reading li->reg.
592 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
593 MachineInstr *UseMI = I.skipInstruction();) {
594 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
596 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
597 LiveRangeQuery LRQ(*li, Idx);
598 VNInfo *VNI = LRQ.valueIn();
600 // This shouldn't happen: readsVirtualRegister returns true, but there is
601 // no live value. It is likely caused by a target getting <undef> flags
603 DEBUG(dbgs() << Idx << '\t' << *UseMI
604 << "Warning: Instr claims to read non-existent value in "
608 // Special case: An early-clobber tied operand reads and writes the
609 // register one slot early.
610 if (VNInfo *DefVNI = LRQ.valueDefined())
613 WorkList.push_back(std::make_pair(Idx, VNI));
616 // Create a new live interval with only minimal live segments per def.
617 LiveInterval NewLI(li->reg, 0);
618 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
623 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
626 // Keep track of the PHIs that are in use.
627 SmallPtrSet<VNInfo*, 8> UsedPHIs;
629 // Extend intervals to reach all uses in WorkList.
630 while (!WorkList.empty()) {
631 SlotIndex Idx = WorkList.back().first;
632 VNInfo *VNI = WorkList.back().second;
634 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
635 SlotIndex BlockStart = getMBBStartIdx(MBB);
637 // Extend the live range for VNI to be live at Idx.
638 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
640 assert(ExtVNI == VNI && "Unexpected existing value number");
641 // Is this a PHIDef we haven't seen before?
642 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
644 // The PHI is live, make sure the predecessors are live-out.
645 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
646 PE = MBB->pred_end(); PI != PE; ++PI) {
647 if (!LiveOut.insert(*PI))
649 SlotIndex Stop = getMBBEndIdx(*PI);
650 // A predecessor is not required to have a live-out value for a PHI.
651 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
652 WorkList.push_back(std::make_pair(Stop, PVNI));
657 // VNI is live-in to MBB.
658 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
659 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
661 // Make sure VNI is live-out from the predecessors.
662 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
663 PE = MBB->pred_end(); PI != PE; ++PI) {
664 if (!LiveOut.insert(*PI))
666 SlotIndex Stop = getMBBEndIdx(*PI);
667 assert(li->getVNInfoBefore(Stop) == VNI &&
668 "Wrong value out of predecessor");
669 WorkList.push_back(std::make_pair(Stop, VNI));
673 // Handle dead values.
674 bool CanSeparate = false;
675 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
680 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
681 assert(LII != NewLI.end() && "Missing live range for PHI");
682 if (LII->end != VNI->def.getDeadSlot())
684 if (VNI->isPHIDef()) {
685 // This is a dead PHI. Remove it.
686 VNI->setIsUnused(true);
687 NewLI.removeRange(*LII);
688 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
691 // This is a dead def. Make sure the instruction knows.
692 MachineInstr *MI = getInstructionFromIndex(VNI->def);
693 assert(MI && "No instruction defining live value");
694 MI->addRegisterDead(li->reg, TRI);
695 if (dead && MI->allDefsAreDead()) {
696 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
702 // Move the trimmed ranges back.
703 li->ranges.swap(NewLI.ranges);
704 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
709 //===----------------------------------------------------------------------===//
710 // Register allocator hooks.
713 void LiveIntervals::addKillFlags() {
714 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
715 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
716 if (MRI->reg_nodbg_empty(Reg))
718 LiveInterval *LI = &getInterval(Reg);
720 // Every instruction that kills Reg corresponds to a live range end point.
721 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
723 // A block index indicates an MBB edge.
724 if (RI->end.isBlock())
726 MachineInstr *MI = getInstructionFromIndex(RI->end);
729 MI->addRegisterKilled(Reg, NULL);
735 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
736 // A local live range must be fully contained inside the block, meaning it is
737 // defined and killed at instructions, not at block boundaries. It is not
738 // live in or or out of any block.
740 // It is technically possible to have a PHI-defined live range identical to a
741 // single block, but we are going to return false in that case.
743 SlotIndex Start = LI.beginIndex();
747 SlotIndex Stop = LI.endIndex();
751 // getMBBFromIndex doesn't need to search the MBB table when both indexes
752 // belong to proper instructions.
753 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
754 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
755 return MBB1 == MBB2 ? MBB1 : NULL;
759 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
760 // Limit the loop depth ridiculousness.
764 // The loop depth is used to roughly estimate the number of times the
765 // instruction is executed. Something like 10^d is simple, but will quickly
766 // overflow a float. This expression behaves like 10^d for small d, but is
767 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
768 // headroom before overflow.
769 // By the way, powf() might be unavailable here. For consistency,
770 // We may take pow(double,double).
771 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
773 return (isDef + isUse) * lc;
776 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
777 MachineInstr* startInst) {
778 LiveInterval& Interval = getOrCreateInterval(reg);
779 VNInfo* VN = Interval.getNextValue(
780 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
781 getVNInfoAllocator());
782 VN->setHasPHIKill(true);
784 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
785 getMBBEndIdx(startInst->getParent()), VN);
786 Interval.addRange(LR);
792 //===----------------------------------------------------------------------===//
793 // Register mask functions
794 //===----------------------------------------------------------------------===//
796 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
797 BitVector &UsableRegs) {
800 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
802 // Use a smaller arrays for local live ranges.
803 ArrayRef<SlotIndex> Slots;
804 ArrayRef<const uint32_t*> Bits;
805 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
806 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
807 Bits = getRegMaskBitsInBlock(MBB->getNumber());
809 Slots = getRegMaskSlots();
810 Bits = getRegMaskBits();
813 // We are going to enumerate all the register mask slots contained in LI.
814 // Start with a binary search of RegMaskSlots to find a starting point.
815 ArrayRef<SlotIndex>::iterator SlotI =
816 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
817 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
819 // No slots in range, LI begins after the last call.
825 assert(*SlotI >= LiveI->start);
826 // Loop over all slots overlapping this segment.
827 while (*SlotI < LiveI->end) {
828 // *SlotI overlaps LI. Collect mask bits.
830 // This is the first overlap. Initialize UsableRegs to all ones.
832 UsableRegs.resize(TRI->getNumRegs(), true);
835 // Remove usable registers clobbered by this mask.
836 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
837 if (++SlotI == SlotE)
840 // *SlotI is beyond the current LI segment.
841 LiveI = LI.advanceTo(LiveI, *SlotI);
844 // Advance SlotI until it overlaps.
845 while (*SlotI < LiveI->start)
846 if (++SlotI == SlotE)
851 //===----------------------------------------------------------------------===//
852 // IntervalUpdate class.
853 //===----------------------------------------------------------------------===//
855 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
856 class LiveIntervals::HMEditor {
859 const MachineRegisterInfo& MRI;
860 const TargetRegisterInfo& TRI;
863 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
864 typedef DenseSet<IntRangePair> RangeSet;
871 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
873 typedef DenseMap<unsigned, RegRanges> BundleRanges;
876 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
877 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
878 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
880 // Update intervals for all operands of MI from OldIdx to NewIdx.
881 // This assumes that MI used to be at OldIdx, and now resides at
883 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
884 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
886 // Collect the operands.
887 RangeSet Entering, Internal, Exiting;
888 bool hasRegMaskOp = false;
889 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
891 // To keep the LiveRanges valid within an interval, move the ranges closest
892 // to the destination first. This prevents ranges from overlapping, to that
893 // APIs like removeRange still work.
894 if (NewIdx < OldIdx) {
895 moveAllEnteringFrom(OldIdx, Entering);
896 moveAllInternalFrom(OldIdx, Internal);
897 moveAllExitingFrom(OldIdx, Exiting);
900 moveAllExitingFrom(OldIdx, Exiting);
901 moveAllInternalFrom(OldIdx, Internal);
902 moveAllEnteringFrom(OldIdx, Entering);
906 updateRegMaskSlots(OldIdx);
909 LIValidator validator;
910 validator = std::for_each(Entering.begin(), Entering.end(), validator);
911 validator = std::for_each(Internal.begin(), Internal.end(), validator);
912 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
913 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
918 // Update intervals for all operands of MI to refer to BundleStart's
920 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
921 if (MI == BundleStart)
922 return; // Bundling instr with itself - nothing to do.
924 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
925 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
926 "SlotIndex <-> Instruction mapping broken for MI");
928 // Collect all ranges already in the bundle.
929 MachineBasicBlock::instr_iterator BII(BundleStart);
930 RangeSet Entering, Internal, Exiting;
931 bool hasRegMaskOp = false;
932 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
933 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
934 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
937 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
938 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
941 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
946 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
947 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
949 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
950 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
951 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
953 moveAllEnteringFromInto(OldIdx, Entering, BR);
954 moveAllInternalFromInto(OldIdx, Internal, BR);
955 moveAllExitingFromInto(OldIdx, Exiting, BR);
959 LIValidator validator;
960 validator = std::for_each(Entering.begin(), Entering.end(), validator);
961 validator = std::for_each(Internal.begin(), Internal.end(), validator);
962 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
963 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
972 DenseSet<const LiveInterval*> Checked, Bogus;
974 void operator()(const IntRangePair& P) {
975 const LiveInterval* LI = P.first;
976 if (Checked.count(LI))
981 SlotIndex LastEnd = LI->begin()->start;
982 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
984 const LiveRange& LR = *LRI;
985 if (LastEnd > LR.start || LR.start >= LR.end)
991 bool rangesOk() const {
992 return Bogus.empty();
997 // Collect IntRangePairs for all operands of MI that may need fixing.
998 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1000 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1001 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1002 hasRegMaskOp = false;
1003 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1004 MOE = MI->operands_end();
1005 MOI != MOE; ++MOI) {
1006 const MachineOperand& MO = *MOI;
1008 if (MO.isRegMask()) {
1009 hasRegMaskOp = true;
1013 if (!MO.isReg() || MO.getReg() == 0)
1016 unsigned Reg = MO.getReg();
1018 // TODO: Currently we're skipping uses that are reserved or have no
1019 // interval, but we're not updating their kills. This should be
1021 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
1024 // Collect ranges for register units. These live ranges are computed on
1025 // demand, so just skip any that haven't been computed yet.
1026 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1027 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1028 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1029 collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx);
1031 // Collect ranges for individual virtual registers.
1032 collectRanges(MO, &LIS.getInterval(Reg),
1033 Entering, Internal, Exiting, OldIdx);
1038 void collectRanges(const MachineOperand &MO, LiveInterval *LI,
1039 RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
1041 if (MO.readsReg()) {
1042 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1044 Entering.insert(std::make_pair(LI, LR));
1047 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1048 assert(LR != 0 && "No live range for def?");
1049 if (LR->end > OldIdx.getDeadSlot())
1050 Exiting.insert(std::make_pair(LI, LR));
1052 Internal.insert(std::make_pair(LI, LR));
1056 BundleRanges createBundleRanges(RangeSet& Entering,
1058 RangeSet& Exiting) {
1061 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1063 LiveInterval* LI = EI->first;
1064 LiveRange* LR = EI->second;
1065 BR[LI->reg].Use = LR;
1068 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1070 LiveInterval* LI = II->first;
1071 LiveRange* LR = II->second;
1072 if (LR->end.isDead()) {
1073 BR[LI->reg].Dead = LR;
1075 BR[LI->reg].EC = LR;
1079 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1081 LiveInterval* LI = EI->first;
1082 LiveRange* LR = EI->second;
1083 BR[LI->reg].Def = LR;
1089 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1090 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1091 if (!OldKillMI->killsRegister(reg))
1092 return; // Bail out if we don't have kill flags on the old register.
1093 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1094 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1095 assert(!NewKillMI->killsRegister(reg) &&
1096 "New kill instr is already a kill.");
1097 OldKillMI->clearRegisterKills(reg, &TRI);
1098 NewKillMI->addRegisterKilled(reg, &TRI);
1101 void updateRegMaskSlots(SlotIndex OldIdx) {
1102 SmallVectorImpl<SlotIndex>::iterator RI =
1103 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1105 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1107 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1108 "RegSlots out of order. Did you move one call across another?");
1111 // Return the last use of reg between NewIdx and OldIdx.
1112 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1113 SlotIndex LastUse = NewIdx;
1114 for (MachineRegisterInfo::use_nodbg_iterator
1115 UI = MRI.use_nodbg_begin(Reg),
1116 UE = MRI.use_nodbg_end();
1117 UI != UE; UI.skipInstruction()) {
1118 const MachineInstr* MI = &*UI;
1119 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1120 if (InstSlot > LastUse && InstSlot < OldIdx)
1126 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1127 LiveInterval* LI = P.first;
1128 LiveRange* LR = P.second;
1129 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1132 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1133 if (LastUse != NewIdx)
1134 moveKillFlags(LI->reg, NewIdx, LastUse);
1135 LR->end = LastUse.getRegSlot();
1138 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1139 LiveInterval* LI = P.first;
1140 LiveRange* LR = P.second;
1141 // Extend the LiveRange if NewIdx is past the end.
1142 if (NewIdx > LR->end) {
1143 // Move kill flags if OldIdx was not originally the end
1144 // (otherwise LR->end points to an invalid slot).
1145 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1146 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1147 moveKillFlags(LI->reg, LR->end, NewIdx);
1149 LR->end = NewIdx.getRegSlot();
1153 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1154 bool GoingUp = NewIdx < OldIdx;
1157 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1159 moveEnteringUpFrom(OldIdx, *EI);
1161 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1163 moveEnteringDownFrom(OldIdx, *EI);
1167 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1168 LiveInterval* LI = P.first;
1169 LiveRange* LR = P.second;
1170 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1171 LR->end <= OldIdx.getDeadSlot() &&
1172 "Range should be internal to OldIdx.");
1174 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1175 Tmp.valno->def = Tmp.start;
1176 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1177 LI->removeRange(*LR);
1181 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1182 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1184 moveInternalFrom(OldIdx, *II);
1187 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1188 LiveRange* LR = P.second;
1189 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1190 "Range should start in OldIdx.");
1191 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1192 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1193 LR->start = NewStart;
1194 LR->valno->def = NewStart;
1197 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1198 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1200 moveExitingFrom(OldIdx, *EI);
1203 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1205 LiveInterval* LI = P.first;
1206 LiveRange* LR = P.second;
1207 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1209 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1210 "Def in bundle should be def range.");
1211 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1212 "If bundle has use for this reg it should be LR.");
1213 BR[LI->reg].Use = LR;
1217 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1218 moveKillFlags(LI->reg, OldIdx, LastUse);
1220 if (LR->start < NewIdx) {
1221 // Becoming a new entering range.
1222 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1223 "Bundle shouldn't be re-defining reg mid-range.");
1224 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1225 "Bundle shouldn't have different use range for same reg.");
1226 LR->end = LastUse.getRegSlot();
1227 BR[LI->reg].Use = LR;
1229 // Becoming a new Dead-def.
1230 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1231 "Live range starting at unexpected slot.");
1232 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1233 assert(BR[LI->reg].Dead == 0 &&
1234 "Can't have def and dead def of same reg in a bundle.");
1235 LR->end = LastUse.getDeadSlot();
1236 BR[LI->reg].Dead = BR[LI->reg].Def;
1237 BR[LI->reg].Def = 0;
1241 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1243 LiveInterval* LI = P.first;
1244 LiveRange* LR = P.second;
1245 if (NewIdx > LR->end) {
1246 // Range extended to bundle. Add to bundle uses.
1247 // Note: Currently adds kill flags to bundle start.
1248 assert(BR[LI->reg].Use == 0 &&
1249 "Bundle already has use range for reg.");
1250 moveKillFlags(LI->reg, LR->end, NewIdx);
1251 LR->end = NewIdx.getRegSlot();
1252 BR[LI->reg].Use = LR;
1254 assert(BR[LI->reg].Use != 0 &&
1255 "Bundle should already have a use range for reg.");
1259 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1261 bool GoingUp = NewIdx < OldIdx;
1264 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1266 moveEnteringUpFromInto(OldIdx, *EI, BR);
1268 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1270 moveEnteringDownFromInto(OldIdx, *EI, BR);
1274 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1276 // TODO: Sane rules for moving ranges into bundles.
1279 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1281 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1283 moveInternalFromInto(OldIdx, *II, BR);
1286 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1288 LiveInterval* LI = P.first;
1289 LiveRange* LR = P.second;
1291 assert(LR->start.isRegister() &&
1292 "Don't know how to merge exiting ECs into bundles yet.");
1294 if (LR->end > NewIdx.getDeadSlot()) {
1295 // This range is becoming an exiting range on the bundle.
1296 // If there was an old dead-def of this reg, delete it.
1297 if (BR[LI->reg].Dead != 0) {
1298 LI->removeRange(*BR[LI->reg].Dead);
1299 BR[LI->reg].Dead = 0;
1301 assert(BR[LI->reg].Def == 0 &&
1302 "Can't have two defs for the same variable exiting a bundle.");
1303 LR->start = NewIdx.getRegSlot();
1304 LR->valno->def = LR->start;
1305 BR[LI->reg].Def = LR;
1307 // This range is becoming internal to the bundle.
1308 assert(LR->end == NewIdx.getRegSlot() &&
1309 "Can't bundle def whose kill is before the bundle");
1310 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1311 // Already have a def for this. Just delete range.
1312 LI->removeRange(*LR);
1314 // Make range dead, record.
1315 LR->end = NewIdx.getDeadSlot();
1316 BR[LI->reg].Dead = LR;
1317 assert(BR[LI->reg].Use == LR &&
1318 "Range becoming dead should currently be use.");
1320 // In both cases the range is no longer a use on the bundle.
1321 BR[LI->reg].Use = 0;
1325 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1327 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1329 moveExitingFromInto(OldIdx, *EI, BR);
1334 void LiveIntervals::handleMove(MachineInstr* MI) {
1335 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1336 Indexes->removeMachineInstrFromMaps(MI);
1337 SlotIndex NewIndex = MI->isInsideBundle() ?
1338 Indexes->getInstructionIndex(MI) :
1339 Indexes->insertMachineInstrInMaps(MI);
1340 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1341 OldIndex < getMBBEndIdx(MI->getParent()) &&
1342 "Cannot handle moves across basic block boundaries.");
1343 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1345 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1346 HME.moveAllRangesFrom(MI, OldIndex);
1349 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1350 MachineInstr* BundleStart) {
1351 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1352 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1353 HME.moveAllRangesInto(MI, BundleStart);