1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<AliasAnalysis>();
69 AU.addPreserved<AliasAnalysis>();
70 // LiveVariables isn't really required by this analysis, it is only required
71 // here to make sure it is live during TwoAddressInstructionPass and
72 // PHIElimination. This is temporary.
73 AU.addRequired<LiveVariables>();
74 AU.addPreserved<LiveVariables>();
75 AU.addPreservedID(MachineLoopInfoID);
76 AU.addRequiredTransitiveID(MachineDominatorsID);
77 AU.addPreservedID(MachineDominatorsID);
78 AU.addPreserved<SlotIndexes>();
79 AU.addRequiredTransitive<SlotIndexes>();
80 MachineFunctionPass::getAnalysisUsage(AU);
83 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
84 DomTree(nullptr), LRCalc(nullptr) {
85 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
88 LiveIntervals::~LiveIntervals() {
92 void LiveIntervals::releaseMemory() {
93 // Free the live intervals themselves.
94 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
95 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
96 VirtRegIntervals.clear();
99 RegMaskBlocks.clear();
101 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
102 delete RegUnitRanges[i];
103 RegUnitRanges.clear();
105 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
106 VNInfoAllocator.Reset();
109 /// runOnMachineFunction - calculates LiveIntervals
111 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
113 MRI = &MF->getRegInfo();
114 TRI = MF->getSubtarget().getRegisterInfo();
115 TII = MF->getSubtarget().getInstrInfo();
116 AA = &getAnalysis<AliasAnalysis>();
117 Indexes = &getAnalysis<SlotIndexes>();
118 DomTree = &getAnalysis<MachineDominatorTree>();
120 LRCalc = new LiveRangeCalc();
122 // Allocate space for all virtual registers.
123 VirtRegIntervals.resize(MRI->getNumVirtRegs());
127 computeLiveInRegUnits();
129 if (EnablePrecomputePhysRegs) {
130 // For stress testing, precompute live ranges of all physical register
131 // units, including reserved registers.
132 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
139 /// print - Implement the dump method.
140 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
141 OS << "********** INTERVALS **********\n";
143 // Dump the regunits.
144 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
145 if (LiveRange *LR = RegUnitRanges[i])
146 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
148 // Dump the virtregs.
149 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
150 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
151 if (hasInterval(Reg))
152 OS << getInterval(Reg) << '\n';
156 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
157 OS << ' ' << RegMaskSlots[i];
163 void LiveIntervals::printInstrs(raw_ostream &OS) const {
164 OS << "********** MACHINEINSTRS **********\n";
165 MF->print(OS, Indexes);
168 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
169 void LiveIntervals::dumpInstrs() const {
174 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
175 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
176 llvm::huge_valf : 0.0F;
177 return new LiveInterval(reg, Weight);
181 /// computeVirtRegInterval - Compute the live interval of a virtual register,
182 /// based on defs and uses.
183 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
184 assert(LRCalc && "LRCalc not initialized.");
185 assert(LI.empty() && "Should only compute empty intervals.");
186 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
187 LRCalc->createDeadDefs(LI);
188 LRCalc->extendToUses(LI);
189 computeDeadValues(LI, LI);
192 void LiveIntervals::computeVirtRegs() {
193 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
194 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
195 if (MRI->reg_nodbg_empty(Reg))
197 createAndComputeVirtRegInterval(Reg);
201 void LiveIntervals::computeRegMasks() {
202 RegMaskBlocks.resize(MF->getNumBlockIDs());
204 // Find all instructions with regmask operands.
205 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
207 MachineBasicBlock *MBB = MBBI;
208 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
209 RMB.first = RegMaskSlots.size();
210 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
212 for (MIOperands MO(MI); MO.isValid(); ++MO) {
213 if (!MO->isRegMask())
215 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
216 RegMaskBits.push_back(MO->getRegMask());
218 // Compute the number of register mask instructions in this block.
219 RMB.second = RegMaskSlots.size() - RMB.first;
223 //===----------------------------------------------------------------------===//
224 // Register Unit Liveness
225 //===----------------------------------------------------------------------===//
227 // Fixed interference typically comes from ABI boundaries: Function arguments
228 // and return values are passed in fixed registers, and so are exception
229 // pointers entering landing pads. Certain instructions require values to be
230 // present in specific registers. That is also represented through fixed
234 /// computeRegUnitInterval - Compute the live range of a register unit, based
235 /// on the uses and defs of aliasing registers. The range should be empty,
236 /// or contain only dead phi-defs from ABI blocks.
237 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
238 assert(LRCalc && "LRCalc not initialized.");
239 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
241 // The physregs aliasing Unit are the roots and their super-registers.
242 // Create all values as dead defs before extending to uses. Note that roots
243 // may share super-registers. That's OK because createDeadDefs() is
244 // idempotent. It is very rare for a register unit to have multiple roots, so
245 // uniquing super-registers is probably not worthwhile.
246 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
247 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
248 Supers.isValid(); ++Supers) {
249 if (!MRI->reg_empty(*Supers))
250 LRCalc->createDeadDefs(LR, *Supers);
254 // Now extend LR to reach all uses.
255 // Ignore uses of reserved registers. We only track defs of those.
256 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
257 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
258 Supers.isValid(); ++Supers) {
259 unsigned Reg = *Supers;
260 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
261 LRCalc->extendToUses(LR, Reg);
267 /// computeLiveInRegUnits - Precompute the live ranges of any register units
268 /// that are live-in to an ABI block somewhere. Register values can appear
269 /// without a corresponding def when entering the entry block or a landing pad.
271 void LiveIntervals::computeLiveInRegUnits() {
272 RegUnitRanges.resize(TRI->getNumRegUnits());
273 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
275 // Keep track of the live range sets allocated.
276 SmallVector<unsigned, 8> NewRanges;
278 // Check all basic blocks for live-ins.
279 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
281 const MachineBasicBlock *MBB = MFI;
283 // We only care about ABI blocks: Entry + landing pads.
284 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
287 // Create phi-defs at Begin for all live-in registers.
288 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
289 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
290 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
291 LIE = MBB->livein_end(); LII != LIE; ++LII) {
292 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
293 unsigned Unit = *Units;
294 LiveRange *LR = RegUnitRanges[Unit];
296 LR = RegUnitRanges[Unit] = new LiveRange();
297 NewRanges.push_back(Unit);
299 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
301 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
304 DEBUG(dbgs() << '\n');
306 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
308 // Compute the 'normal' part of the ranges.
309 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
310 unsigned Unit = NewRanges[i];
311 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
316 static void createSegmentsForValues(LiveRange &LR,
317 iterator_range<LiveInterval::vni_iterator> VNIs) {
318 for (auto VNI : VNIs) {
321 SlotIndex Def = VNI->def;
322 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
326 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
328 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
329 ShrinkToUsesWorkList &WorkList,
330 const LiveRange &OldRange) {
331 // Keep track of the PHIs that are in use.
332 SmallPtrSet<VNInfo*, 8> UsedPHIs;
333 // Blocks that have already been added to WorkList as live-out.
334 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
336 // Extend intervals to reach all uses in WorkList.
337 while (!WorkList.empty()) {
338 SlotIndex Idx = WorkList.back().first;
339 VNInfo *VNI = WorkList.back().second;
341 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
342 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
344 // Extend the live range for VNI to be live at Idx.
345 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
346 assert(ExtVNI == VNI && "Unexpected existing value number");
348 // Is this a PHIDef we haven't seen before?
349 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
350 !UsedPHIs.insert(VNI).second)
352 // The PHI is live, make sure the predecessors are live-out.
353 for (auto &Pred : MBB->predecessors()) {
354 if (!LiveOut.insert(Pred).second)
356 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
357 // A predecessor is not required to have a live-out value for a PHI.
358 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
359 WorkList.push_back(std::make_pair(Stop, PVNI));
364 // VNI is live-in to MBB.
365 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
366 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
368 // Make sure VNI is live-out from the predecessors.
369 for (auto &Pred : MBB->predecessors()) {
370 if (!LiveOut.insert(Pred).second)
372 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
373 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
374 "Wrong value out of predecessor");
375 WorkList.push_back(std::make_pair(Stop, VNI));
380 /// shrinkToUses - After removing some uses of a register, shrink its live
381 /// range to just the remaining uses. This method does not compute reaching
382 /// defs for new uses, and it doesn't remove dead defs.
383 bool LiveIntervals::shrinkToUses(LiveInterval *li,
384 SmallVectorImpl<MachineInstr*> *dead) {
385 DEBUG(dbgs() << "Shrink: " << *li << '\n');
386 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
387 && "Can only shrink virtual registers");
389 // Shrink subregister live ranges.
390 for (LiveInterval::subrange_iterator I = li->subrange_begin(),
391 E = li->subrange_end(); I != E; ++I) {
392 shrinkToUses(*I, li->reg);
395 // Find all the values used, including PHI kills.
396 ShrinkToUsesWorkList WorkList;
398 // Visit all instructions reading li->reg.
399 for (MachineRegisterInfo::reg_instr_iterator
400 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
402 MachineInstr *UseMI = &*(I++);
403 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
405 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
406 LiveQueryResult LRQ = li->Query(Idx);
407 VNInfo *VNI = LRQ.valueIn();
409 // This shouldn't happen: readsVirtualRegister returns true, but there is
410 // no live value. It is likely caused by a target getting <undef> flags
412 DEBUG(dbgs() << Idx << '\t' << *UseMI
413 << "Warning: Instr claims to read non-existent value in "
417 // Special case: An early-clobber tied operand reads and writes the
418 // register one slot early.
419 if (VNInfo *DefVNI = LRQ.valueDefined())
422 WorkList.push_back(std::make_pair(Idx, VNI));
425 // Create new live ranges with only minimal live segments per def.
427 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
428 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
430 // Handle dead values.
432 computeDeadValues(NewLR, *li, &CanSeparate, li->reg, dead);
434 // Move the trimmed segments back.
435 li->segments.swap(NewLR.segments);
436 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
440 void LiveIntervals::computeDeadValues(LiveRange &Segments, LiveRange &LR,
441 bool *CanSeparateRes, unsigned Reg,
442 SmallVectorImpl<MachineInstr*> *dead) {
443 bool CanSeparate = false;
444 for (auto VNI : make_range(LR.vni_begin(), LR.vni_end())) {
447 LiveRange::iterator LRI = Segments.FindSegmentContaining(VNI->def);
448 assert(LRI != Segments.end() && "Missing segment for PHI");
449 if (LRI->end != VNI->def.getDeadSlot())
451 if (VNI->isPHIDef()) {
452 // This is a dead PHI. Remove it.
454 Segments.removeSegment(LRI->start, LRI->end);
455 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
457 } else if (dead != nullptr) {
458 // This is a dead def. Make sure the instruction knows.
459 MachineInstr *MI = getInstructionFromIndex(VNI->def);
460 assert(MI && "No instruction defining live value");
461 MI->addRegisterDead(Reg, TRI);
462 if (dead && MI->allDefsAreDead()) {
463 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
468 if (CanSeparateRes != nullptr)
469 *CanSeparateRes = CanSeparate;
472 bool LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
474 DEBUG(dbgs() << "Shrink: " << SR << '\n');
475 assert(TargetRegisterInfo::isVirtualRegister(Reg)
476 && "Can only shrink virtual registers");
477 // Find all the values used, including PHI kills.
478 ShrinkToUsesWorkList WorkList;
480 // Visit all instructions reading Reg.
482 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
483 MachineInstr *UseMI = MO.getParent();
484 if (UseMI->isDebugValue())
486 // Maybe the operand is for a subregister we don't care about.
487 unsigned SubReg = MO.getSubReg();
489 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
490 if ((SubRegMask & SR.LaneMask) == 0)
493 // We only need to visit each instruction once.
494 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
499 LiveQueryResult LRQ = SR.Query(Idx);
500 VNInfo *VNI = LRQ.valueIn();
501 // For Subranges it is possible that only undef values are left in that
502 // part of the subregister, so there is no real liverange at the use
506 // Special case: An early-clobber tied operand reads and writes the
507 // register one slot early.
508 if (VNInfo *DefVNI = LRQ.valueDefined())
511 WorkList.push_back(std::make_pair(Idx, VNI));
514 // Create a new live ranges with only minimal live segments per def.
516 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
517 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
519 // Handle dead values.
521 computeDeadValues(NewLR, SR, &CanSeparate);
523 // Move the trimmed ranges back.
524 SR.segments.swap(NewLR.segments);
525 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
529 void LiveIntervals::extendToIndices(LiveRange &LR,
530 ArrayRef<SlotIndex> Indices) {
531 assert(LRCalc && "LRCalc not initialized.");
532 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
533 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
534 LRCalc->extend(LR, Indices[i]);
537 void LiveIntervals::pruneValue(LiveInterval *LI, SlotIndex Kill,
538 SmallVectorImpl<SlotIndex> *EndPoints) {
539 LiveQueryResult LRQ = LI->Query(Kill);
540 VNInfo *VNI = LRQ.valueOut();
544 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
545 SlotIndex MBBStart, MBBEnd;
546 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(KillMBB);
548 // If VNI isn't live out from KillMBB, the value is trivially pruned.
549 if (LRQ.endPoint() < MBBEnd) {
550 LI->removeSegment(Kill, LRQ.endPoint());
551 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
555 // VNI is live out of KillMBB.
556 LI->removeSegment(Kill, MBBEnd);
557 if (EndPoints) EndPoints->push_back(MBBEnd);
559 // Find all blocks that are reachable from KillMBB without leaving VNI's live
560 // range. It is possible that KillMBB itself is reachable, so start a DFS
561 // from each successor.
562 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
564 for (MachineBasicBlock::succ_iterator
565 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
566 SuccI != SuccE; ++SuccI) {
567 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
568 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
570 MachineBasicBlock *MBB = *I;
572 // Check if VNI is live in to MBB.
573 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
574 LiveQueryResult LRQ = LI->Query(MBBStart);
575 if (LRQ.valueIn() != VNI) {
576 // This block isn't part of the VNI segment. Prune the search.
581 // Prune the search if VNI is killed in MBB.
582 if (LRQ.endPoint() < MBBEnd) {
583 LI->removeSegment(MBBStart, LRQ.endPoint());
584 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
589 // VNI is live through MBB.
590 LI->removeSegment(MBBStart, MBBEnd);
591 if (EndPoints) EndPoints->push_back(MBBEnd);
597 //===----------------------------------------------------------------------===//
598 // Register allocator hooks.
601 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
602 // Keep track of regunit ranges.
603 SmallVector<std::pair<LiveRange*, LiveRange::iterator>, 8> RU;
605 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
606 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
607 if (MRI->reg_nodbg_empty(Reg))
609 LiveInterval *LI = &getInterval(Reg);
613 // Find the regunit intervals for the assigned register. They may overlap
614 // the virtual register live range, cancelling any kills.
616 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
618 LiveRange &RURanges = getRegUnit(*Units);
619 if (RURanges.empty())
621 RU.push_back(std::make_pair(&RURanges, RURanges.find(LI->begin()->end)));
624 // Every instruction that kills Reg corresponds to a segment range end
626 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
628 // A block index indicates an MBB edge.
629 if (RI->end.isBlock())
631 MachineInstr *MI = getInstructionFromIndex(RI->end);
635 // Check if any of the regunits are live beyond the end of RI. That could
636 // happen when a physreg is defined as a copy of a virtreg:
638 // %EAX = COPY %vreg5
639 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
642 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
643 bool CancelKill = false;
644 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
645 LiveRange &RRanges = *RU[u].first;
646 LiveRange::iterator &I = RU[u].second;
647 if (I == RRanges.end())
649 I = RRanges.advanceTo(I, RI->end);
650 if (I == RRanges.end() || I->start >= RI->end)
652 // I is overlapping RI.
657 MI->clearRegisterKills(Reg, nullptr);
659 MI->addRegisterKilled(Reg, nullptr);
665 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
666 // A local live range must be fully contained inside the block, meaning it is
667 // defined and killed at instructions, not at block boundaries. It is not
668 // live in or or out of any block.
670 // It is technically possible to have a PHI-defined live range identical to a
671 // single block, but we are going to return false in that case.
673 SlotIndex Start = LI.beginIndex();
677 SlotIndex Stop = LI.endIndex();
681 // getMBBFromIndex doesn't need to search the MBB table when both indexes
682 // belong to proper instructions.
683 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
684 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
685 return MBB1 == MBB2 ? MBB1 : nullptr;
689 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
690 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
692 const VNInfo *PHI = *I;
693 if (PHI->isUnused() || !PHI->isPHIDef())
695 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
696 // Conservatively return true instead of scanning huge predecessor lists.
697 if (PHIMBB->pred_size() > 100)
699 for (MachineBasicBlock::const_pred_iterator
700 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
701 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
708 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
709 const MachineBlockFrequencyInfo *MBFI,
710 const MachineInstr *MI) {
711 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
712 const float Scale = 1.0f / MBFI->getEntryFreq();
713 return (isDef + isUse) * (Freq.getFrequency() * Scale);
717 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
718 LiveInterval& Interval = createEmptyInterval(reg);
719 VNInfo* VN = Interval.getNextValue(
720 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
721 getVNInfoAllocator());
722 LiveRange::Segment S(
723 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
724 getMBBEndIdx(startInst->getParent()), VN);
725 Interval.addSegment(S);
731 //===----------------------------------------------------------------------===//
732 // Register mask functions
733 //===----------------------------------------------------------------------===//
735 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
736 BitVector &UsableRegs) {
739 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
741 // Use a smaller arrays for local live ranges.
742 ArrayRef<SlotIndex> Slots;
743 ArrayRef<const uint32_t*> Bits;
744 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
745 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
746 Bits = getRegMaskBitsInBlock(MBB->getNumber());
748 Slots = getRegMaskSlots();
749 Bits = getRegMaskBits();
752 // We are going to enumerate all the register mask slots contained in LI.
753 // Start with a binary search of RegMaskSlots to find a starting point.
754 ArrayRef<SlotIndex>::iterator SlotI =
755 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
756 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
758 // No slots in range, LI begins after the last call.
764 assert(*SlotI >= LiveI->start);
765 // Loop over all slots overlapping this segment.
766 while (*SlotI < LiveI->end) {
767 // *SlotI overlaps LI. Collect mask bits.
769 // This is the first overlap. Initialize UsableRegs to all ones.
771 UsableRegs.resize(TRI->getNumRegs(), true);
774 // Remove usable registers clobbered by this mask.
775 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
776 if (++SlotI == SlotE)
779 // *SlotI is beyond the current LI segment.
780 LiveI = LI.advanceTo(LiveI, *SlotI);
783 // Advance SlotI until it overlaps.
784 while (*SlotI < LiveI->start)
785 if (++SlotI == SlotE)
790 //===----------------------------------------------------------------------===//
791 // IntervalUpdate class.
792 //===----------------------------------------------------------------------===//
794 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
795 class LiveIntervals::HMEditor {
798 const MachineRegisterInfo& MRI;
799 const TargetRegisterInfo& TRI;
802 SmallPtrSet<LiveRange*, 8> Updated;
806 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
807 const TargetRegisterInfo& TRI,
808 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
809 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
810 UpdateFlags(UpdateFlags) {}
812 // FIXME: UpdateFlags is a workaround that creates live intervals for all
813 // physregs, even those that aren't needed for regalloc, in order to update
814 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
815 // flags, and postRA passes will use a live register utility instead.
816 LiveRange *getRegUnitLI(unsigned Unit) {
818 return &LIS.getRegUnit(Unit);
819 return LIS.getCachedRegUnit(Unit);
822 /// Update all live ranges touched by MI, assuming a move from OldIdx to
824 void updateAllRanges(MachineInstr *MI) {
825 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
826 bool hasRegMask = false;
827 for (MIOperands MO(MI); MO.isValid(); ++MO) {
832 // Aggressively clear all kill flags.
833 // They are reinserted by VirtRegRewriter.
835 MO->setIsKill(false);
837 unsigned Reg = MO->getReg();
840 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
841 LiveInterval &LI = LIS.getInterval(Reg);
842 if (LI.hasSubRanges()) {
843 unsigned SubReg = MO->getSubReg();
844 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
845 for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
846 SE = LI.subrange_end(); S != SE; ++S) {
847 if ((S->LaneMask & LaneMask) == 0)
849 updateRange(*S, Reg, S->LaneMask);
852 updateRange(LI, Reg, 0);
856 // For physregs, only update the regunits that actually have a
857 // precomputed live range.
858 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
859 if (LiveRange *LR = getRegUnitLI(*Units))
860 updateRange(*LR, *Units, 0);
863 updateRegMaskSlots();
867 /// Update a single live range, assuming an instruction has been moved from
868 /// OldIdx to NewIdx.
869 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
870 if (!Updated.insert(&LR).second)
874 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
875 dbgs() << PrintReg(Reg);
877 dbgs() << format(" L%04X", LaneMask);
879 dbgs() << PrintRegUnit(Reg, &TRI);
881 dbgs() << ":\t" << LR << '\n';
883 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
886 handleMoveUp(LR, Reg, LaneMask);
887 DEBUG(dbgs() << " -->\t" << LR << '\n');
891 /// Update LR to reflect an instruction has been moved downwards from OldIdx
894 /// 1. Live def at OldIdx:
895 /// Move def to NewIdx, assert endpoint after NewIdx.
897 /// 2. Live def at OldIdx, killed at NewIdx:
898 /// Change to dead def at NewIdx.
899 /// (Happens when bundling def+kill together).
901 /// 3. Dead def at OldIdx:
902 /// Move def to NewIdx, possibly across another live value.
904 /// 4. Def at OldIdx AND at NewIdx:
905 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
906 /// (Happens when bundling multiple defs together).
908 /// 5. Value read at OldIdx, killed before NewIdx:
909 /// Extend kill to NewIdx.
911 void handleMoveDown(LiveRange &LR) {
912 // First look for a kill at OldIdx.
913 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
914 LiveRange::iterator E = LR.end();
915 // Is LR even live at OldIdx?
916 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
919 // Handle a live-in value.
920 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
921 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
922 // If the live-in value already extends to NewIdx, there is nothing to do.
923 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
925 // Aggressively remove all kill flags from the old kill point.
926 // Kill flags shouldn't be used while live intervals exist, they will be
927 // reinserted by VirtRegRewriter.
928 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
929 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
930 if (MO->isReg() && MO->isUse())
931 MO->setIsKill(false);
932 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
933 // overlapping ranges. Case 5 above.
934 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
935 // If this was a kill, there may also be a def. Otherwise we're done.
941 // Check for a def at OldIdx.
942 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
944 // We have a def at OldIdx.
945 VNInfo *DefVNI = I->valno;
946 assert(DefVNI->def == I->start && "Inconsistent def");
947 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
948 // If the defined value extends beyond NewIdx, just move the def down.
949 // This is case 1 above.
950 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
951 I->start = DefVNI->def;
954 // The remaining possibilities are now:
955 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
956 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
957 // In either case, it is possible that there is an existing def at NewIdx.
958 assert((I->end == OldIdx.getDeadSlot() ||
959 SlotIndex::isSameInstr(I->end, NewIdx)) &&
960 "Cannot move def below kill");
961 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
962 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
963 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
964 // coalesced into that value.
965 assert(NewI->valno != DefVNI && "Multiple defs of value?");
966 LR.removeValNo(DefVNI);
969 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
970 // If the def at OldIdx was dead, we allow it to be moved across other LR
971 // values. The new range should be placed immediately before NewI, move any
972 // intermediate ranges up.
973 assert(NewI != I && "Inconsistent iterators");
974 std::copy(std::next(I), NewI, I);
976 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
979 /// Update LR to reflect an instruction has been moved upwards from OldIdx
982 /// 1. Live def at OldIdx:
983 /// Hoist def to NewIdx.
985 /// 2. Dead def at OldIdx:
986 /// Hoist def+end to NewIdx, possibly move across other values.
988 /// 3. Dead def at OldIdx AND existing def at NewIdx:
989 /// Remove value defined at OldIdx, coalescing it with existing value.
991 /// 4. Live def at OldIdx AND existing def at NewIdx:
992 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
993 /// (Happens when bundling multiple defs together).
995 /// 5. Value killed at OldIdx:
996 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
999 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1000 // First look for a kill at OldIdx.
1001 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1002 LiveRange::iterator E = LR.end();
1003 // Is LR even live at OldIdx?
1004 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1007 // Handle a live-in value.
1008 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1009 // If the live-in value isn't killed here, there is nothing to do.
1010 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1012 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1013 // another use, we need to search for that use. Case 5 above.
1014 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1016 // If OldIdx also defines a value, there couldn't have been another use.
1017 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1018 // No def, search for the new kill.
1019 // This can never be an early clobber kill since there is no def.
1020 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1025 // Now deal with the def at OldIdx.
1026 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1027 VNInfo *DefVNI = I->valno;
1028 assert(DefVNI->def == I->start && "Inconsistent def");
1029 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1031 // Check for an existing def at NewIdx.
1032 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1033 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1034 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1035 // There is an existing def at NewIdx.
1036 if (I->end.isDead()) {
1037 // Case 3: Remove the dead def at OldIdx.
1038 LR.removeValNo(DefVNI);
1041 // Case 4: Replace def at NewIdx with live def at OldIdx.
1042 I->start = DefVNI->def;
1043 LR.removeValNo(NewI->valno);
1047 // There is no existing def at NewIdx. Hoist DefVNI.
1048 if (!I->end.isDead()) {
1049 // Leave the end point of a live def.
1050 I->start = DefVNI->def;
1054 // DefVNI is a dead def. It may have been moved across other values in LR,
1055 // so move I up to NewI. Slide [NewI;I) down one position.
1056 std::copy_backward(NewI, I, std::next(I));
1057 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1060 void updateRegMaskSlots() {
1061 SmallVectorImpl<SlotIndex>::iterator RI =
1062 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1064 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1065 "No RegMask at OldIdx.");
1066 *RI = NewIdx.getRegSlot();
1067 assert((RI == LIS.RegMaskSlots.begin() ||
1068 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1069 "Cannot move regmask instruction above another call");
1070 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1071 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1072 "Cannot move regmask instruction below another call");
1075 // Return the last use of reg between NewIdx and OldIdx.
1076 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1078 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1079 SlotIndex LastUse = NewIdx;
1080 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1081 unsigned SubReg = MO.getSubReg();
1082 if (SubReg != 0 && LaneMask != 0
1083 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1086 const MachineInstr *MI = MO.getParent();
1087 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1088 if (InstSlot > LastUse && InstSlot < OldIdx)
1094 // This is a regunit interval, so scanning the use list could be very
1095 // expensive. Scan upwards from OldIdx instead.
1096 assert(NewIdx < OldIdx && "Expected upwards move");
1097 SlotIndexes *Indexes = LIS.getSlotIndexes();
1098 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1100 // OldIdx may not correspond to an instruction any longer, so set MII to
1101 // point to the next instruction after OldIdx, or MBB->end().
1102 MachineBasicBlock::iterator MII = MBB->end();
1103 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1104 Indexes->getNextNonNullIndex(OldIdx)))
1105 if (MI->getParent() == MBB)
1108 MachineBasicBlock::iterator Begin = MBB->begin();
1109 while (MII != Begin) {
1110 if ((--MII)->isDebugValue())
1112 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1114 // Stop searching when NewIdx is reached.
1115 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1118 // Check if MII uses Reg.
1119 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1121 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1122 TRI.hasRegUnit(MO->getReg(), Reg))
1125 // Didn't reach NewIdx. It must be the first instruction in the block.
1130 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1131 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1132 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1133 Indexes->removeMachineInstrFromMaps(MI);
1134 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1135 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1136 OldIndex < getMBBEndIdx(MI->getParent()) &&
1137 "Cannot handle moves across basic block boundaries.");
1139 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1140 HME.updateAllRanges(MI);
1143 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1144 MachineInstr* BundleStart,
1146 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1147 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1148 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1149 HME.updateAllRanges(MI);
1152 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1153 const MachineBasicBlock::iterator End,
1154 const SlotIndex endIdx,
1155 LiveRange &LR, const unsigned Reg,
1156 const unsigned LaneMask) {
1157 LiveInterval::iterator LII = LR.find(endIdx);
1158 SlotIndex lastUseIdx;
1159 if (LII != LR.end() && LII->start < endIdx)
1160 lastUseIdx = LII->end;
1164 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1166 MachineInstr *MI = I;
1167 if (MI->isDebugValue())
1170 SlotIndex instrIdx = getInstructionIndex(MI);
1171 bool isStartValid = getInstructionFromIndex(LII->start);
1172 bool isEndValid = getInstructionFromIndex(LII->end);
1174 // FIXME: This doesn't currently handle early-clobber or multiple removed
1175 // defs inside of the region to repair.
1176 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1177 OE = MI->operands_end(); OI != OE; ++OI) {
1178 const MachineOperand &MO = *OI;
1179 if (!MO.isReg() || MO.getReg() != Reg)
1182 unsigned SubReg = MO.getSubReg();
1183 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1184 if ((Mask & LaneMask) == 0)
1188 if (!isStartValid) {
1189 if (LII->end.isDead()) {
1190 SlotIndex prevStart;
1191 if (LII != LR.begin())
1192 prevStart = std::prev(LII)->start;
1194 // FIXME: This could be more efficient if there was a
1195 // removeSegment method that returned an iterator.
1196 LR.removeSegment(*LII, true);
1197 if (prevStart.isValid())
1198 LII = LR.find(prevStart);
1202 LII->start = instrIdx.getRegSlot();
1203 LII->valno->def = instrIdx.getRegSlot();
1204 if (MO.getSubReg() && !MO.isUndef())
1205 lastUseIdx = instrIdx.getRegSlot();
1207 lastUseIdx = SlotIndex();
1212 if (!lastUseIdx.isValid()) {
1213 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1214 LiveRange::Segment S(instrIdx.getRegSlot(),
1215 instrIdx.getDeadSlot(), VNI);
1216 LII = LR.addSegment(S);
1217 } else if (LII->start != instrIdx.getRegSlot()) {
1218 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1219 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1220 LII = LR.addSegment(S);
1223 if (MO.getSubReg() && !MO.isUndef())
1224 lastUseIdx = instrIdx.getRegSlot();
1226 lastUseIdx = SlotIndex();
1227 } else if (MO.isUse()) {
1228 // FIXME: This should probably be handled outside of this branch,
1229 // either as part of the def case (for defs inside of the region) or
1230 // after the loop over the region.
1231 if (!isEndValid && !LII->end.isBlock())
1232 LII->end = instrIdx.getRegSlot();
1233 if (!lastUseIdx.isValid())
1234 lastUseIdx = instrIdx.getRegSlot();
1241 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1242 MachineBasicBlock::iterator Begin,
1243 MachineBasicBlock::iterator End,
1244 ArrayRef<unsigned> OrigRegs) {
1245 // Find anchor points, which are at the beginning/end of blocks or at
1246 // instructions that already have indexes.
1247 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1249 while (End != MBB->end() && !Indexes->hasIndex(End))
1253 if (End == MBB->end())
1254 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1256 endIdx = getInstructionIndex(End);
1258 Indexes->repairIndexesInRange(MBB, Begin, End);
1260 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1262 MachineInstr *MI = I;
1263 if (MI->isDebugValue())
1265 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1266 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1268 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1269 !hasInterval(MOI->getReg())) {
1270 createAndComputeVirtRegInterval(MOI->getReg());
1275 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1276 unsigned Reg = OrigRegs[i];
1277 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1280 LiveInterval &LI = getInterval(Reg);
1281 // FIXME: Should we support undefs that gain defs?
1282 if (!LI.hasAtLeastOneValue())
1285 for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
1286 SE = LI.subrange_end(); S != SE; ++S) {
1287 repairOldRegInRange(Begin, End, endIdx, *S, Reg, S->LaneMask);
1289 repairOldRegInRange(Begin, End, endIdx, LI, Reg);