1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numIntervals, "Number of original intervals");
40 STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
41 STATISTIC(numJoins , "Number of interval joins performed");
42 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
43 STATISTIC(numFolded , "Number of loads/stores folded into instructions");
46 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
49 EnableJoining("join-liveintervals",
50 cl::desc("Coallesce copies (default=true)"),
54 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.addRequired<LiveVariables>();
56 AU.addPreservedID(PHIEliminationID);
57 AU.addRequiredID(PHIEliminationID);
58 AU.addRequiredID(TwoAddressInstructionPassID);
59 AU.addRequired<LoopInfo>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 void LiveIntervals::releaseMemory() {
71 static bool isZeroLengthInterval(LiveInterval *li) {
72 for (LiveInterval::Ranges::const_iterator
73 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
74 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
80 /// runOnMachineFunction - Register allocate the whole function
82 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
84 tm_ = &fn.getTarget();
85 mri_ = tm_->getRegisterInfo();
86 tii_ = tm_->getInstrInfo();
87 lv_ = &getAnalysis<LiveVariables>();
88 allocatableRegs_ = mri_->getAllocatableSet(fn);
89 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
91 // Number MachineInstrs and MachineBasicBlocks.
92 // Initialize MBB indexes to a sentinal.
93 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
96 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
98 // Set the MBB2IdxMap entry for this MBB.
99 MBB2IdxMap[MBB->getNumber()] = MIIndex;
101 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
103 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
104 assert(inserted && "multiple MachineInstr -> index mappings");
105 i2miMap_.push_back(I);
106 MIIndex += InstrSlots::NUM;
112 numIntervals += getNumIntervals();
114 DOUT << "********** INTERVALS **********\n";
115 for (iterator I = begin(), E = end(); I != E; ++I) {
116 I->second.print(DOUT, mri_);
120 // Join (coallesce) intervals if requested.
121 if (EnableJoining) joinIntervals();
123 numIntervalsAfter += getNumIntervals();
126 // perform a final pass over the instructions and compute spill
127 // weights, coalesce virtual registers and remove identity moves.
128 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
130 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
131 mbbi != mbbe; ++mbbi) {
132 MachineBasicBlock* mbb = mbbi;
133 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
135 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
137 // if the move will be an identity move delete it
138 unsigned srcReg, dstReg, RegRep;
139 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
140 (RegRep = rep(srcReg)) == rep(dstReg)) {
141 // remove from def list
142 LiveInterval &RegInt = getOrCreateInterval(RegRep);
143 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
144 // If def of this move instruction is dead, remove its live range from
145 // the dstination register's live interval.
147 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
148 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
149 RegInt.removeRange(MLR->start, MoveIdx+1);
151 removeInterval(RegRep);
153 RemoveMachineInstrFromMaps(mii);
154 mii = mbbi->erase(mii);
158 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
159 const MachineOperand &mop = mii->getOperand(i);
160 if (mop.isRegister() && mop.getReg() &&
161 MRegisterInfo::isVirtualRegister(mop.getReg())) {
162 // replace register with representative register
163 unsigned reg = rep(mop.getReg());
164 mii->getOperand(i).setReg(reg);
166 LiveInterval &RegInt = getInterval(reg);
168 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
176 for (iterator I = begin(), E = end(); I != E; ++I) {
177 LiveInterval &LI = I->second;
178 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
179 // If the live interval length is essentially zero, i.e. in every live
180 // range the use follows def immediately, it doesn't make sense to spill
181 // it and hope it will be easier to allocate for this li.
182 if (isZeroLengthInterval(&LI))
183 LI.weight = HUGE_VALF;
185 // Divide the weight of the interval by its size. This encourages
186 // spilling of intervals that are large and have few uses, and
187 // discourages spilling of small intervals with many uses.
189 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II)
190 Size += II->end - II->start;
200 /// print - Implement the dump method.
201 void LiveIntervals::print(std::ostream &O, const Module* ) const {
202 O << "********** INTERVALS **********\n";
203 for (const_iterator I = begin(), E = end(); I != E; ++I) {
204 I->second.print(DOUT, mri_);
208 O << "********** MACHINEINSTRS **********\n";
209 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
210 mbbi != mbbe; ++mbbi) {
211 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
212 for (MachineBasicBlock::iterator mii = mbbi->begin(),
213 mie = mbbi->end(); mii != mie; ++mii) {
214 O << getInstructionIndex(mii) << '\t' << *mii;
219 /// CreateNewLiveInterval - Create a new live interval with the given live
220 /// ranges. The new live interval will have an infinite spill weight.
222 LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
223 const std::vector<LiveRange> &LRs) {
224 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
226 // Create a new virtual register for the spill interval.
227 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
229 // Replace the old virtual registers in the machine operands with the shiny
231 for (std::vector<LiveRange>::const_iterator
232 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
233 unsigned Index = getBaseIndex(I->start);
234 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
236 for (; Index != End; Index += InstrSlots::NUM) {
237 // Skip deleted instructions
238 while (Index != End && !getInstructionFromIndex(Index))
239 Index += InstrSlots::NUM;
241 if (Index == End) break;
243 MachineInstr *MI = getInstructionFromIndex(Index);
245 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
246 MachineOperand &MOp = MI->getOperand(J);
247 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg)
253 LiveInterval &NewLI = getOrCreateInterval(NewVReg);
255 // The spill weight is now infinity as it cannot be spilled again
256 NewLI.weight = float(HUGE_VAL);
258 for (std::vector<LiveRange>::const_iterator
259 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
260 DOUT << " Adding live range " << *I << " to new interval\n";
264 DOUT << "Created new live interval " << NewLI << "\n";
268 std::vector<LiveInterval*> LiveIntervals::
269 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
270 // since this is called after the analysis is done we don't know if
271 // LiveVariables is available
272 lv_ = getAnalysisToUpdate<LiveVariables>();
274 std::vector<LiveInterval*> added;
276 assert(li.weight != HUGE_VALF &&
277 "attempt to spill already spilled interval!");
279 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
280 li.print(DOUT, mri_);
283 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
285 for (LiveInterval::Ranges::const_iterator
286 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
287 unsigned index = getBaseIndex(i->start);
288 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
289 for (; index != end; index += InstrSlots::NUM) {
290 // skip deleted instructions
291 while (index != end && !getInstructionFromIndex(index))
292 index += InstrSlots::NUM;
293 if (index == end) break;
295 MachineInstr *MI = getInstructionFromIndex(index);
298 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
299 MachineOperand& mop = MI->getOperand(i);
300 if (mop.isRegister() && mop.getReg() == li.reg) {
301 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) {
302 // Attempt to fold the memory reference into the instruction. If we
303 // can do this, we don't need to insert spill code.
305 lv_->instructionChanged(MI, fmi);
306 MachineBasicBlock &MBB = *MI->getParent();
307 vrm.virtFolded(li.reg, MI, i, fmi);
309 i2miMap_[index/InstrSlots::NUM] = fmi;
310 mi2iMap_[fmi] = index;
311 MI = MBB.insert(MBB.erase(MI), fmi);
313 // Folding the load/store can completely change the instruction in
314 // unpredictable ways, rescan it from the beginning.
315 goto RestartInstruction;
317 // Create a new virtual register for the spill interval.
318 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
320 // Scan all of the operands of this instruction rewriting operands
321 // to use NewVReg instead of li.reg as appropriate. We do this for
324 // 1. If the instr reads the same spilled vreg multiple times, we
325 // want to reuse the NewVReg.
326 // 2. If the instr is a two-addr instruction, we are required to
327 // keep the src/dst regs pinned.
329 // Keep track of whether we replace a use and/or def so that we can
330 // create the spill interval with the appropriate range.
333 bool HasUse = mop.isUse();
334 bool HasDef = mop.isDef();
335 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
336 if (MI->getOperand(j).isReg() &&
337 MI->getOperand(j).getReg() == li.reg) {
338 MI->getOperand(j).setReg(NewVReg);
339 HasUse |= MI->getOperand(j).isUse();
340 HasDef |= MI->getOperand(j).isDef();
344 // create a new register for this spill
346 vrm.assignVirt2StackSlot(NewVReg, slot);
347 LiveInterval &nI = getOrCreateInterval(NewVReg);
350 // the spill weight is now infinity as it
351 // cannot be spilled again
352 nI.weight = HUGE_VALF;
355 LiveRange LR(getLoadIndex(index), getUseIndex(index),
356 nI.getNextValue(~0U, 0));
361 LiveRange LR(getDefIndex(index), getStoreIndex(index),
362 nI.getNextValue(~0U, 0));
367 added.push_back(&nI);
369 // update live variables if it is available
371 lv_->addVirtualRegisterKilled(NewVReg, MI);
373 DOUT << "\t\t\t\tadded new interval: ";
374 nI.print(DOUT, mri_);
385 void LiveIntervals::printRegName(unsigned reg) const {
386 if (MRegisterInfo::isPhysicalRegister(reg))
387 cerr << mri_->getName(reg);
389 cerr << "%reg" << reg;
392 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
393 /// two addr elimination.
394 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
395 const TargetInstrInfo *TII) {
396 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
397 MachineOperand &MO1 = MI->getOperand(i);
398 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
399 for (unsigned j = i+1; j < e; ++j) {
400 MachineOperand &MO2 = MI->getOperand(j);
401 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
402 MI->getInstrDescriptor()->
403 getOperandConstraint(j, TOI::TIED_TO) == (int)i)
411 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
412 MachineBasicBlock::iterator mi,
414 LiveInterval &interval) {
415 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
416 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
418 // Virtual registers may be defined multiple times (due to phi
419 // elimination and 2-addr elimination). Much of what we do only has to be
420 // done once for the vreg. We use an empty interval to detect the first
421 // time we see a vreg.
422 if (interval.empty()) {
423 // Get the Idx of the defining instructions.
424 unsigned defIndex = getDefIndex(MIIdx);
427 unsigned SrcReg, DstReg;
428 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
429 ValNum = interval.getNextValue(~0U, 0);
431 ValNum = interval.getNextValue(defIndex, SrcReg);
433 assert(ValNum == 0 && "First value in interval is not 0?");
434 ValNum = 0; // Clue in the optimizer.
436 // Loop over all of the blocks that the vreg is defined in. There are
437 // two cases we have to handle here. The most common case is a vreg
438 // whose lifetime is contained within a basic block. In this case there
439 // will be a single kill, in MBB, which comes after the definition.
440 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
441 // FIXME: what about dead vars?
443 if (vi.Kills[0] != mi)
444 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
446 killIdx = defIndex+1;
448 // If the kill happens after the definition, we have an intra-block
450 if (killIdx > defIndex) {
451 assert(vi.AliveBlocks.none() &&
452 "Shouldn't be alive across any blocks!");
453 LiveRange LR(defIndex, killIdx, ValNum);
454 interval.addRange(LR);
455 DOUT << " +" << LR << "\n";
460 // The other case we handle is when a virtual register lives to the end
461 // of the defining block, potentially live across some blocks, then is
462 // live into some number of blocks, but gets killed. Start by adding a
463 // range that goes from this definition to the end of the defining block.
464 LiveRange NewLR(defIndex,
465 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
467 DOUT << " +" << NewLR;
468 interval.addRange(NewLR);
470 // Iterate over all of the blocks that the variable is completely
471 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
473 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
474 if (vi.AliveBlocks[i]) {
475 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
477 LiveRange LR(getMBBStartIdx(i),
478 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
480 interval.addRange(LR);
486 // Finally, this virtual register is live from the start of any killing
487 // block to the 'use' slot of the killing instruction.
488 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
489 MachineInstr *Kill = vi.Kills[i];
490 LiveRange LR(getMBBStartIdx(Kill->getParent()),
491 getUseIndex(getInstructionIndex(Kill))+1,
493 interval.addRange(LR);
498 // If this is the second time we see a virtual register definition, it
499 // must be due to phi elimination or two addr elimination. If this is
500 // the result of two address elimination, then the vreg is one of the
501 // def-and-use register operand.
502 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
503 // If this is a two-address definition, then we have already processed
504 // the live range. The only problem is that we didn't realize there
505 // are actually two values in the live interval. Because of this we
506 // need to take the LiveRegion that defines this register and split it
508 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
509 unsigned RedefIndex = getDefIndex(MIIdx);
511 // Delete the initial value, which should be short and continuous,
512 // because the 2-addr copy must be in the same MBB as the redef.
513 interval.removeRange(DefIndex, RedefIndex);
515 // Two-address vregs should always only be redefined once. This means
516 // that at this point, there should be exactly one value number in it.
517 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
519 // The new value number (#1) is defined by the instruction we claimed
521 unsigned ValNo = interval.getNextValue(0, 0);
522 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
524 // Value#0 is now defined by the 2-addr instruction.
525 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
527 // Add the new live interval which replaces the range for the input copy.
528 LiveRange LR(DefIndex, RedefIndex, ValNo);
529 DOUT << " replace range with " << LR;
530 interval.addRange(LR);
532 // If this redefinition is dead, we need to add a dummy unit live
533 // range covering the def slot.
534 if (lv_->RegisterDefIsDead(mi, interval.reg))
535 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
538 interval.print(DOUT, mri_);
541 // Otherwise, this must be because of phi elimination. If this is the
542 // first redefinition of the vreg that we have seen, go back and change
543 // the live range in the PHI block to be a different value number.
544 if (interval.containsOneValue()) {
545 assert(vi.Kills.size() == 1 &&
546 "PHI elimination vreg should have one kill, the PHI itself!");
548 // Remove the old range that we now know has an incorrect number.
549 MachineInstr *Killer = vi.Kills[0];
550 unsigned Start = getMBBStartIdx(Killer->getParent());
551 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
552 DOUT << "Removing [" << Start << "," << End << "] from: ";
553 interval.print(DOUT, mri_); DOUT << "\n";
554 interval.removeRange(Start, End);
555 DOUT << "RESULT: "; interval.print(DOUT, mri_);
557 // Replace the interval with one of a NEW value number. Note that this
558 // value number isn't actually defined by an instruction, weird huh? :)
559 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
560 DOUT << " replace range with " << LR;
561 interval.addRange(LR);
562 DOUT << "RESULT: "; interval.print(DOUT, mri_);
565 // In the case of PHI elimination, each variable definition is only
566 // live until the end of the block. We've already taken care of the
567 // rest of the live range.
568 unsigned defIndex = getDefIndex(MIIdx);
571 unsigned SrcReg, DstReg;
572 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
573 ValNum = interval.getNextValue(~0U, 0);
575 ValNum = interval.getNextValue(defIndex, SrcReg);
577 LiveRange LR(defIndex,
578 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
579 interval.addRange(LR);
587 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
588 MachineBasicBlock::iterator mi,
590 LiveInterval &interval,
592 // A physical register cannot be live across basic block, so its
593 // lifetime must end somewhere in its defining basic block.
594 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
596 unsigned baseIndex = MIIdx;
597 unsigned start = getDefIndex(baseIndex);
598 unsigned end = start;
600 // If it is not used after definition, it is considered dead at
601 // the instruction defining it. Hence its interval is:
602 // [defSlot(def), defSlot(def)+1)
603 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
605 end = getDefIndex(start) + 1;
609 // If it is not dead on definition, it must be killed by a
610 // subsequent instruction. Hence its interval is:
611 // [defSlot(def), useSlot(kill)+1)
612 while (++mi != MBB->end()) {
613 baseIndex += InstrSlots::NUM;
614 if (lv_->KillsRegister(mi, interval.reg)) {
616 end = getUseIndex(baseIndex) + 1;
618 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
619 // Another instruction redefines the register before it is ever read.
620 // Then the register is essentially dead at the instruction that defines
621 // it. Hence its interval is:
622 // [defSlot(def), defSlot(def)+1)
624 end = getDefIndex(start) + 1;
629 // The only case we should have a dead physreg here without a killing or
630 // instruction where we know it's dead is if it is live-in to the function
632 assert(!SrcReg && "physreg was not killed in defining block!");
633 end = getDefIndex(start) + 1; // It's dead.
636 assert(start < end && "did not find end of interval?");
638 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
640 interval.addRange(LR);
641 DOUT << " +" << LR << '\n';
644 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
645 MachineBasicBlock::iterator MI,
648 if (MRegisterInfo::isVirtualRegister(reg))
649 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
650 else if (allocatableRegs_[reg]) {
651 unsigned SrcReg, DstReg;
652 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
654 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
655 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
656 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
660 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
661 LiveInterval &interval) {
662 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
664 // Look for kills, if it reaches a def before it's killed, then it shouldn't
665 // be considered a livein.
666 MachineBasicBlock::iterator mi = MBB->begin();
667 unsigned baseIndex = 0;
669 unsigned end = start;
670 while (mi != MBB->end()) {
671 if (lv_->KillsRegister(mi, interval.reg)) {
673 end = getUseIndex(baseIndex) + 1;
675 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
676 // Another instruction redefines the register before it is ever read.
677 // Then the register is essentially dead at the instruction that defines
678 // it. Hence its interval is:
679 // [defSlot(def), defSlot(def)+1)
681 end = getDefIndex(start) + 1;
685 baseIndex += InstrSlots::NUM;
690 assert(start < end && "did not find end of interval?");
692 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
693 interval.addRange(LR);
694 DOUT << " +" << LR << '\n';
697 /// computeIntervals - computes the live intervals for virtual
698 /// registers. for some ordering of the machine instructions [1,N] a
699 /// live interval is an interval [i, j) where 1 <= i <= j < N for
700 /// which a variable is live
701 void LiveIntervals::computeIntervals() {
702 DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
703 << "********** Function: "
704 << ((Value*)mf_->getFunction())->getName() << '\n';
705 // Track the index of the current machine instr.
706 unsigned MIIndex = 0;
707 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
709 MachineBasicBlock *MBB = MBBI;
710 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
712 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
714 if (MBB->livein_begin() != MBB->livein_end()) {
715 // Create intervals for live-ins to this BB first.
716 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
717 LE = MBB->livein_end(); LI != LE; ++LI) {
718 handleLiveInRegister(MBB, getOrCreateInterval(*LI));
719 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
720 handleLiveInRegister(MBB, getOrCreateInterval(*AS));
724 for (; MI != miEnd; ++MI) {
725 DOUT << MIIndex << "\t" << *MI;
728 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
729 MachineOperand &MO = MI->getOperand(i);
730 // handle register defs - build intervals
731 if (MO.isRegister() && MO.getReg() && MO.isDef())
732 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
735 MIIndex += InstrSlots::NUM;
740 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
741 /// being the source and IntB being the dest, thus this defines a value number
742 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
743 /// see if we can merge these two pieces of B into a single value number,
744 /// eliminating a copy. For example:
748 /// B1 = A3 <- this copy
750 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
751 /// value number to be replaced with B0 (which simplifies the B liveinterval).
753 /// This returns true if an interval was modified.
755 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
756 MachineInstr *CopyMI) {
757 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
759 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
760 // the example above.
761 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
762 unsigned BValNo = BLR->ValId;
764 // Get the location that B is defined at. Two options: either this value has
765 // an unknown definition point or it is defined at CopyIdx. If unknown, we
767 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
768 if (BValNoDefIdx == ~0U) return false;
769 assert(BValNoDefIdx == CopyIdx &&
770 "Copy doesn't define the value?");
772 // AValNo is the value number in A that defines the copy, A0 in the example.
773 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
774 unsigned AValNo = AValLR->ValId;
776 // If AValNo is defined as a copy from IntB, we can potentially process this.
778 // Get the instruction that defines this value number.
779 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
780 if (!SrcReg) return false; // Not defined by a copy.
782 // If the value number is not defined by a copy instruction, ignore it.
784 // If the source register comes from an interval other than IntB, we can't
786 if (rep(SrcReg) != IntB.reg) return false;
788 // Get the LiveRange in IntB that this value number starts with.
789 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
790 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
792 // Make sure that the end of the live range is inside the same block as
794 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
796 ValLREndInst->getParent() != CopyMI->getParent()) return false;
798 // Okay, we now know that ValLR ends in the same block that the CopyMI
799 // live-range starts. If there are no intervening live ranges between them in
800 // IntB, we can merge them.
801 if (ValLR+1 != BLR) return false;
803 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
805 // We are about to delete CopyMI, so need to remove it as the 'instruction
806 // that defines this value #'.
807 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
809 // Okay, we can merge them. We need to insert a new liverange:
810 // [ValLR.end, BLR.begin) of either value number, then we merge the
811 // two value numbers.
812 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
813 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
815 // If the IntB live range is assigned to a physical register, and if that
816 // physreg has aliases,
817 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
818 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
819 LiveInterval &AliasLI = getInterval(*AS);
820 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
821 AliasLI.getNextValue(~0U, 0)));
825 // Okay, merge "B1" into the same value number as "B0".
826 if (BValNo != ValLR->ValId)
827 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
828 DOUT << " result = "; IntB.print(DOUT, mri_);
831 // Finally, delete the copy instruction.
832 RemoveMachineInstrFromMaps(CopyMI);
833 CopyMI->eraseFromParent();
838 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
839 /// which are the src/dst of the copy instruction CopyMI. This returns true
840 /// if the copy was successfully coallesced away, or if it is never possible
841 /// to coallesce these this copy, due to register constraints. It returns
842 /// false if it is not currently possible to coallesce this interval, but
843 /// it may be possible if other things get coallesced.
844 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
845 unsigned SrcReg, unsigned DstReg) {
846 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
848 // Get representative registers.
849 unsigned repSrcReg = rep(SrcReg);
850 unsigned repDstReg = rep(DstReg);
852 // If they are already joined we continue.
853 if (repSrcReg == repDstReg) {
854 DOUT << "\tCopy already coallesced.\n";
855 return true; // Not coallescable.
858 // If they are both physical registers, we cannot join them.
859 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
860 MRegisterInfo::isPhysicalRegister(repDstReg)) {
861 DOUT << "\tCan not coallesce physregs.\n";
862 return true; // Not coallescable.
865 // We only join virtual registers with allocatable physical registers.
866 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
867 !allocatableRegs_[repSrcReg]) {
868 DOUT << "\tSrc reg is unallocatable physreg.\n";
869 return true; // Not coallescable.
871 if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
872 !allocatableRegs_[repDstReg]) {
873 DOUT << "\tDst reg is unallocatable physreg.\n";
874 return true; // Not coallescable.
877 // If they are not of the same register class, we cannot join them.
878 if (differingRegisterClasses(repSrcReg, repDstReg)) {
879 DOUT << "\tSrc/Dest are different register classes.\n";
880 return true; // Not coallescable.
883 LiveInterval &SrcInt = getInterval(repSrcReg);
884 LiveInterval &DestInt = getInterval(repDstReg);
885 assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
886 "Register mapping is horribly broken!");
888 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
889 DOUT << " and "; DestInt.print(DOUT, mri_);
892 // Check if it is necessary to propagate "isDead" property before intervals
894 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
895 bool isDead = mopd->isDead();
896 unsigned SrcStart = 0;
899 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
900 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
901 SrcStart = SrcLR->start;
903 if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
907 // Okay, attempt to join these two intervals. On failure, this returns false.
908 // Otherwise, if one of the intervals being joined is a physreg, this method
909 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
910 // been modified, so we can use this information below to update aliases.
911 if (JoinIntervals(DestInt, SrcInt)) {
913 // Result of the copy is dead. Propagate this property.
915 // Live-in to the function but dead. Remove it from MBB live-in set.
916 // JoinIntervals may end up swapping the two intervals.
917 LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
918 LiveInInt.removeRange(SrcStart, SrcEnd);
919 MachineBasicBlock *MBB = CopyMI->getParent();
920 MBB->removeLiveIn(SrcReg);
922 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
924 // FIXME: SrcMI == NULL means the register is livein to a non-entry
925 // MBB. Remove the range from its live interval?
926 MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
928 // FIXME: mops == NULL means SrcMI defines a subregister?
934 // Coallescing failed.
936 // If we can eliminate the copy without merging the live ranges, do so now.
937 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
940 // Otherwise, we are unable to join the intervals.
941 DOUT << "Interference!\n";
945 bool Swapped = repSrcReg == DestInt.reg;
947 std::swap(repSrcReg, repDstReg);
948 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
949 "LiveInterval::join didn't work right!");
951 // If we're about to merge live ranges into a physical register live range,
952 // we have to update any aliased register's live ranges to indicate that they
953 // have clobbered values for this range.
954 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
955 for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
956 getInterval(*AS).MergeInClobberRanges(SrcInt);
959 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_);
962 // If the intervals were swapped by Join, swap them back so that the register
963 // mapping (in the r2i map) is correct.
964 if (Swapped) SrcInt.swap(DestInt);
965 removeInterval(repSrcReg);
966 r2rMap_[repSrcReg] = repDstReg;
968 // Finally, delete the copy instruction.
969 RemoveMachineInstrFromMaps(CopyMI);
970 CopyMI->eraseFromParent();
976 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
977 /// compute what the resultant value numbers for each value in the input two
978 /// ranges will be. This is complicated by copies between the two which can
979 /// and will commonly cause multiple value numbers to be merged into one.
981 /// VN is the value number that we're trying to resolve. InstDefiningValue
982 /// keeps track of the new InstDefiningValue assignment for the result
983 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
984 /// whether a value in this or other is a copy from the opposite set.
985 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
986 /// already been assigned.
988 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
989 /// contains the value number the copy is from.
991 static unsigned ComputeUltimateVN(unsigned VN,
992 SmallVector<std::pair<unsigned,
993 unsigned>, 16> &ValueNumberInfo,
994 SmallVector<int, 16> &ThisFromOther,
995 SmallVector<int, 16> &OtherFromThis,
996 SmallVector<int, 16> &ThisValNoAssignments,
997 SmallVector<int, 16> &OtherValNoAssignments,
998 LiveInterval &ThisLI, LiveInterval &OtherLI) {
999 // If the VN has already been computed, just return it.
1000 if (ThisValNoAssignments[VN] >= 0)
1001 return ThisValNoAssignments[VN];
1002 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1004 // If this val is not a copy from the other val, then it must be a new value
1005 // number in the destination.
1006 int OtherValNo = ThisFromOther[VN];
1007 if (OtherValNo == -1) {
1008 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
1009 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
1012 // Otherwise, this *is* a copy from the RHS. If the other side has already
1013 // been computed, return it.
1014 if (OtherValNoAssignments[OtherValNo] >= 0)
1015 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
1017 // Mark this value number as currently being computed, then ask what the
1018 // ultimate value # of the other value is.
1019 ThisValNoAssignments[VN] = -2;
1020 unsigned UltimateVN =
1021 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
1022 OtherFromThis, ThisFromOther,
1023 OtherValNoAssignments, ThisValNoAssignments,
1025 return ThisValNoAssignments[VN] = UltimateVN;
1028 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
1029 return std::find(V.begin(), V.end(), Val) != V.end();
1032 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1033 /// caller of this method must guarantee that the RHS only contains a single
1034 /// value number and that the RHS is not defined by a copy from this
1035 /// interval. This returns false if the intervals are not joinable, or it
1036 /// joins them and returns true.
1037 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
1038 assert(RHS.containsOneValue());
1040 // Some number (potentially more than one) value numbers in the current
1041 // interval may be defined as copies from the RHS. Scan the overlapping
1042 // portions of the LHS and RHS, keeping track of this and looking for
1043 // overlapping live ranges that are NOT defined as copies. If these exist, we
1044 // cannot coallesce.
1046 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1047 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1049 if (LHSIt->start < RHSIt->start) {
1050 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1051 if (LHSIt != LHS.begin()) --LHSIt;
1052 } else if (RHSIt->start < LHSIt->start) {
1053 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1054 if (RHSIt != RHS.begin()) --RHSIt;
1057 SmallVector<unsigned, 8> EliminatedLHSVals;
1060 // Determine if these live intervals overlap.
1061 bool Overlaps = false;
1062 if (LHSIt->start <= RHSIt->start)
1063 Overlaps = LHSIt->end > RHSIt->start;
1065 Overlaps = RHSIt->end > LHSIt->start;
1067 // If the live intervals overlap, there are two interesting cases: if the
1068 // LHS interval is defined by a copy from the RHS, it's ok and we record
1069 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1070 // coallesce these live ranges and we bail out.
1072 // If we haven't already recorded that this value # is safe, check it.
1073 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
1074 // Copy from the RHS?
1075 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
1076 if (rep(SrcReg) != RHS.reg)
1077 return false; // Nope, bail out.
1079 EliminatedLHSVals.push_back(LHSIt->ValId);
1082 // We know this entire LHS live range is okay, so skip it now.
1083 if (++LHSIt == LHSEnd) break;
1087 if (LHSIt->end < RHSIt->end) {
1088 if (++LHSIt == LHSEnd) break;
1090 // One interesting case to check here. It's possible that we have
1091 // something like "X3 = Y" which defines a new value number in the LHS,
1092 // and is the last use of this liverange of the RHS. In this case, we
1093 // want to notice this copy (so that it gets coallesced away) even though
1094 // the live ranges don't actually overlap.
1095 if (LHSIt->start == RHSIt->end) {
1096 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
1097 // We already know that this value number is going to be merged in
1098 // if coallescing succeeds. Just skip the liverange.
1099 if (++LHSIt == LHSEnd) break;
1101 // Otherwise, if this is a copy from the RHS, mark it as being merged
1103 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
1104 EliminatedLHSVals.push_back(LHSIt->ValId);
1106 // We know this entire LHS live range is okay, so skip it now.
1107 if (++LHSIt == LHSEnd) break;
1112 if (++RHSIt == RHSEnd) break;
1116 // If we got here, we know that the coallescing will be successful and that
1117 // the value numbers in EliminatedLHSVals will all be merged together. Since
1118 // the most common case is that EliminatedLHSVals has a single number, we
1119 // optimize for it: if there is more than one value, we merge them all into
1120 // the lowest numbered one, then handle the interval as if we were merging
1121 // with one value number.
1123 if (EliminatedLHSVals.size() > 1) {
1124 // Loop through all the equal value numbers merging them into the smallest
1126 unsigned Smallest = EliminatedLHSVals[0];
1127 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1128 if (EliminatedLHSVals[i] < Smallest) {
1129 // Merge the current notion of the smallest into the smaller one.
1130 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1131 Smallest = EliminatedLHSVals[i];
1133 // Merge into the smallest.
1134 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1137 LHSValNo = Smallest;
1139 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1140 LHSValNo = EliminatedLHSVals[0];
1143 // Okay, now that there is a single LHS value number that we're merging the
1144 // RHS into, update the value number info for the LHS to indicate that the
1145 // value number is defined where the RHS value number was.
1146 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1148 // Okay, the final step is to loop over the RHS live intervals, adding them to
1150 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1151 LHS.weight += RHS.weight;
1156 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1157 /// returns false. Otherwise, if one of the intervals being joined is a
1158 /// physreg, this method always canonicalizes LHS to be it. The output
1159 /// "RHS" will not have been modified, so we can use this information
1160 /// below to update aliases.
1161 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1162 // Compute the final value assignment, assuming that the live ranges can be
1164 SmallVector<int, 16> LHSValNoAssignments;
1165 SmallVector<int, 16> RHSValNoAssignments;
1166 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1168 // Compute ultimate value numbers for the LHS and RHS values.
1169 if (RHS.containsOneValue()) {
1170 // Copies from a liveinterval with a single value are simple to handle and
1171 // very common, handle the special case here. This is important, because
1172 // often RHS is small and LHS is large (e.g. a physreg).
1174 // Find out if the RHS is defined as a copy from some value in the LHS.
1176 std::pair<unsigned,unsigned> RHSValNoInfo;
1177 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1178 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1179 // If RHS is not defined as a copy from the LHS, we can use simpler and
1180 // faster checks to see if the live ranges are coallescable. This joiner
1181 // can't swap the LHS/RHS intervals though.
1182 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1183 return SimpleJoin(LHS, RHS);
1185 RHSValNoInfo = RHS.getValNumInfo(0);
1188 // It was defined as a copy from the LHS, find out what value # it is.
1189 unsigned ValInst = RHS.getInstForValNum(0);
1190 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1191 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1194 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1195 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1196 ValueNumberInfo.resize(LHS.getNumValNums());
1198 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1199 // should now get updated.
1200 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1201 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1202 if (rep(LHSSrcReg) != RHS.reg) {
1203 // If this is not a copy from the RHS, its value number will be
1204 // unmodified by the coallescing.
1205 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1206 LHSValNoAssignments[VN] = VN;
1207 } else if (RHSValID == -1) {
1208 // Otherwise, it is a copy from the RHS, and we don't already have a
1209 // value# for it. Keep the current value number, but remember it.
1210 LHSValNoAssignments[VN] = RHSValID = VN;
1211 ValueNumberInfo[VN] = RHSValNoInfo;
1213 // Otherwise, use the specified value #.
1214 LHSValNoAssignments[VN] = RHSValID;
1215 if (VN != (unsigned)RHSValID)
1216 ValueNumberInfo[VN].first = ~1U;
1218 ValueNumberInfo[VN] = RHSValNoInfo;
1221 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1222 LHSValNoAssignments[VN] = VN;
1226 assert(RHSValID != -1 && "Didn't find value #?");
1227 RHSValNoAssignments[0] = RHSValID;
1230 // Loop over the value numbers of the LHS, seeing if any are defined from
1232 SmallVector<int, 16> LHSValsDefinedFromRHS;
1233 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1234 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1235 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1236 if (ValSrcReg == 0) // Src not defined by a copy?
1239 // DstReg is known to be a register in the LHS interval. If the src is
1240 // from the RHS interval, we can use its value #.
1241 if (rep(ValSrcReg) != RHS.reg)
1244 // Figure out the value # from the RHS.
1245 unsigned ValInst = LHS.getInstForValNum(VN);
1246 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1249 // Loop over the value numbers of the RHS, seeing if any are defined from
1251 SmallVector<int, 16> RHSValsDefinedFromLHS;
1252 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1253 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1254 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1255 if (ValSrcReg == 0) // Src not defined by a copy?
1258 // DstReg is known to be a register in the RHS interval. If the src is
1259 // from the LHS interval, we can use its value #.
1260 if (rep(ValSrcReg) != LHS.reg)
1263 // Figure out the value # from the LHS.
1264 unsigned ValInst = RHS.getInstForValNum(VN);
1265 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1268 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1269 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1270 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1272 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1273 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1275 ComputeUltimateVN(VN, ValueNumberInfo,
1276 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1277 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1279 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1280 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1282 // If this value number isn't a copy from the LHS, it's a new number.
1283 if (RHSValsDefinedFromLHS[VN] == -1) {
1284 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1285 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1289 ComputeUltimateVN(VN, ValueNumberInfo,
1290 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1291 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1295 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1296 // interval lists to see if these intervals are coallescable.
1297 LiveInterval::const_iterator I = LHS.begin();
1298 LiveInterval::const_iterator IE = LHS.end();
1299 LiveInterval::const_iterator J = RHS.begin();
1300 LiveInterval::const_iterator JE = RHS.end();
1302 // Skip ahead until the first place of potential sharing.
1303 if (I->start < J->start) {
1304 I = std::upper_bound(I, IE, J->start);
1305 if (I != LHS.begin()) --I;
1306 } else if (J->start < I->start) {
1307 J = std::upper_bound(J, JE, I->start);
1308 if (J != RHS.begin()) --J;
1312 // Determine if these two live ranges overlap.
1314 if (I->start < J->start) {
1315 Overlaps = I->end > J->start;
1317 Overlaps = J->end > I->start;
1320 // If so, check value # info to determine if they are really different.
1322 // If the live range overlap will map to the same value number in the
1323 // result liverange, we can still coallesce them. If not, we can't.
1324 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1328 if (I->end < J->end) {
1337 // If we get here, we know that we can coallesce the live ranges. Ask the
1338 // intervals to coallesce themselves now.
1339 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1346 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1347 // depth of the basic block (the unsigned), and then on the MBB number.
1348 struct DepthMBBCompare {
1349 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1350 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1351 if (LHS.first > RHS.first) return true; // Deeper loops first
1352 return LHS.first == RHS.first &&
1353 LHS.second->getNumber() < RHS.second->getNumber();
1359 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1360 std::vector<CopyRec> &TryAgain) {
1361 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1363 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1365 MachineInstr *Inst = MII++;
1367 // If this isn't a copy, we can't join intervals.
1368 unsigned SrcReg, DstReg;
1369 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1371 if (!JoinCopy(Inst, SrcReg, DstReg))
1372 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
1377 void LiveIntervals::joinIntervals() {
1378 DOUT << "********** JOINING INTERVALS ***********\n";
1380 std::vector<CopyRec> TryAgainList;
1382 const LoopInfo &LI = getAnalysis<LoopInfo>();
1383 if (LI.begin() == LI.end()) {
1384 // If there are no loops in the function, join intervals in function order.
1385 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1387 CopyCoallesceInMBB(I, TryAgainList);
1389 // Otherwise, join intervals in inner loops before other intervals.
1390 // Unfortunately we can't just iterate over loop hierarchy here because
1391 // there may be more MBB's than BB's. Collect MBB's for sorting.
1392 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1393 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1395 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1397 // Sort by loop depth.
1398 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1400 // Finally, join intervals in loop nest order.
1401 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1402 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
1405 // Joining intervals can allow other intervals to be joined. Iteratively join
1406 // until we make no progress.
1407 bool ProgressMade = true;
1408 while (ProgressMade) {
1409 ProgressMade = false;
1411 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1412 CopyRec &TheCopy = TryAgainList[i];
1414 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1415 TheCopy.MI = 0; // Mark this one as done.
1416 ProgressMade = true;
1421 DOUT << "*** Register mapping ***\n";
1422 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1424 DOUT << " reg " << i << " -> ";
1425 DEBUG(printRegName(r2rMap_[i]));
1430 /// Return true if the two specified registers belong to different register
1431 /// classes. The registers may be either phys or virt regs.
1432 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1433 unsigned RegB) const {
1435 // Get the register classes for the first reg.
1436 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1437 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1438 "Shouldn't consider two physregs!");
1439 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1442 // Compare against the regclass for the second reg.
1443 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1444 if (MRegisterInfo::isVirtualRegister(RegB))
1445 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1447 return !RegClass->contains(RegB);
1450 /// hasRegisterUse - Returns true if there is any use of the specific
1451 /// reg between indexes Start and End.
1453 LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
1454 for (unsigned Index = Start+InstrSlots::NUM; Index < End;
1455 Index += InstrSlots::NUM) {
1456 // Skip deleted instructions
1457 while (Index < End && !getInstructionFromIndex(Index))
1458 Index += InstrSlots::NUM;
1459 if (Index >= End) break;
1461 MachineInstr *MI = getInstructionFromIndex(Index);
1462 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1463 MachineOperand &MO = MI->getOperand(i);
1464 if (MO.isReg() && MO.isUse() && MO.getReg() &&
1465 mri_->regsOverlap(rep(MO.getReg()), Reg))
1473 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1474 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1476 return LiveInterval(reg, Weight);