1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
41 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
43 static Statistic<> numIntervals
44 ("liveintervals", "Number of original intervals");
46 static Statistic<> numIntervalsAfter
47 ("liveintervals", "Number of intervals after coalescing");
49 static Statistic<> numJoins
50 ("liveintervals", "Number of interval joins performed");
52 static Statistic<> numPeep
53 ("liveintervals", "Number of identity moves eliminated after coalescing");
55 static Statistic<> numFolded
56 ("liveintervals", "Number of loads/stores folded into instructions");
59 EnableJoining("join-liveintervals",
60 cl::desc("Coallesce copies (default=true)"),
63 EnableReweight("enable-majik-f00");
67 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<LiveVariables>();
69 AU.addPreservedID(PHIEliminationID);
70 AU.addRequiredID(PHIEliminationID);
71 AU.addRequiredID(TwoAddressInstructionPassID);
72 AU.addRequired<LoopInfo>();
73 MachineFunctionPass::getAnalysisUsage(AU);
76 void LiveIntervals::releaseMemory() {
84 static bool isZeroLengthInterval(LiveInterval *li) {
85 for (LiveInterval::Ranges::const_iterator
86 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
87 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
93 /// runOnMachineFunction - Register allocate the whole function
95 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
97 tm_ = &fn.getTarget();
98 mri_ = tm_->getRegisterInfo();
99 tii_ = tm_->getInstrInfo();
100 lv_ = &getAnalysis<LiveVariables>();
101 allocatableRegs_ = mri_->getAllocatableSet(fn);
102 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
104 // If this function has any live ins, insert a dummy instruction at the
105 // beginning of the function that we will pretend "defines" the values. This
106 // is to make the interval analysis simpler by providing a number.
107 if (fn.livein_begin() != fn.livein_end()) {
108 unsigned FirstLiveIn = fn.livein_begin()->first;
110 // Find a reg class that contains this live in.
111 const TargetRegisterClass *RC = 0;
112 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
113 E = mri_->regclass_end(); RCI != E; ++RCI)
114 if ((*RCI)->contains(FirstLiveIn)) {
119 MachineInstr *OldFirstMI = fn.begin()->begin();
120 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
121 FirstLiveIn, FirstLiveIn, RC);
122 assert(OldFirstMI != fn.begin()->begin() &&
123 "copyRetToReg didn't insert anything!");
126 // Number MachineInstrs and MachineBasicBlocks.
127 // Initialize MBB indexes to a sentinal.
128 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
130 unsigned MIIndex = 0;
131 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
133 // Set the MBB2IdxMap entry for this MBB.
134 MBB2IdxMap[MBB->getNumber()] = MIIndex;
136 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
138 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
139 assert(inserted && "multiple MachineInstr -> index mappings");
140 i2miMap_.push_back(I);
141 MIIndex += InstrSlots::NUM;
145 // Note intervals due to live-in values.
146 if (fn.livein_begin() != fn.livein_end()) {
147 MachineBasicBlock *Entry = fn.begin();
148 for (MachineFunction::livein_iterator I = fn.livein_begin(),
149 E = fn.livein_end(); I != E; ++I) {
150 handlePhysicalRegisterDef(Entry, Entry->begin(), 0,
151 getOrCreateInterval(I->first), 0);
152 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
153 handlePhysicalRegisterDef(Entry, Entry->begin(), 0,
154 getOrCreateInterval(*AS), 0);
160 numIntervals += getNumIntervals();
162 DEBUG(std::cerr << "********** INTERVALS **********\n";
163 for (iterator I = begin(), E = end(); I != E; ++I) {
164 I->second.print(std::cerr, mri_);
168 // Join (coallesce) intervals if requested.
169 if (EnableJoining) joinIntervals();
171 numIntervalsAfter += getNumIntervals();
174 // perform a final pass over the instructions and compute spill
175 // weights, coalesce virtual registers and remove identity moves.
176 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
178 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
179 mbbi != mbbe; ++mbbi) {
180 MachineBasicBlock* mbb = mbbi;
181 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
183 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
185 // if the move will be an identity move delete it
186 unsigned srcReg, dstReg, RegRep;
187 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
188 (RegRep = rep(srcReg)) == rep(dstReg)) {
189 // remove from def list
190 getOrCreateInterval(RegRep);
191 RemoveMachineInstrFromMaps(mii);
192 mii = mbbi->erase(mii);
196 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
197 const MachineOperand &mop = mii->getOperand(i);
198 if (mop.isRegister() && mop.getReg() &&
199 MRegisterInfo::isVirtualRegister(mop.getReg())) {
200 // replace register with representative register
201 unsigned reg = rep(mop.getReg());
202 mii->getOperand(i).setReg(reg);
204 LiveInterval &RegInt = getInterval(reg);
206 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
215 for (iterator I = begin(), E = end(); I != E; ++I) {
216 LiveInterval &LI = I->second;
217 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
218 // If the live interval length is essentially zero, i.e. in every live
219 // range the use follows def immediately, it doesn't make sense to spill
220 // it and hope it will be easier to allocate for this li.
221 if (isZeroLengthInterval(&LI))
222 LI.weight = HUGE_VALF;
224 if (EnableReweight) {
225 // Divide the weight of the interval by its size. This encourages
226 // spilling of intervals that are large and have few uses, and
227 // discourages spilling of small intervals with many uses.
229 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II)
230 Size += II->end - II->start;
241 /// print - Implement the dump method.
242 void LiveIntervals::print(std::ostream &O, const Module* ) const {
243 O << "********** INTERVALS **********\n";
244 for (const_iterator I = begin(), E = end(); I != E; ++I) {
245 I->second.print(std::cerr, mri_);
249 O << "********** MACHINEINSTRS **********\n";
250 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
251 mbbi != mbbe; ++mbbi) {
252 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
253 for (MachineBasicBlock::iterator mii = mbbi->begin(),
254 mie = mbbi->end(); mii != mie; ++mii) {
255 O << getInstructionIndex(mii) << '\t' << *mii;
260 std::vector<LiveInterval*> LiveIntervals::
261 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
262 // since this is called after the analysis is done we don't know if
263 // LiveVariables is available
264 lv_ = getAnalysisToUpdate<LiveVariables>();
266 std::vector<LiveInterval*> added;
268 assert(li.weight != HUGE_VALF &&
269 "attempt to spill already spilled interval!");
271 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: ";
272 li.print(std::cerr, mri_); std::cerr << '\n');
274 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
276 for (LiveInterval::Ranges::const_iterator
277 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
278 unsigned index = getBaseIndex(i->start);
279 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
280 for (; index != end; index += InstrSlots::NUM) {
281 // skip deleted instructions
282 while (index != end && !getInstructionFromIndex(index))
283 index += InstrSlots::NUM;
284 if (index == end) break;
286 MachineInstr *MI = getInstructionFromIndex(index);
289 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
290 MachineOperand& mop = MI->getOperand(i);
291 if (mop.isRegister() && mop.getReg() == li.reg) {
292 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) {
293 // Attempt to fold the memory reference into the instruction. If we
294 // can do this, we don't need to insert spill code.
296 lv_->instructionChanged(MI, fmi);
297 MachineBasicBlock &MBB = *MI->getParent();
298 vrm.virtFolded(li.reg, MI, i, fmi);
300 i2miMap_[index/InstrSlots::NUM] = fmi;
301 mi2iMap_[fmi] = index;
302 MI = MBB.insert(MBB.erase(MI), fmi);
304 // Folding the load/store can completely change the instruction in
305 // unpredictable ways, rescan it from the beginning.
306 goto RestartInstruction;
308 // Create a new virtual register for the spill interval.
309 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
311 // Scan all of the operands of this instruction rewriting operands
312 // to use NewVReg instead of li.reg as appropriate. We do this for
315 // 1. If the instr reads the same spilled vreg multiple times, we
316 // want to reuse the NewVReg.
317 // 2. If the instr is a two-addr instruction, we are required to
318 // keep the src/dst regs pinned.
320 // Keep track of whether we replace a use and/or def so that we can
321 // create the spill interval with the appropriate range.
324 bool HasUse = mop.isUse();
325 bool HasDef = mop.isDef();
326 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
327 if (MI->getOperand(j).isReg() &&
328 MI->getOperand(j).getReg() == li.reg) {
329 MI->getOperand(j).setReg(NewVReg);
330 HasUse |= MI->getOperand(j).isUse();
331 HasDef |= MI->getOperand(j).isDef();
335 // create a new register for this spill
337 vrm.assignVirt2StackSlot(NewVReg, slot);
338 LiveInterval &nI = getOrCreateInterval(NewVReg);
341 // the spill weight is now infinity as it
342 // cannot be spilled again
343 nI.weight = HUGE_VALF;
346 LiveRange LR(getLoadIndex(index), getUseIndex(index),
347 nI.getNextValue(~0U, 0));
348 DEBUG(std::cerr << " +" << LR);
352 LiveRange LR(getDefIndex(index), getStoreIndex(index),
353 nI.getNextValue(~0U, 0));
354 DEBUG(std::cerr << " +" << LR);
358 added.push_back(&nI);
360 // update live variables if it is available
362 lv_->addVirtualRegisterKilled(NewVReg, MI);
364 DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
365 nI.print(std::cerr, mri_); std::cerr << '\n');
375 void LiveIntervals::printRegName(unsigned reg) const {
376 if (MRegisterInfo::isPhysicalRegister(reg))
377 std::cerr << mri_->getName(reg);
379 std::cerr << "%reg" << reg;
382 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
383 /// two addr elimination.
384 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
385 const TargetInstrInfo *TII) {
386 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
387 MachineOperand &MO1 = MI->getOperand(i);
388 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
389 for (unsigned j = i+1; j < e; ++j) {
390 MachineOperand &MO2 = MI->getOperand(j);
391 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
392 TII->getOperandConstraint(MI->getOpcode(), j,
393 TargetInstrInfo::TIED_TO) == (int)i)
401 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
402 MachineBasicBlock::iterator mi,
404 LiveInterval &interval) {
405 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
406 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
408 // Virtual registers may be defined multiple times (due to phi
409 // elimination and 2-addr elimination). Much of what we do only has to be
410 // done once for the vreg. We use an empty interval to detect the first
411 // time we see a vreg.
412 if (interval.empty()) {
413 // Get the Idx of the defining instructions.
414 unsigned defIndex = getDefIndex(MIIdx);
417 unsigned SrcReg, DstReg;
418 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
419 ValNum = interval.getNextValue(~0U, 0);
421 ValNum = interval.getNextValue(defIndex, SrcReg);
423 assert(ValNum == 0 && "First value in interval is not 0?");
424 ValNum = 0; // Clue in the optimizer.
426 // Loop over all of the blocks that the vreg is defined in. There are
427 // two cases we have to handle here. The most common case is a vreg
428 // whose lifetime is contained within a basic block. In this case there
429 // will be a single kill, in MBB, which comes after the definition.
430 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
431 // FIXME: what about dead vars?
433 if (vi.Kills[0] != mi)
434 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
436 killIdx = defIndex+1;
438 // If the kill happens after the definition, we have an intra-block
440 if (killIdx > defIndex) {
441 assert(vi.AliveBlocks.empty() &&
442 "Shouldn't be alive across any blocks!");
443 LiveRange LR(defIndex, killIdx, ValNum);
444 interval.addRange(LR);
445 DEBUG(std::cerr << " +" << LR << "\n");
450 // The other case we handle is when a virtual register lives to the end
451 // of the defining block, potentially live across some blocks, then is
452 // live into some number of blocks, but gets killed. Start by adding a
453 // range that goes from this definition to the end of the defining block.
454 LiveRange NewLR(defIndex,
455 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
457 DEBUG(std::cerr << " +" << NewLR);
458 interval.addRange(NewLR);
460 // Iterate over all of the blocks that the variable is completely
461 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
463 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
464 if (vi.AliveBlocks[i]) {
465 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
467 LiveRange LR(getMBBStartIdx(i),
468 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
470 interval.addRange(LR);
471 DEBUG(std::cerr << " +" << LR);
476 // Finally, this virtual register is live from the start of any killing
477 // block to the 'use' slot of the killing instruction.
478 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
479 MachineInstr *Kill = vi.Kills[i];
480 LiveRange LR(getMBBStartIdx(Kill->getParent()),
481 getUseIndex(getInstructionIndex(Kill))+1,
483 interval.addRange(LR);
484 DEBUG(std::cerr << " +" << LR);
488 // If this is the second time we see a virtual register definition, it
489 // must be due to phi elimination or two addr elimination. If this is
490 // the result of two address elimination, then the vreg is one of the
491 // def-and-use register operand.
492 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
493 // If this is a two-address definition, then we have already processed
494 // the live range. The only problem is that we didn't realize there
495 // are actually two values in the live interval. Because of this we
496 // need to take the LiveRegion that defines this register and split it
498 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
499 unsigned RedefIndex = getDefIndex(MIIdx);
501 // Delete the initial value, which should be short and continuous,
502 // because the 2-addr copy must be in the same MBB as the redef.
503 interval.removeRange(DefIndex, RedefIndex);
505 // Two-address vregs should always only be redefined once. This means
506 // that at this point, there should be exactly one value number in it.
507 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
509 // The new value number (#1) is defined by the instruction we claimed
511 unsigned ValNo = interval.getNextValue(0, 0);
512 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
514 // Value#0 is now defined by the 2-addr instruction.
515 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
517 // Add the new live interval which replaces the range for the input copy.
518 LiveRange LR(DefIndex, RedefIndex, ValNo);
519 DEBUG(std::cerr << " replace range with " << LR);
520 interval.addRange(LR);
522 // If this redefinition is dead, we need to add a dummy unit live
523 // range covering the def slot.
524 if (lv_->RegisterDefIsDead(mi, interval.reg))
525 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
527 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
530 // Otherwise, this must be because of phi elimination. If this is the
531 // first redefinition of the vreg that we have seen, go back and change
532 // the live range in the PHI block to be a different value number.
533 if (interval.containsOneValue()) {
534 assert(vi.Kills.size() == 1 &&
535 "PHI elimination vreg should have one kill, the PHI itself!");
537 // Remove the old range that we now know has an incorrect number.
538 MachineInstr *Killer = vi.Kills[0];
539 unsigned Start = getMBBStartIdx(Killer->getParent());
540 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
541 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: ";
542 interval.print(std::cerr, mri_); std::cerr << "\n");
543 interval.removeRange(Start, End);
544 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
546 // Replace the interval with one of a NEW value number. Note that this
547 // value number isn't actually defined by an instruction, weird huh? :)
548 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
549 DEBUG(std::cerr << " replace range with " << LR);
550 interval.addRange(LR);
551 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
554 // In the case of PHI elimination, each variable definition is only
555 // live until the end of the block. We've already taken care of the
556 // rest of the live range.
557 unsigned defIndex = getDefIndex(MIIdx);
560 unsigned SrcReg, DstReg;
561 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
562 ValNum = interval.getNextValue(~0U, 0);
564 ValNum = interval.getNextValue(defIndex, SrcReg);
566 LiveRange LR(defIndex,
567 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
568 interval.addRange(LR);
569 DEBUG(std::cerr << " +" << LR);
573 DEBUG(std::cerr << '\n');
576 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
577 MachineBasicBlock::iterator mi,
579 LiveInterval &interval,
581 // A physical register cannot be live across basic block, so its
582 // lifetime must end somewhere in its defining basic block.
583 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
584 typedef LiveVariables::killed_iterator KillIter;
586 unsigned baseIndex = MIIdx;
587 unsigned start = getDefIndex(baseIndex);
588 unsigned end = start;
590 // If it is not used after definition, it is considered dead at
591 // the instruction defining it. Hence its interval is:
592 // [defSlot(def), defSlot(def)+1)
593 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
594 DEBUG(std::cerr << " dead");
595 end = getDefIndex(start) + 1;
599 // If it is not dead on definition, it must be killed by a
600 // subsequent instruction. Hence its interval is:
601 // [defSlot(def), useSlot(kill)+1)
602 while (++mi != MBB->end()) {
603 baseIndex += InstrSlots::NUM;
604 if (lv_->KillsRegister(mi, interval.reg)) {
605 DEBUG(std::cerr << " killed");
606 end = getUseIndex(baseIndex) + 1;
611 // The only case we should have a dead physreg here without a killing or
612 // instruction where we know it's dead is if it is live-in to the function
614 assert(!SrcReg && "physreg was not killed in defining block!");
615 end = getDefIndex(start) + 1; // It's dead.
618 assert(start < end && "did not find end of interval?");
620 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
622 interval.addRange(LR);
623 DEBUG(std::cerr << " +" << LR << '\n');
626 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
627 MachineBasicBlock::iterator MI,
630 if (MRegisterInfo::isVirtualRegister(reg))
631 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
632 else if (allocatableRegs_[reg]) {
633 unsigned SrcReg, DstReg;
634 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
636 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
637 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
638 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
642 /// computeIntervals - computes the live intervals for virtual
643 /// registers. for some ordering of the machine instructions [1,N] a
644 /// live interval is an interval [i, j) where 1 <= i <= j < N for
645 /// which a variable is live
646 void LiveIntervals::computeIntervals() {
647 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
648 DEBUG(std::cerr << "********** Function: "
649 << ((Value*)mf_->getFunction())->getName() << '\n');
650 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
652 // Track the index of the current machine instr.
653 unsigned MIIndex = 0;
654 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
656 MachineBasicBlock *MBB = MBBI;
657 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
659 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
660 if (IgnoreFirstInstr) {
662 IgnoreFirstInstr = false;
663 MIIndex += InstrSlots::NUM;
666 for (; MI != miEnd; ++MI) {
667 const TargetInstrDescriptor &TID = tii_->get(MI->getOpcode());
668 DEBUG(std::cerr << MIIndex << "\t" << *MI);
670 // Handle implicit defs.
671 if (TID.ImplicitDefs) {
672 for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef)
673 handleRegisterDef(MBB, MI, MIIndex, *ImpDef);
676 // Handle explicit defs.
677 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
678 MachineOperand &MO = MI->getOperand(i);
679 // handle register defs - build intervals
680 if (MO.isRegister() && MO.getReg() && MO.isDef())
681 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
684 MIIndex += InstrSlots::NUM;
689 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
690 /// being the source and IntB being the dest, thus this defines a value number
691 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
692 /// see if we can merge these two pieces of B into a single value number,
693 /// eliminating a copy. For example:
697 /// B1 = A3 <- this copy
699 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
700 /// value number to be replaced with B0 (which simplifies the B liveinterval).
702 /// This returns true if an interval was modified.
704 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
705 MachineInstr *CopyMI) {
706 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
708 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
709 // the example above.
710 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
711 unsigned BValNo = BLR->ValId;
713 // Get the location that B is defined at. Two options: either this value has
714 // an unknown definition point or it is defined at CopyIdx. If unknown, we
716 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
717 if (BValNoDefIdx == ~0U) return false;
718 assert(BValNoDefIdx == CopyIdx &&
719 "Copy doesn't define the value?");
721 // AValNo is the value number in A that defines the copy, A0 in the example.
722 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
723 unsigned AValNo = AValLR->ValId;
725 // If AValNo is defined as a copy from IntB, we can potentially process this.
727 // Get the instruction that defines this value number.
728 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
729 if (!SrcReg) return false; // Not defined by a copy.
731 // If the value number is not defined by a copy instruction, ignore it.
733 // If the source register comes from an interval other than IntB, we can't
735 if (rep(SrcReg) != IntB.reg) return false;
737 // Get the LiveRange in IntB that this value number starts with.
738 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
739 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
741 // Make sure that the end of the live range is inside the same block as
743 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
745 ValLREndInst->getParent() != CopyMI->getParent()) return false;
747 // Okay, we now know that ValLR ends in the same block that the CopyMI
748 // live-range starts. If there are no intervening live ranges between them in
749 // IntB, we can merge them.
750 if (ValLR+1 != BLR) return false;
752 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_));
754 // We are about to delete CopyMI, so need to remove it as the 'instruction
755 // that defines this value #'.
756 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
758 // Okay, we can merge them. We need to insert a new liverange:
759 // [ValLR.end, BLR.begin) of either value number, then we merge the
760 // two value numbers.
761 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
762 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
764 // If the IntB live range is assigned to a physical register, and if that
765 // physreg has aliases,
766 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
767 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
768 LiveInterval &AliasLI = getInterval(*AS);
769 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
770 AliasLI.getNextValue(~0U, 0)));
774 // Okay, merge "B1" into the same value number as "B0".
775 if (BValNo != ValLR->ValId)
776 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
777 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_);
780 // Finally, delete the copy instruction.
781 RemoveMachineInstrFromMaps(CopyMI);
782 CopyMI->eraseFromParent();
788 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
789 /// which are the src/dst of the copy instruction CopyMI. This returns true
790 /// if the copy was successfully coallesced away, or if it is never possible
791 /// to coallesce these this copy, due to register constraints. It returns
792 /// false if it is not currently possible to coallesce this interval, but
793 /// it may be possible if other things get coallesced.
794 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
795 unsigned SrcReg, unsigned DstReg) {
798 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI);
800 // Get representative registers.
801 SrcReg = rep(SrcReg);
802 DstReg = rep(DstReg);
804 // If they are already joined we continue.
805 if (SrcReg == DstReg) {
806 DEBUG(std::cerr << "\tCopy already coallesced.\n");
807 return true; // Not coallescable.
810 // If they are both physical registers, we cannot join them.
811 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
812 MRegisterInfo::isPhysicalRegister(DstReg)) {
813 DEBUG(std::cerr << "\tCan not coallesce physregs.\n");
814 return true; // Not coallescable.
817 // We only join virtual registers with allocatable physical registers.
818 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
819 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n");
820 return true; // Not coallescable.
822 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
823 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n");
824 return true; // Not coallescable.
827 // If they are not of the same register class, we cannot join them.
828 if (differingRegisterClasses(SrcReg, DstReg)) {
829 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n");
830 return true; // Not coallescable.
833 LiveInterval &SrcInt = getInterval(SrcReg);
834 LiveInterval &DestInt = getInterval(DstReg);
835 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
836 "Register mapping is horribly broken!");
838 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
839 std::cerr << " and "; DestInt.print(std::cerr, mri_);
842 // Okay, attempt to join these two intervals. On failure, this returns false.
843 // Otherwise, if one of the intervals being joined is a physreg, this method
844 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
845 // been modified, so we can use this information below to update aliases.
846 if (!JoinIntervals(DestInt, SrcInt)) {
847 // Coallescing failed.
849 // If we can eliminate the copy without merging the live ranges, do so now.
850 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
853 // Otherwise, we are unable to join the intervals.
854 DEBUG(std::cerr << "Interference!\n");
858 bool Swapped = SrcReg == DestInt.reg;
860 std::swap(SrcReg, DstReg);
861 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
862 "LiveInterval::join didn't work right!");
864 // If we're about to merge live ranges into a physical register live range,
865 // we have to update any aliased register's live ranges to indicate that they
866 // have clobbered values for this range.
867 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
868 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
869 getInterval(*AS).MergeInClobberRanges(SrcInt);
872 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_);
875 // If the intervals were swapped by Join, swap them back so that the register
876 // mapping (in the r2i map) is correct.
877 if (Swapped) SrcInt.swap(DestInt);
878 r2iMap_.erase(SrcReg);
879 r2rMap_[SrcReg] = DstReg;
881 // Finally, delete the copy instruction.
882 RemoveMachineInstrFromMaps(CopyMI);
883 CopyMI->eraseFromParent();
889 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
890 /// compute what the resultant value numbers for each value in the input two
891 /// ranges will be. This is complicated by copies between the two which can
892 /// and will commonly cause multiple value numbers to be merged into one.
894 /// VN is the value number that we're trying to resolve. InstDefiningValue
895 /// keeps track of the new InstDefiningValue assignment for the result
896 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
897 /// whether a value in this or other is a copy from the opposite set.
898 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
899 /// already been assigned.
901 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
902 /// contains the value number the copy is from.
904 static unsigned ComputeUltimateVN(unsigned VN,
905 SmallVector<std::pair<unsigned,
906 unsigned>, 16> &ValueNumberInfo,
907 SmallVector<int, 16> &ThisFromOther,
908 SmallVector<int, 16> &OtherFromThis,
909 SmallVector<int, 16> &ThisValNoAssignments,
910 SmallVector<int, 16> &OtherValNoAssignments,
911 LiveInterval &ThisLI, LiveInterval &OtherLI) {
912 // If the VN has already been computed, just return it.
913 if (ThisValNoAssignments[VN] >= 0)
914 return ThisValNoAssignments[VN];
915 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
917 // If this val is not a copy from the other val, then it must be a new value
918 // number in the destination.
919 int OtherValNo = ThisFromOther[VN];
920 if (OtherValNo == -1) {
921 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
922 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
925 // Otherwise, this *is* a copy from the RHS. If the other side has already
926 // been computed, return it.
927 if (OtherValNoAssignments[OtherValNo] >= 0)
928 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
930 // Mark this value number as currently being computed, then ask what the
931 // ultimate value # of the other value is.
932 ThisValNoAssignments[VN] = -2;
933 unsigned UltimateVN =
934 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
935 OtherFromThis, ThisFromOther,
936 OtherValNoAssignments, ThisValNoAssignments,
938 return ThisValNoAssignments[VN] = UltimateVN;
941 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
942 return std::find(V.begin(), V.end(), Val) != V.end();
945 /// SimpleJoin - Attempt to joint the specified interval into this one. The
946 /// caller of this method must guarantee that the RHS only contains a single
947 /// value number and that the RHS is not defined by a copy from this
948 /// interval. This returns false if the intervals are not joinable, or it
949 /// joins them and returns true.
950 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
951 assert(RHS.containsOneValue());
953 // Some number (potentially more than one) value numbers in the current
954 // interval may be defined as copies from the RHS. Scan the overlapping
955 // portions of the LHS and RHS, keeping track of this and looking for
956 // overlapping live ranges that are NOT defined as copies. If these exist, we
959 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
960 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
962 if (LHSIt->start < RHSIt->start) {
963 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
964 if (LHSIt != LHS.begin()) --LHSIt;
965 } else if (RHSIt->start < LHSIt->start) {
966 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
967 if (RHSIt != RHS.begin()) --RHSIt;
970 SmallVector<unsigned, 8> EliminatedLHSVals;
973 // Determine if these live intervals overlap.
974 bool Overlaps = false;
975 if (LHSIt->start <= RHSIt->start)
976 Overlaps = LHSIt->end > RHSIt->start;
978 Overlaps = RHSIt->end > LHSIt->start;
980 // If the live intervals overlap, there are two interesting cases: if the
981 // LHS interval is defined by a copy from the RHS, it's ok and we record
982 // that the LHS value # is the same as the RHS. If it's not, then we cannot
983 // coallesce these live ranges and we bail out.
985 // If we haven't already recorded that this value # is safe, check it.
986 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
987 // Copy from the RHS?
988 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
989 if (rep(SrcReg) != RHS.reg)
990 return false; // Nope, bail out.
992 EliminatedLHSVals.push_back(LHSIt->ValId);
995 // We know this entire LHS live range is okay, so skip it now.
996 if (++LHSIt == LHSEnd) break;
1000 if (LHSIt->end < RHSIt->end) {
1001 if (++LHSIt == LHSEnd) break;
1003 // One interesting case to check here. It's possible that we have
1004 // something like "X3 = Y" which defines a new value number in the LHS,
1005 // and is the last use of this liverange of the RHS. In this case, we
1006 // want to notice this copy (so that it gets coallesced away) even though
1007 // the live ranges don't actually overlap.
1008 if (LHSIt->start == RHSIt->end) {
1009 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
1010 // We already know that this value number is going to be merged in
1011 // if coallescing succeeds. Just skip the liverange.
1012 if (++LHSIt == LHSEnd) break;
1014 // Otherwise, if this is a copy from the RHS, mark it as being merged
1016 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
1017 EliminatedLHSVals.push_back(LHSIt->ValId);
1019 // We know this entire LHS live range is okay, so skip it now.
1020 if (++LHSIt == LHSEnd) break;
1025 if (++RHSIt == RHSEnd) break;
1029 // If we got here, we know that the coallescing will be successful and that
1030 // the value numbers in EliminatedLHSVals will all be merged together. Since
1031 // the most common case is that EliminatedLHSVals has a single number, we
1032 // optimize for it: if there is more than one value, we merge them all into
1033 // the lowest numbered one, then handle the interval as if we were merging
1034 // with one value number.
1036 if (EliminatedLHSVals.size() > 1) {
1037 // Loop through all the equal value numbers merging them into the smallest
1039 unsigned Smallest = EliminatedLHSVals[0];
1040 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1041 if (EliminatedLHSVals[i] < Smallest) {
1042 // Merge the current notion of the smallest into the smaller one.
1043 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1044 Smallest = EliminatedLHSVals[i];
1046 // Merge into the smallest.
1047 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1050 LHSValNo = Smallest;
1052 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1053 LHSValNo = EliminatedLHSVals[0];
1056 // Okay, now that there is a single LHS value number that we're merging the
1057 // RHS into, update the value number info for the LHS to indicate that the
1058 // value number is defined where the RHS value number was.
1059 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1061 // Okay, the final step is to loop over the RHS live intervals, adding them to
1063 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1064 LHS.weight += RHS.weight;
1069 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1070 /// returns false. Otherwise, if one of the intervals being joined is a
1071 /// physreg, this method always canonicalizes LHS to be it. The output
1072 /// "RHS" will not have been modified, so we can use this information
1073 /// below to update aliases.
1074 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1075 // Compute the final value assignment, assuming that the live ranges can be
1077 SmallVector<int, 16> LHSValNoAssignments;
1078 SmallVector<int, 16> RHSValNoAssignments;
1079 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1081 // Compute ultimate value numbers for the LHS and RHS values.
1082 if (RHS.containsOneValue()) {
1083 // Copies from a liveinterval with a single value are simple to handle and
1084 // very common, handle the special case here. This is important, because
1085 // often RHS is small and LHS is large (e.g. a physreg).
1087 // Find out if the RHS is defined as a copy from some value in the LHS.
1089 std::pair<unsigned,unsigned> RHSValNoInfo;
1090 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1091 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1092 // If RHS is not defined as a copy from the LHS, we can use simpler and
1093 // faster checks to see if the live ranges are coallescable. This joiner
1094 // can't swap the LHS/RHS intervals though.
1095 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1096 return SimpleJoin(LHS, RHS);
1098 RHSValNoInfo = RHS.getValNumInfo(0);
1101 // It was defined as a copy from the LHS, find out what value # it is.
1102 unsigned ValInst = RHS.getInstForValNum(0);
1103 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1104 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1107 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1108 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1109 ValueNumberInfo.resize(LHS.getNumValNums());
1111 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1112 // should now get updated.
1113 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1114 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1115 if (rep(LHSSrcReg) != RHS.reg) {
1116 // If this is not a copy from the RHS, its value number will be
1117 // unmodified by the coallescing.
1118 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1119 LHSValNoAssignments[VN] = VN;
1120 } else if (RHSValID == -1) {
1121 // Otherwise, it is a copy from the RHS, and we don't already have a
1122 // value# for it. Keep the current value number, but remember it.
1123 LHSValNoAssignments[VN] = RHSValID = VN;
1124 ValueNumberInfo[VN] = RHSValNoInfo;
1126 // Otherwise, use the specified value #.
1127 LHSValNoAssignments[VN] = RHSValID;
1128 if (VN != (unsigned)RHSValID)
1129 ValueNumberInfo[VN].first = ~1U;
1131 ValueNumberInfo[VN] = RHSValNoInfo;
1134 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1135 LHSValNoAssignments[VN] = VN;
1139 assert(RHSValID != -1 && "Didn't find value #?");
1140 RHSValNoAssignments[0] = RHSValID;
1143 // Loop over the value numbers of the LHS, seeing if any are defined from
1145 SmallVector<int, 16> LHSValsDefinedFromRHS;
1146 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1147 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1148 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1149 if (ValSrcReg == 0) // Src not defined by a copy?
1152 // DstReg is known to be a register in the LHS interval. If the src is
1153 // from the RHS interval, we can use its value #.
1154 if (rep(ValSrcReg) != RHS.reg)
1157 // Figure out the value # from the RHS.
1158 unsigned ValInst = LHS.getInstForValNum(VN);
1159 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1162 // Loop over the value numbers of the RHS, seeing if any are defined from
1164 SmallVector<int, 16> RHSValsDefinedFromLHS;
1165 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1166 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1167 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1168 if (ValSrcReg == 0) // Src not defined by a copy?
1171 // DstReg is known to be a register in the RHS interval. If the src is
1172 // from the LHS interval, we can use its value #.
1173 if (rep(ValSrcReg) != LHS.reg)
1176 // Figure out the value # from the LHS.
1177 unsigned ValInst = RHS.getInstForValNum(VN);
1178 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1181 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1182 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1183 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1185 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1186 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1188 ComputeUltimateVN(VN, ValueNumberInfo,
1189 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1190 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1192 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1193 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1195 // If this value number isn't a copy from the LHS, it's a new number.
1196 if (RHSValsDefinedFromLHS[VN] == -1) {
1197 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1198 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1202 ComputeUltimateVN(VN, ValueNumberInfo,
1203 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1204 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1208 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1209 // interval lists to see if these intervals are coallescable.
1210 LiveInterval::const_iterator I = LHS.begin();
1211 LiveInterval::const_iterator IE = LHS.end();
1212 LiveInterval::const_iterator J = RHS.begin();
1213 LiveInterval::const_iterator JE = RHS.end();
1215 // Skip ahead until the first place of potential sharing.
1216 if (I->start < J->start) {
1217 I = std::upper_bound(I, IE, J->start);
1218 if (I != LHS.begin()) --I;
1219 } else if (J->start < I->start) {
1220 J = std::upper_bound(J, JE, I->start);
1221 if (J != RHS.begin()) --J;
1225 // Determine if these two live ranges overlap.
1227 if (I->start < J->start) {
1228 Overlaps = I->end > J->start;
1230 Overlaps = J->end > I->start;
1233 // If so, check value # info to determine if they are really different.
1235 // If the live range overlap will map to the same value number in the
1236 // result liverange, we can still coallesce them. If not, we can't.
1237 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1241 if (I->end < J->end) {
1250 // If we get here, we know that we can coallesce the live ranges. Ask the
1251 // intervals to coallesce themselves now.
1252 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1259 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1260 // depth of the basic block (the unsigned), and then on the MBB number.
1261 struct DepthMBBCompare {
1262 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1263 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1264 if (LHS.first > RHS.first) return true; // Deeper loops first
1265 return LHS.first == RHS.first &&
1266 LHS.second->getNumber() < RHS.second->getNumber();
1272 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1273 std::vector<CopyRec> &TryAgain) {
1274 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
1276 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1278 MachineInstr *Inst = MII++;
1280 // If this isn't a copy, we can't join intervals.
1281 unsigned SrcReg, DstReg;
1282 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1284 if (!JoinCopy(Inst, SrcReg, DstReg))
1285 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
1290 void LiveIntervals::joinIntervals() {
1291 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
1293 std::vector<CopyRec> TryAgainList;
1295 const LoopInfo &LI = getAnalysis<LoopInfo>();
1296 if (LI.begin() == LI.end()) {
1297 // If there are no loops in the function, join intervals in function order.
1298 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1300 CopyCoallesceInMBB(I, TryAgainList);
1302 // Otherwise, join intervals in inner loops before other intervals.
1303 // Unfortunately we can't just iterate over loop hierarchy here because
1304 // there may be more MBB's than BB's. Collect MBB's for sorting.
1305 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1306 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1308 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1310 // Sort by loop depth.
1311 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1313 // Finally, join intervals in loop nest order.
1314 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1315 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
1318 // Joining intervals can allow other intervals to be joined. Iteratively join
1319 // until we make no progress.
1320 bool ProgressMade = true;
1321 while (ProgressMade) {
1322 ProgressMade = false;
1324 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1325 CopyRec &TheCopy = TryAgainList[i];
1327 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1328 TheCopy.MI = 0; // Mark this one as done.
1329 ProgressMade = true;
1334 DEBUG(std::cerr << "*** Register mapping ***\n");
1335 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1337 std::cerr << " reg " << i << " -> ";
1338 printRegName(r2rMap_[i]);
1343 /// Return true if the two specified registers belong to different register
1344 /// classes. The registers may be either phys or virt regs.
1345 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1346 unsigned RegB) const {
1348 // Get the register classes for the first reg.
1349 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1350 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1351 "Shouldn't consider two physregs!");
1352 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1355 // Compare against the regclass for the second reg.
1356 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1357 if (MRegisterInfo::isVirtualRegister(RegB))
1358 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1360 return !RegClass->contains(RegB);
1363 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1364 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1366 return LiveInterval(reg, Weight);