1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numIntervals, "Number of original intervals");
40 STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
41 STATISTIC(numJoins , "Number of interval joins performed");
42 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
43 STATISTIC(numFolded , "Number of loads/stores folded into instructions");
46 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
49 EnableJoining("join-liveintervals",
50 cl::desc("Coallesce copies (default=true)"),
54 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.addRequired<LiveVariables>();
56 AU.addPreservedID(PHIEliminationID);
57 AU.addRequiredID(PHIEliminationID);
58 AU.addRequiredID(TwoAddressInstructionPassID);
59 AU.addRequired<LoopInfo>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 void LiveIntervals::releaseMemory() {
71 static bool isZeroLengthInterval(LiveInterval *li) {
72 for (LiveInterval::Ranges::const_iterator
73 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
74 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
80 /// runOnMachineFunction - Register allocate the whole function
82 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
84 tm_ = &fn.getTarget();
85 mri_ = tm_->getRegisterInfo();
86 tii_ = tm_->getInstrInfo();
87 lv_ = &getAnalysis<LiveVariables>();
88 allocatableRegs_ = mri_->getAllocatableSet(fn);
89 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
91 // Number MachineInstrs and MachineBasicBlocks.
92 // Initialize MBB indexes to a sentinal.
93 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
96 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
98 // Set the MBB2IdxMap entry for this MBB.
99 MBB2IdxMap[MBB->getNumber()] = MIIndex;
101 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
103 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
104 assert(inserted && "multiple MachineInstr -> index mappings");
105 i2miMap_.push_back(I);
106 MIIndex += InstrSlots::NUM;
112 numIntervals += getNumIntervals();
114 DOUT << "********** INTERVALS **********\n";
115 for (iterator I = begin(), E = end(); I != E; ++I) {
116 I->second.print(DOUT, mri_);
120 // Join (coallesce) intervals if requested.
121 if (EnableJoining) joinIntervals();
123 numIntervalsAfter += getNumIntervals();
126 // perform a final pass over the instructions and compute spill
127 // weights, coalesce virtual registers and remove identity moves.
128 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
130 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
131 mbbi != mbbe; ++mbbi) {
132 MachineBasicBlock* mbb = mbbi;
133 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
135 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
137 // if the move will be an identity move delete it
138 unsigned srcReg, dstReg, RegRep;
139 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
140 (RegRep = rep(srcReg)) == rep(dstReg)) {
141 // remove from def list
142 LiveInterval &RegInt = getOrCreateInterval(RegRep);
143 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
144 // If def of this move instruction is dead, remove its live range from
145 // the dstination register's live interval.
147 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii));
148 RegInt.removeRange(*RegInt.FindLiveRangeContaining(MoveIdx));
150 removeInterval(RegRep);
152 RemoveMachineInstrFromMaps(mii);
153 mii = mbbi->erase(mii);
157 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
158 const MachineOperand &mop = mii->getOperand(i);
159 if (mop.isRegister() && mop.getReg() &&
160 MRegisterInfo::isVirtualRegister(mop.getReg())) {
161 // replace register with representative register
162 unsigned reg = rep(mop.getReg());
163 mii->getOperand(i).setReg(reg);
165 LiveInterval &RegInt = getInterval(reg);
167 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
175 for (iterator I = begin(), E = end(); I != E; ++I) {
176 LiveInterval &LI = I->second;
177 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
178 // If the live interval length is essentially zero, i.e. in every live
179 // range the use follows def immediately, it doesn't make sense to spill
180 // it and hope it will be easier to allocate for this li.
181 if (isZeroLengthInterval(&LI))
182 LI.weight = HUGE_VALF;
184 // Divide the weight of the interval by its size. This encourages
185 // spilling of intervals that are large and have few uses, and
186 // discourages spilling of small intervals with many uses.
188 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II)
189 Size += II->end - II->start;
199 /// print - Implement the dump method.
200 void LiveIntervals::print(std::ostream &O, const Module* ) const {
201 O << "********** INTERVALS **********\n";
202 for (const_iterator I = begin(), E = end(); I != E; ++I) {
203 I->second.print(DOUT, mri_);
207 O << "********** MACHINEINSTRS **********\n";
208 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
209 mbbi != mbbe; ++mbbi) {
210 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
211 for (MachineBasicBlock::iterator mii = mbbi->begin(),
212 mie = mbbi->end(); mii != mie; ++mii) {
213 O << getInstructionIndex(mii) << '\t' << *mii;
218 /// CreateNewLiveInterval - Create a new live interval with the given live
219 /// ranges. The new live interval will have an infinite spill weight.
221 LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
222 const std::vector<LiveRange> &LRs) {
223 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
225 // Create a new virtual register for the spill interval.
226 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
228 // Replace the old virtual registers in the machine operands with the shiny
230 for (std::vector<LiveRange>::const_iterator
231 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
232 unsigned Index = getBaseIndex(I->start);
233 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
235 for (; Index != End; Index += InstrSlots::NUM) {
236 // Skip deleted instructions
237 while (Index != End && !getInstructionFromIndex(Index))
238 Index += InstrSlots::NUM;
240 if (Index == End) break;
242 MachineInstr *MI = getInstructionFromIndex(Index);
244 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
245 MachineOperand &MOp = MI->getOperand(J);
246 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg)
252 LiveInterval &NewLI = getOrCreateInterval(NewVReg);
254 // The spill weight is now infinity as it cannot be spilled again
255 NewLI.weight = float(HUGE_VAL);
257 for (std::vector<LiveRange>::const_iterator
258 I = LRs.begin(), E = LRs.end(); I != E; ++I) {
259 DOUT << " Adding live range " << *I << " to new interval\n";
263 DOUT << "Created new live interval " << NewLI << "\n";
267 std::vector<LiveInterval*> LiveIntervals::
268 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
269 // since this is called after the analysis is done we don't know if
270 // LiveVariables is available
271 lv_ = getAnalysisToUpdate<LiveVariables>();
273 std::vector<LiveInterval*> added;
275 assert(li.weight != HUGE_VALF &&
276 "attempt to spill already spilled interval!");
278 DOUT << "\t\t\t\tadding intervals for spills for interval: ";
279 li.print(DOUT, mri_);
282 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
284 for (LiveInterval::Ranges::const_iterator
285 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
286 unsigned index = getBaseIndex(i->start);
287 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
288 for (; index != end; index += InstrSlots::NUM) {
289 // skip deleted instructions
290 while (index != end && !getInstructionFromIndex(index))
291 index += InstrSlots::NUM;
292 if (index == end) break;
294 MachineInstr *MI = getInstructionFromIndex(index);
297 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
298 MachineOperand& mop = MI->getOperand(i);
299 if (mop.isRegister() && mop.getReg() == li.reg) {
300 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) {
301 // Attempt to fold the memory reference into the instruction. If we
302 // can do this, we don't need to insert spill code.
304 lv_->instructionChanged(MI, fmi);
305 MachineBasicBlock &MBB = *MI->getParent();
306 vrm.virtFolded(li.reg, MI, i, fmi);
308 i2miMap_[index/InstrSlots::NUM] = fmi;
309 mi2iMap_[fmi] = index;
310 MI = MBB.insert(MBB.erase(MI), fmi);
312 // Folding the load/store can completely change the instruction in
313 // unpredictable ways, rescan it from the beginning.
314 goto RestartInstruction;
316 // Create a new virtual register for the spill interval.
317 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
319 // Scan all of the operands of this instruction rewriting operands
320 // to use NewVReg instead of li.reg as appropriate. We do this for
323 // 1. If the instr reads the same spilled vreg multiple times, we
324 // want to reuse the NewVReg.
325 // 2. If the instr is a two-addr instruction, we are required to
326 // keep the src/dst regs pinned.
328 // Keep track of whether we replace a use and/or def so that we can
329 // create the spill interval with the appropriate range.
332 bool HasUse = mop.isUse();
333 bool HasDef = mop.isDef();
334 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
335 if (MI->getOperand(j).isReg() &&
336 MI->getOperand(j).getReg() == li.reg) {
337 MI->getOperand(j).setReg(NewVReg);
338 HasUse |= MI->getOperand(j).isUse();
339 HasDef |= MI->getOperand(j).isDef();
343 // create a new register for this spill
345 vrm.assignVirt2StackSlot(NewVReg, slot);
346 LiveInterval &nI = getOrCreateInterval(NewVReg);
349 // the spill weight is now infinity as it
350 // cannot be spilled again
351 nI.weight = HUGE_VALF;
354 LiveRange LR(getLoadIndex(index), getUseIndex(index),
355 nI.getNextValue(~0U, 0));
360 LiveRange LR(getDefIndex(index), getStoreIndex(index),
361 nI.getNextValue(~0U, 0));
366 added.push_back(&nI);
368 // update live variables if it is available
370 lv_->addVirtualRegisterKilled(NewVReg, MI);
372 DOUT << "\t\t\t\tadded new interval: ";
373 nI.print(DOUT, mri_);
384 void LiveIntervals::printRegName(unsigned reg) const {
385 if (MRegisterInfo::isPhysicalRegister(reg))
386 cerr << mri_->getName(reg);
388 cerr << "%reg" << reg;
391 /// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
392 /// two addr elimination.
393 static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
394 const TargetInstrInfo *TII) {
395 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
396 MachineOperand &MO1 = MI->getOperand(i);
397 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
398 for (unsigned j = i+1; j < e; ++j) {
399 MachineOperand &MO2 = MI->getOperand(j);
400 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
401 MI->getInstrDescriptor()->
402 getOperandConstraint(j, TOI::TIED_TO) == (int)i)
410 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
411 MachineBasicBlock::iterator mi,
413 LiveInterval &interval) {
414 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
415 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
417 // Virtual registers may be defined multiple times (due to phi
418 // elimination and 2-addr elimination). Much of what we do only has to be
419 // done once for the vreg. We use an empty interval to detect the first
420 // time we see a vreg.
421 if (interval.empty()) {
422 // Get the Idx of the defining instructions.
423 unsigned defIndex = getDefIndex(MIIdx);
426 unsigned SrcReg, DstReg;
427 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
428 ValNum = interval.getNextValue(~0U, 0);
430 ValNum = interval.getNextValue(defIndex, SrcReg);
432 assert(ValNum == 0 && "First value in interval is not 0?");
433 ValNum = 0; // Clue in the optimizer.
435 // Loop over all of the blocks that the vreg is defined in. There are
436 // two cases we have to handle here. The most common case is a vreg
437 // whose lifetime is contained within a basic block. In this case there
438 // will be a single kill, in MBB, which comes after the definition.
439 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
440 // FIXME: what about dead vars?
442 if (vi.Kills[0] != mi)
443 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
445 killIdx = defIndex+1;
447 // If the kill happens after the definition, we have an intra-block
449 if (killIdx > defIndex) {
450 assert(vi.AliveBlocks.none() &&
451 "Shouldn't be alive across any blocks!");
452 LiveRange LR(defIndex, killIdx, ValNum);
453 interval.addRange(LR);
454 DOUT << " +" << LR << "\n";
459 // The other case we handle is when a virtual register lives to the end
460 // of the defining block, potentially live across some blocks, then is
461 // live into some number of blocks, but gets killed. Start by adding a
462 // range that goes from this definition to the end of the defining block.
463 LiveRange NewLR(defIndex,
464 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
466 DOUT << " +" << NewLR;
467 interval.addRange(NewLR);
469 // Iterate over all of the blocks that the variable is completely
470 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
472 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
473 if (vi.AliveBlocks[i]) {
474 MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
476 LiveRange LR(getMBBStartIdx(i),
477 getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
479 interval.addRange(LR);
485 // Finally, this virtual register is live from the start of any killing
486 // block to the 'use' slot of the killing instruction.
487 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
488 MachineInstr *Kill = vi.Kills[i];
489 LiveRange LR(getMBBStartIdx(Kill->getParent()),
490 getUseIndex(getInstructionIndex(Kill))+1,
492 interval.addRange(LR);
497 // If this is the second time we see a virtual register definition, it
498 // must be due to phi elimination or two addr elimination. If this is
499 // the result of two address elimination, then the vreg is one of the
500 // def-and-use register operand.
501 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
502 // If this is a two-address definition, then we have already processed
503 // the live range. The only problem is that we didn't realize there
504 // are actually two values in the live interval. Because of this we
505 // need to take the LiveRegion that defines this register and split it
507 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
508 unsigned RedefIndex = getDefIndex(MIIdx);
510 // Delete the initial value, which should be short and continuous,
511 // because the 2-addr copy must be in the same MBB as the redef.
512 interval.removeRange(DefIndex, RedefIndex);
514 // Two-address vregs should always only be redefined once. This means
515 // that at this point, there should be exactly one value number in it.
516 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
518 // The new value number (#1) is defined by the instruction we claimed
520 unsigned ValNo = interval.getNextValue(0, 0);
521 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
523 // Value#0 is now defined by the 2-addr instruction.
524 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
526 // Add the new live interval which replaces the range for the input copy.
527 LiveRange LR(DefIndex, RedefIndex, ValNo);
528 DOUT << " replace range with " << LR;
529 interval.addRange(LR);
531 // If this redefinition is dead, we need to add a dummy unit live
532 // range covering the def slot.
533 if (lv_->RegisterDefIsDead(mi, interval.reg))
534 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
537 interval.print(DOUT, mri_);
540 // Otherwise, this must be because of phi elimination. If this is the
541 // first redefinition of the vreg that we have seen, go back and change
542 // the live range in the PHI block to be a different value number.
543 if (interval.containsOneValue()) {
544 assert(vi.Kills.size() == 1 &&
545 "PHI elimination vreg should have one kill, the PHI itself!");
547 // Remove the old range that we now know has an incorrect number.
548 MachineInstr *Killer = vi.Kills[0];
549 unsigned Start = getMBBStartIdx(Killer->getParent());
550 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
551 DOUT << "Removing [" << Start << "," << End << "] from: ";
552 interval.print(DOUT, mri_); DOUT << "\n";
553 interval.removeRange(Start, End);
554 DOUT << "RESULT: "; interval.print(DOUT, mri_);
556 // Replace the interval with one of a NEW value number. Note that this
557 // value number isn't actually defined by an instruction, weird huh? :)
558 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
559 DOUT << " replace range with " << LR;
560 interval.addRange(LR);
561 DOUT << "RESULT: "; interval.print(DOUT, mri_);
564 // In the case of PHI elimination, each variable definition is only
565 // live until the end of the block. We've already taken care of the
566 // rest of the live range.
567 unsigned defIndex = getDefIndex(MIIdx);
570 unsigned SrcReg, DstReg;
571 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
572 ValNum = interval.getNextValue(~0U, 0);
574 ValNum = interval.getNextValue(defIndex, SrcReg);
576 LiveRange LR(defIndex,
577 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
578 interval.addRange(LR);
586 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
587 MachineBasicBlock::iterator mi,
589 LiveInterval &interval,
591 // A physical register cannot be live across basic block, so its
592 // lifetime must end somewhere in its defining basic block.
593 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
595 unsigned baseIndex = MIIdx;
596 unsigned start = getDefIndex(baseIndex);
597 unsigned end = start;
599 // If it is not used after definition, it is considered dead at
600 // the instruction defining it. Hence its interval is:
601 // [defSlot(def), defSlot(def)+1)
602 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
604 end = getDefIndex(start) + 1;
608 // If it is not dead on definition, it must be killed by a
609 // subsequent instruction. Hence its interval is:
610 // [defSlot(def), useSlot(kill)+1)
611 while (++mi != MBB->end()) {
612 baseIndex += InstrSlots::NUM;
613 if (lv_->KillsRegister(mi, interval.reg)) {
615 end = getUseIndex(baseIndex) + 1;
617 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
618 // Another instruction redefines the register before it is ever read.
619 // Then the register is essentially dead at the instruction that defines
620 // it. Hence its interval is:
621 // [defSlot(def), defSlot(def)+1)
623 end = getDefIndex(start) + 1;
628 // The only case we should have a dead physreg here without a killing or
629 // instruction where we know it's dead is if it is live-in to the function
631 assert(!SrcReg && "physreg was not killed in defining block!");
632 end = getDefIndex(start) + 1; // It's dead.
635 assert(start < end && "did not find end of interval?");
637 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
639 interval.addRange(LR);
640 DOUT << " +" << LR << '\n';
643 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
644 MachineBasicBlock::iterator MI,
647 if (MRegisterInfo::isVirtualRegister(reg))
648 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
649 else if (allocatableRegs_[reg]) {
650 unsigned SrcReg, DstReg;
651 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
653 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
654 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
655 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
659 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
660 LiveInterval &interval) {
661 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
663 // Look for kills, if it reaches a def before it's killed, then it shouldn't
664 // be considered a livein.
665 MachineBasicBlock::iterator mi = MBB->begin();
666 unsigned baseIndex = 0;
668 unsigned end = start;
669 while (mi != MBB->end()) {
670 if (lv_->KillsRegister(mi, interval.reg)) {
672 end = getUseIndex(baseIndex) + 1;
674 } else if (lv_->ModifiesRegister(mi, interval.reg)) {
675 // Another instruction redefines the register before it is ever read.
676 // Then the register is essentially dead at the instruction that defines
677 // it. Hence its interval is:
678 // [defSlot(def), defSlot(def)+1)
680 end = getDefIndex(start) + 1;
684 baseIndex += InstrSlots::NUM;
689 assert(start < end && "did not find end of interval?");
691 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
692 interval.addRange(LR);
693 DOUT << " +" << LR << '\n';
696 /// computeIntervals - computes the live intervals for virtual
697 /// registers. for some ordering of the machine instructions [1,N] a
698 /// live interval is an interval [i, j) where 1 <= i <= j < N for
699 /// which a variable is live
700 void LiveIntervals::computeIntervals() {
701 DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
702 << "********** Function: "
703 << ((Value*)mf_->getFunction())->getName() << '\n';
704 // Track the index of the current machine instr.
705 unsigned MIIndex = 0;
706 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
708 MachineBasicBlock *MBB = MBBI;
709 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
711 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
713 if (MBB->livein_begin() != MBB->livein_end()) {
714 // Create intervals for live-ins to this BB first.
715 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
716 LE = MBB->livein_end(); LI != LE; ++LI) {
717 handleLiveInRegister(MBB, getOrCreateInterval(*LI));
718 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
719 handleLiveInRegister(MBB, getOrCreateInterval(*AS));
723 for (; MI != miEnd; ++MI) {
724 DOUT << MIIndex << "\t" << *MI;
727 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
728 MachineOperand &MO = MI->getOperand(i);
729 // handle register defs - build intervals
730 if (MO.isRegister() && MO.getReg() && MO.isDef())
731 handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
734 MIIndex += InstrSlots::NUM;
739 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
740 /// being the source and IntB being the dest, thus this defines a value number
741 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
742 /// see if we can merge these two pieces of B into a single value number,
743 /// eliminating a copy. For example:
747 /// B1 = A3 <- this copy
749 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
750 /// value number to be replaced with B0 (which simplifies the B liveinterval).
752 /// This returns true if an interval was modified.
754 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
755 MachineInstr *CopyMI) {
756 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
758 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
759 // the example above.
760 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
761 unsigned BValNo = BLR->ValId;
763 // Get the location that B is defined at. Two options: either this value has
764 // an unknown definition point or it is defined at CopyIdx. If unknown, we
766 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
767 if (BValNoDefIdx == ~0U) return false;
768 assert(BValNoDefIdx == CopyIdx &&
769 "Copy doesn't define the value?");
771 // AValNo is the value number in A that defines the copy, A0 in the example.
772 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
773 unsigned AValNo = AValLR->ValId;
775 // If AValNo is defined as a copy from IntB, we can potentially process this.
777 // Get the instruction that defines this value number.
778 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
779 if (!SrcReg) return false; // Not defined by a copy.
781 // If the value number is not defined by a copy instruction, ignore it.
783 // If the source register comes from an interval other than IntB, we can't
785 if (rep(SrcReg) != IntB.reg) return false;
787 // Get the LiveRange in IntB that this value number starts with.
788 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
789 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
791 // Make sure that the end of the live range is inside the same block as
793 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
795 ValLREndInst->getParent() != CopyMI->getParent()) return false;
797 // Okay, we now know that ValLR ends in the same block that the CopyMI
798 // live-range starts. If there are no intervening live ranges between them in
799 // IntB, we can merge them.
800 if (ValLR+1 != BLR) return false;
802 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
804 // We are about to delete CopyMI, so need to remove it as the 'instruction
805 // that defines this value #'.
806 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
808 // Okay, we can merge them. We need to insert a new liverange:
809 // [ValLR.end, BLR.begin) of either value number, then we merge the
810 // two value numbers.
811 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
812 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
814 // If the IntB live range is assigned to a physical register, and if that
815 // physreg has aliases,
816 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
817 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
818 LiveInterval &AliasLI = getInterval(*AS);
819 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
820 AliasLI.getNextValue(~0U, 0)));
824 // Okay, merge "B1" into the same value number as "B0".
825 if (BValNo != ValLR->ValId)
826 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
827 DOUT << " result = "; IntB.print(DOUT, mri_);
830 // Finally, delete the copy instruction.
831 RemoveMachineInstrFromMaps(CopyMI);
832 CopyMI->eraseFromParent();
837 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
838 /// which are the src/dst of the copy instruction CopyMI. This returns true
839 /// if the copy was successfully coallesced away, or if it is never possible
840 /// to coallesce these this copy, due to register constraints. It returns
841 /// false if it is not currently possible to coallesce this interval, but
842 /// it may be possible if other things get coallesced.
843 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
844 unsigned SrcReg, unsigned DstReg) {
845 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI;
847 // Get representative registers.
848 unsigned repSrcReg = rep(SrcReg);
849 unsigned repDstReg = rep(DstReg);
851 // If they are already joined we continue.
852 if (repSrcReg == repDstReg) {
853 DOUT << "\tCopy already coallesced.\n";
854 return true; // Not coallescable.
857 // If they are both physical registers, we cannot join them.
858 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
859 MRegisterInfo::isPhysicalRegister(repDstReg)) {
860 DOUT << "\tCan not coallesce physregs.\n";
861 return true; // Not coallescable.
864 // We only join virtual registers with allocatable physical registers.
865 if (MRegisterInfo::isPhysicalRegister(repSrcReg) &&
866 !allocatableRegs_[repSrcReg]) {
867 DOUT << "\tSrc reg is unallocatable physreg.\n";
868 return true; // Not coallescable.
870 if (MRegisterInfo::isPhysicalRegister(repDstReg) &&
871 !allocatableRegs_[repDstReg]) {
872 DOUT << "\tDst reg is unallocatable physreg.\n";
873 return true; // Not coallescable.
876 // If they are not of the same register class, we cannot join them.
877 if (differingRegisterClasses(repSrcReg, repDstReg)) {
878 DOUT << "\tSrc/Dest are different register classes.\n";
879 return true; // Not coallescable.
882 LiveInterval &SrcInt = getInterval(repSrcReg);
883 LiveInterval &DestInt = getInterval(repDstReg);
884 assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg &&
885 "Register mapping is horribly broken!");
887 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
888 DOUT << " and "; DestInt.print(DOUT, mri_);
891 // Check if it is necessary to propagate "isDead" property before intervals
893 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
894 bool isDead = mopd->isDead();
895 unsigned SrcStart = 0;
898 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
899 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1);
900 SrcStart = SrcLR->start;
902 if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd))
906 // Okay, attempt to join these two intervals. On failure, this returns false.
907 // Otherwise, if one of the intervals being joined is a physreg, this method
908 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
909 // been modified, so we can use this information below to update aliases.
910 if (JoinIntervals(DestInt, SrcInt)) {
912 // Result of the copy is dead. Propagate this property.
914 // Live-in to the function but dead. Remove it from MBB live-in set.
915 // JoinIntervals may end up swapping the two intervals.
916 LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt;
917 LiveInInt.removeRange(SrcStart, SrcEnd);
918 MachineBasicBlock *MBB = CopyMI->getParent();
919 MBB->removeLiveIn(SrcReg);
921 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart);
923 // FIXME: SrcMI == NULL means the register is livein to a non-entry
924 // MBB. Remove the range from its live interval?
925 MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg);
927 // FIXME: mops == NULL means SrcMI defines a subregister?
933 // Coallescing failed.
935 // If we can eliminate the copy without merging the live ranges, do so now.
936 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
939 // Otherwise, we are unable to join the intervals.
940 DOUT << "Interference!\n";
944 bool Swapped = repSrcReg == DestInt.reg;
946 std::swap(repSrcReg, repDstReg);
947 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
948 "LiveInterval::join didn't work right!");
950 // If we're about to merge live ranges into a physical register live range,
951 // we have to update any aliased register's live ranges to indicate that they
952 // have clobbered values for this range.
953 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
954 for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
955 getInterval(*AS).MergeInClobberRanges(SrcInt);
958 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_);
961 // If the intervals were swapped by Join, swap them back so that the register
962 // mapping (in the r2i map) is correct.
963 if (Swapped) SrcInt.swap(DestInt);
964 removeInterval(repSrcReg);
965 r2rMap_[repSrcReg] = repDstReg;
967 // Finally, delete the copy instruction.
968 RemoveMachineInstrFromMaps(CopyMI);
969 CopyMI->eraseFromParent();
975 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
976 /// compute what the resultant value numbers for each value in the input two
977 /// ranges will be. This is complicated by copies between the two which can
978 /// and will commonly cause multiple value numbers to be merged into one.
980 /// VN is the value number that we're trying to resolve. InstDefiningValue
981 /// keeps track of the new InstDefiningValue assignment for the result
982 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
983 /// whether a value in this or other is a copy from the opposite set.
984 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
985 /// already been assigned.
987 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
988 /// contains the value number the copy is from.
990 static unsigned ComputeUltimateVN(unsigned VN,
991 SmallVector<std::pair<unsigned,
992 unsigned>, 16> &ValueNumberInfo,
993 SmallVector<int, 16> &ThisFromOther,
994 SmallVector<int, 16> &OtherFromThis,
995 SmallVector<int, 16> &ThisValNoAssignments,
996 SmallVector<int, 16> &OtherValNoAssignments,
997 LiveInterval &ThisLI, LiveInterval &OtherLI) {
998 // If the VN has already been computed, just return it.
999 if (ThisValNoAssignments[VN] >= 0)
1000 return ThisValNoAssignments[VN];
1001 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1003 // If this val is not a copy from the other val, then it must be a new value
1004 // number in the destination.
1005 int OtherValNo = ThisFromOther[VN];
1006 if (OtherValNo == -1) {
1007 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
1008 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
1011 // Otherwise, this *is* a copy from the RHS. If the other side has already
1012 // been computed, return it.
1013 if (OtherValNoAssignments[OtherValNo] >= 0)
1014 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
1016 // Mark this value number as currently being computed, then ask what the
1017 // ultimate value # of the other value is.
1018 ThisValNoAssignments[VN] = -2;
1019 unsigned UltimateVN =
1020 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
1021 OtherFromThis, ThisFromOther,
1022 OtherValNoAssignments, ThisValNoAssignments,
1024 return ThisValNoAssignments[VN] = UltimateVN;
1027 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
1028 return std::find(V.begin(), V.end(), Val) != V.end();
1031 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1032 /// caller of this method must guarantee that the RHS only contains a single
1033 /// value number and that the RHS is not defined by a copy from this
1034 /// interval. This returns false if the intervals are not joinable, or it
1035 /// joins them and returns true.
1036 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
1037 assert(RHS.containsOneValue());
1039 // Some number (potentially more than one) value numbers in the current
1040 // interval may be defined as copies from the RHS. Scan the overlapping
1041 // portions of the LHS and RHS, keeping track of this and looking for
1042 // overlapping live ranges that are NOT defined as copies. If these exist, we
1043 // cannot coallesce.
1045 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1046 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1048 if (LHSIt->start < RHSIt->start) {
1049 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1050 if (LHSIt != LHS.begin()) --LHSIt;
1051 } else if (RHSIt->start < LHSIt->start) {
1052 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1053 if (RHSIt != RHS.begin()) --RHSIt;
1056 SmallVector<unsigned, 8> EliminatedLHSVals;
1059 // Determine if these live intervals overlap.
1060 bool Overlaps = false;
1061 if (LHSIt->start <= RHSIt->start)
1062 Overlaps = LHSIt->end > RHSIt->start;
1064 Overlaps = RHSIt->end > LHSIt->start;
1066 // If the live intervals overlap, there are two interesting cases: if the
1067 // LHS interval is defined by a copy from the RHS, it's ok and we record
1068 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1069 // coallesce these live ranges and we bail out.
1071 // If we haven't already recorded that this value # is safe, check it.
1072 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
1073 // Copy from the RHS?
1074 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
1075 if (rep(SrcReg) != RHS.reg)
1076 return false; // Nope, bail out.
1078 EliminatedLHSVals.push_back(LHSIt->ValId);
1081 // We know this entire LHS live range is okay, so skip it now.
1082 if (++LHSIt == LHSEnd) break;
1086 if (LHSIt->end < RHSIt->end) {
1087 if (++LHSIt == LHSEnd) break;
1089 // One interesting case to check here. It's possible that we have
1090 // something like "X3 = Y" which defines a new value number in the LHS,
1091 // and is the last use of this liverange of the RHS. In this case, we
1092 // want to notice this copy (so that it gets coallesced away) even though
1093 // the live ranges don't actually overlap.
1094 if (LHSIt->start == RHSIt->end) {
1095 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
1096 // We already know that this value number is going to be merged in
1097 // if coallescing succeeds. Just skip the liverange.
1098 if (++LHSIt == LHSEnd) break;
1100 // Otherwise, if this is a copy from the RHS, mark it as being merged
1102 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
1103 EliminatedLHSVals.push_back(LHSIt->ValId);
1105 // We know this entire LHS live range is okay, so skip it now.
1106 if (++LHSIt == LHSEnd) break;
1111 if (++RHSIt == RHSEnd) break;
1115 // If we got here, we know that the coallescing will be successful and that
1116 // the value numbers in EliminatedLHSVals will all be merged together. Since
1117 // the most common case is that EliminatedLHSVals has a single number, we
1118 // optimize for it: if there is more than one value, we merge them all into
1119 // the lowest numbered one, then handle the interval as if we were merging
1120 // with one value number.
1122 if (EliminatedLHSVals.size() > 1) {
1123 // Loop through all the equal value numbers merging them into the smallest
1125 unsigned Smallest = EliminatedLHSVals[0];
1126 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1127 if (EliminatedLHSVals[i] < Smallest) {
1128 // Merge the current notion of the smallest into the smaller one.
1129 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1130 Smallest = EliminatedLHSVals[i];
1132 // Merge into the smallest.
1133 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1136 LHSValNo = Smallest;
1138 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1139 LHSValNo = EliminatedLHSVals[0];
1142 // Okay, now that there is a single LHS value number that we're merging the
1143 // RHS into, update the value number info for the LHS to indicate that the
1144 // value number is defined where the RHS value number was.
1145 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1147 // Okay, the final step is to loop over the RHS live intervals, adding them to
1149 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1150 LHS.weight += RHS.weight;
1155 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1156 /// returns false. Otherwise, if one of the intervals being joined is a
1157 /// physreg, this method always canonicalizes LHS to be it. The output
1158 /// "RHS" will not have been modified, so we can use this information
1159 /// below to update aliases.
1160 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1161 // Compute the final value assignment, assuming that the live ranges can be
1163 SmallVector<int, 16> LHSValNoAssignments;
1164 SmallVector<int, 16> RHSValNoAssignments;
1165 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1167 // Compute ultimate value numbers for the LHS and RHS values.
1168 if (RHS.containsOneValue()) {
1169 // Copies from a liveinterval with a single value are simple to handle and
1170 // very common, handle the special case here. This is important, because
1171 // often RHS is small and LHS is large (e.g. a physreg).
1173 // Find out if the RHS is defined as a copy from some value in the LHS.
1175 std::pair<unsigned,unsigned> RHSValNoInfo;
1176 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1177 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1178 // If RHS is not defined as a copy from the LHS, we can use simpler and
1179 // faster checks to see if the live ranges are coallescable. This joiner
1180 // can't swap the LHS/RHS intervals though.
1181 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1182 return SimpleJoin(LHS, RHS);
1184 RHSValNoInfo = RHS.getValNumInfo(0);
1187 // It was defined as a copy from the LHS, find out what value # it is.
1188 unsigned ValInst = RHS.getInstForValNum(0);
1189 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1190 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1193 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1194 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1195 ValueNumberInfo.resize(LHS.getNumValNums());
1197 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1198 // should now get updated.
1199 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1200 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1201 if (rep(LHSSrcReg) != RHS.reg) {
1202 // If this is not a copy from the RHS, its value number will be
1203 // unmodified by the coallescing.
1204 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1205 LHSValNoAssignments[VN] = VN;
1206 } else if (RHSValID == -1) {
1207 // Otherwise, it is a copy from the RHS, and we don't already have a
1208 // value# for it. Keep the current value number, but remember it.
1209 LHSValNoAssignments[VN] = RHSValID = VN;
1210 ValueNumberInfo[VN] = RHSValNoInfo;
1212 // Otherwise, use the specified value #.
1213 LHSValNoAssignments[VN] = RHSValID;
1214 if (VN != (unsigned)RHSValID)
1215 ValueNumberInfo[VN].first = ~1U;
1217 ValueNumberInfo[VN] = RHSValNoInfo;
1220 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1221 LHSValNoAssignments[VN] = VN;
1225 assert(RHSValID != -1 && "Didn't find value #?");
1226 RHSValNoAssignments[0] = RHSValID;
1229 // Loop over the value numbers of the LHS, seeing if any are defined from
1231 SmallVector<int, 16> LHSValsDefinedFromRHS;
1232 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1233 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1234 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1235 if (ValSrcReg == 0) // Src not defined by a copy?
1238 // DstReg is known to be a register in the LHS interval. If the src is
1239 // from the RHS interval, we can use its value #.
1240 if (rep(ValSrcReg) != RHS.reg)
1243 // Figure out the value # from the RHS.
1244 unsigned ValInst = LHS.getInstForValNum(VN);
1245 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1248 // Loop over the value numbers of the RHS, seeing if any are defined from
1250 SmallVector<int, 16> RHSValsDefinedFromLHS;
1251 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1252 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1253 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1254 if (ValSrcReg == 0) // Src not defined by a copy?
1257 // DstReg is known to be a register in the RHS interval. If the src is
1258 // from the LHS interval, we can use its value #.
1259 if (rep(ValSrcReg) != LHS.reg)
1262 // Figure out the value # from the LHS.
1263 unsigned ValInst = RHS.getInstForValNum(VN);
1264 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1267 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1268 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1269 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1271 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1272 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1274 ComputeUltimateVN(VN, ValueNumberInfo,
1275 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1276 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1278 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1279 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1281 // If this value number isn't a copy from the LHS, it's a new number.
1282 if (RHSValsDefinedFromLHS[VN] == -1) {
1283 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1284 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1288 ComputeUltimateVN(VN, ValueNumberInfo,
1289 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1290 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1294 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1295 // interval lists to see if these intervals are coallescable.
1296 LiveInterval::const_iterator I = LHS.begin();
1297 LiveInterval::const_iterator IE = LHS.end();
1298 LiveInterval::const_iterator J = RHS.begin();
1299 LiveInterval::const_iterator JE = RHS.end();
1301 // Skip ahead until the first place of potential sharing.
1302 if (I->start < J->start) {
1303 I = std::upper_bound(I, IE, J->start);
1304 if (I != LHS.begin()) --I;
1305 } else if (J->start < I->start) {
1306 J = std::upper_bound(J, JE, I->start);
1307 if (J != RHS.begin()) --J;
1311 // Determine if these two live ranges overlap.
1313 if (I->start < J->start) {
1314 Overlaps = I->end > J->start;
1316 Overlaps = J->end > I->start;
1319 // If so, check value # info to determine if they are really different.
1321 // If the live range overlap will map to the same value number in the
1322 // result liverange, we can still coallesce them. If not, we can't.
1323 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1327 if (I->end < J->end) {
1336 // If we get here, we know that we can coallesce the live ranges. Ask the
1337 // intervals to coallesce themselves now.
1338 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1345 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1346 // depth of the basic block (the unsigned), and then on the MBB number.
1347 struct DepthMBBCompare {
1348 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1349 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1350 if (LHS.first > RHS.first) return true; // Deeper loops first
1351 return LHS.first == RHS.first &&
1352 LHS.second->getNumber() < RHS.second->getNumber();
1358 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1359 std::vector<CopyRec> &TryAgain) {
1360 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1362 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1364 MachineInstr *Inst = MII++;
1366 // If this isn't a copy, we can't join intervals.
1367 unsigned SrcReg, DstReg;
1368 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1370 if (!JoinCopy(Inst, SrcReg, DstReg))
1371 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
1376 void LiveIntervals::joinIntervals() {
1377 DOUT << "********** JOINING INTERVALS ***********\n";
1379 std::vector<CopyRec> TryAgainList;
1381 const LoopInfo &LI = getAnalysis<LoopInfo>();
1382 if (LI.begin() == LI.end()) {
1383 // If there are no loops in the function, join intervals in function order.
1384 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1386 CopyCoallesceInMBB(I, TryAgainList);
1388 // Otherwise, join intervals in inner loops before other intervals.
1389 // Unfortunately we can't just iterate over loop hierarchy here because
1390 // there may be more MBB's than BB's. Collect MBB's for sorting.
1391 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1392 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1394 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1396 // Sort by loop depth.
1397 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1399 // Finally, join intervals in loop nest order.
1400 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1401 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
1404 // Joining intervals can allow other intervals to be joined. Iteratively join
1405 // until we make no progress.
1406 bool ProgressMade = true;
1407 while (ProgressMade) {
1408 ProgressMade = false;
1410 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1411 CopyRec &TheCopy = TryAgainList[i];
1413 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1414 TheCopy.MI = 0; // Mark this one as done.
1415 ProgressMade = true;
1420 DOUT << "*** Register mapping ***\n";
1421 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1423 DOUT << " reg " << i << " -> ";
1424 DEBUG(printRegName(r2rMap_[i]));
1429 /// Return true if the two specified registers belong to different register
1430 /// classes. The registers may be either phys or virt regs.
1431 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1432 unsigned RegB) const {
1434 // Get the register classes for the first reg.
1435 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1436 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1437 "Shouldn't consider two physregs!");
1438 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1441 // Compare against the regclass for the second reg.
1442 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1443 if (MRegisterInfo::isVirtualRegister(RegB))
1444 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1446 return !RegClass->contains(RegB);
1449 /// hasRegisterUse - Returns true if there is any use of the specific
1450 /// reg between indexes Start and End.
1452 LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) {
1453 for (unsigned Index = Start+InstrSlots::NUM; Index != End;
1454 Index += InstrSlots::NUM) {
1455 // Skip deleted instructions
1456 while (Index != End && !getInstructionFromIndex(Index))
1457 Index += InstrSlots::NUM;
1458 if (Index >= End) break;
1460 MachineInstr *MI = getInstructionFromIndex(Index);
1461 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1462 MachineOperand &MO = MI->getOperand(i);
1463 if (MO.isReg() && MO.isUse() && MO.getReg() &&
1464 mri_->regsOverlap(rep(MO.getReg()), Reg))
1472 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1473 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1475 return LiveInterval(reg, Weight);