1 //===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // LiveIntervalUnion represents a coalesced set of live intervals. This may be
11 // used during coalescing to represent a congruence class, or during register
12 // allocation to model liveness of a physical register.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "LiveIntervalUnion.h"
18 #include "llvm/ADT/SparseBitVector.h"
19 #include "llvm/CodeGen/MachineLoopRanges.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
29 // Merge a LiveInterval's segments. Guarantee no overlaps.
30 void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
35 // Insert each of the virtual register's live segments into the map.
36 LiveInterval::iterator RegPos = VirtReg.begin();
37 LiveInterval::iterator RegEnd = VirtReg.end();
38 SegmentIter SegPos = Segments.find(RegPos->start);
40 while (SegPos.valid()) {
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
42 if (++RegPos == RegEnd)
44 SegPos.advanceTo(RegPos->start);
47 // We have reached the end of Segments, so it is no longer necessary to search
48 // for the insertion position.
49 // It is faster to insert the end first.
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
56 // Remove a live virtual register's segments from this union.
57 void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
62 // Remove each of the virtual register's live segments from the map.
63 LiveInterval::iterator RegPos = VirtReg.begin();
64 LiveInterval::iterator RegEnd = VirtReg.end();
65 SegmentIter SegPos = Segments.find(RegPos->start);
68 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
73 // Skip all segments that may have been coalesced.
74 RegPos = VirtReg.advanceTo(RegPos, SegPos.start());
78 SegPos.advanceTo(RegPos->start);
83 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
84 OS << "LIU " << PrintReg(RepReg, TRI);
89 for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
90 OS << " [" << SI.start() << ' ' << SI.stop() << "):"
91 << PrintReg(SI.value()->reg, TRI);
97 // Verify the live intervals in this union and add them to the visited set.
98 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
99 for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
100 VisitedVRegs.set(SI.value()->reg);
104 // Scan the vector of interfering virtual registers in this union. Assume it's
106 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
107 SmallVectorImpl<LiveInterval*>::const_iterator I =
108 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
109 return I != InterferingVRegs.end();
112 // Collect virtual registers in this union that interfere with this
113 // query's live virtual register.
115 // The query state is one of:
117 // 1. CheckedFirstInterference == false: Iterators are uninitialized.
118 // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
119 // 3. Iterators left at the last seen intersection.
121 unsigned LiveIntervalUnion::Query::
122 collectInterferingVRegs(unsigned MaxInterferingRegs) {
123 // Fast path return if we already have the desired information.
124 if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
125 return InterferingVRegs.size();
127 // Set up iterators on the first call.
128 if (!CheckedFirstInterference) {
129 CheckedFirstInterference = true;
131 // Quickly skip interference check for empty sets.
132 if (VirtReg->empty() || LiveUnion->empty()) {
133 SeenAllInterferences = true;
137 // In most cases, the union will start before VirtReg.
138 VirtRegI = VirtReg->begin();
139 LiveUnionI.setMap(LiveUnion->getMap());
140 LiveUnionI.find(VirtRegI->start);
143 LiveInterval::iterator VirtRegEnd = VirtReg->end();
144 LiveInterval *RecentReg = 0;
145 while (LiveUnionI.valid()) {
146 assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg");
148 // Check for overlapping interference.
149 while (VirtRegI->start < LiveUnionI.stop() &&
150 VirtRegI->end > LiveUnionI.start()) {
151 // This is an overlap, record the interfering register.
152 LiveInterval *VReg = LiveUnionI.value();
153 if (VReg != RecentReg && !isSeenInterference(VReg)) {
155 InterferingVRegs.push_back(VReg);
156 if (InterferingVRegs.size() >= MaxInterferingRegs)
157 return InterferingVRegs.size();
159 // This LiveUnion segment is no longer interesting.
160 if (!(++LiveUnionI).valid()) {
161 SeenAllInterferences = true;
162 return InterferingVRegs.size();
166 // The iterators are now not overlapping, LiveUnionI has been advanced
168 assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap");
170 // Advance the iterator that ends first.
171 VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
172 if (VirtRegI == VirtRegEnd)
175 // Detect overlap, handle above.
176 if (VirtRegI->start < LiveUnionI.stop())
179 // Still not overlapping. Catch up LiveUnionI.
180 LiveUnionI.advanceTo(VirtRegI->start);
182 SeenAllInterferences = true;
183 return InterferingVRegs.size();
186 bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
187 // VirtReg is likely live throughout the loop, so start by checking LIU-Loop
189 IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
190 Overlaps(LiveUnion->getMap(), Loop->getMap());
191 if (!Overlaps.valid())
194 // The loop is overlapping an LIU assignment. Check VirtReg as well.
195 LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
198 if (VRI == VirtReg->end())
200 if (VRI->start < Overlaps.stop())
203 Overlaps.advanceTo(VRI->start);
204 if (!Overlaps.valid())
206 if (Overlaps.start() < VRI->end)
209 VRI = VirtReg->advanceTo(VRI, Overlaps.start());