1 //===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // LiveIntervalUnion represents a coalesced set of live intervals. This may be
11 // used during coalescing to represent a congruence class, or during register
12 // allocation to model liveness of a physical register.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "LiveIntervalUnion.h"
18 #include "llvm/ADT/SparseBitVector.h"
19 #include "llvm/CodeGen/MachineLoopRanges.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
27 // Merge a LiveInterval's segments. Guarantee no overlaps.
28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
33 // Insert each of the virtual register's live segments into the map.
34 LiveInterval::iterator RegPos = VirtReg.begin();
35 LiveInterval::iterator RegEnd = VirtReg.end();
36 SegmentIter SegPos = Segments.find(RegPos->start);
38 while (SegPos.valid()) {
39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
40 if (++RegPos == RegEnd)
42 SegPos.advanceTo(RegPos->start);
45 // We have reached the end of Segments, so it is no longer necessary to search
46 // for the insertion position.
47 // It is faster to insert the end first.
49 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
50 for (; RegPos != RegEnd; ++RegPos, ++SegPos)
51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
54 // Remove a live virtual register's segments from this union.
55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
60 // Remove each of the virtual register's live segments from the map.
61 LiveInterval::iterator RegPos = VirtReg.begin();
62 LiveInterval::iterator RegEnd = VirtReg.end();
63 SegmentIter SegPos = Segments.find(RegPos->start);
66 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
71 // Skip all segments that may have been coalesced.
72 RegPos = VirtReg.advanceTo(RegPos, SegPos.start());
76 SegPos.advanceTo(RegPos->start);
81 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
82 OS << "LIU " << PrintReg(RepReg, TRI);
87 for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
88 OS << " [" << SI.start() << ' ' << SI.stop() << "):"
89 << PrintReg(SI.value()->reg, TRI);
95 // Verify the live intervals in this union and add them to the visited set.
96 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
97 for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
98 VisitedVRegs.set(SI.value()->reg);
102 // Private interface accessed by Query.
104 // Find a pair of segments that intersect, one in the live virtual register
105 // (LiveInterval), and the other in this LiveIntervalUnion. The caller (Query)
106 // is responsible for advancing the LiveIntervalUnion segments to find a
107 // "notable" intersection, which requires query-specific logic.
109 // This design assumes only a fast mechanism for intersecting a single live
110 // virtual register segment with a set of LiveIntervalUnion segments. This may
111 // be ok since most virtual registers have very few segments. If we had a data
112 // structure that optimizd MxN intersection of segments, then we would bypass
113 // the loop that advances within the LiveInterval.
115 // If no intersection exists, set VirtRegI = VirtRegEnd, and set SI to the first
116 // segment whose start point is greater than LiveInterval's end point.
118 // Assumes that segments are sorted by start position in both
119 // LiveInterval and LiveSegments.
120 void LiveIntervalUnion::Query::findIntersection(InterferenceResult &IR) const {
121 // Search until reaching the end of the LiveUnion segments.
122 LiveInterval::iterator VirtRegEnd = VirtReg->end();
123 if (IR.VirtRegI == VirtRegEnd)
125 while (IR.LiveUnionI.valid()) {
126 // Slowly advance the live virtual reg iterator until we surpass the next
127 // segment in LiveUnion.
129 // Note: If this is ever used for coalescing of fixed registers and we have
130 // a live vreg with thousands of segments, then change this code to use
131 // upperBound instead.
132 IR.VirtRegI = VirtReg->advanceTo(IR.VirtRegI, IR.LiveUnionI.start());
133 if (IR.VirtRegI == VirtRegEnd)
134 break; // Retain current (nonoverlapping) LiveUnionI
136 // VirtRegI may have advanced far beyond LiveUnionI, catch up.
137 IR.LiveUnionI.advanceTo(IR.VirtRegI->start);
139 // Check if no LiveUnionI exists with VirtRegI->Start < LiveUnionI.end
140 if (!IR.LiveUnionI.valid())
142 if (IR.LiveUnionI.start() < IR.VirtRegI->end) {
143 assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
144 "upperBound postcondition");
148 if (!IR.LiveUnionI.valid())
149 IR.VirtRegI = VirtRegEnd;
152 // Find the first intersection, and cache interference info
153 // (retain segment iterators into both VirtReg and LiveUnion).
154 const LiveIntervalUnion::InterferenceResult &
155 LiveIntervalUnion::Query::firstInterference() {
156 if (CheckedFirstInterference)
157 return FirstInterference;
158 CheckedFirstInterference = true;
159 InterferenceResult &IR = FirstInterference;
160 IR.LiveUnionI.setMap(LiveUnion->getMap());
162 // Quickly skip interference check for empty sets.
163 if (VirtReg->empty() || LiveUnion->empty()) {
164 IR.VirtRegI = VirtReg->end();
165 } else if (VirtReg->beginIndex() < LiveUnion->startIndex()) {
166 // VirtReg starts first, perform double binary search.
167 IR.VirtRegI = VirtReg->find(LiveUnion->startIndex());
168 if (IR.VirtRegI != VirtReg->end())
169 IR.LiveUnionI.find(IR.VirtRegI->start);
171 // LiveUnion starts first, perform double binary search.
172 IR.LiveUnionI.find(VirtReg->beginIndex());
173 if (IR.LiveUnionI.valid())
174 IR.VirtRegI = VirtReg->find(IR.LiveUnionI.start());
176 IR.VirtRegI = VirtReg->end();
178 findIntersection(FirstInterference);
179 assert((IR.VirtRegI == VirtReg->end() || IR.LiveUnionI.valid())
180 && "Uninitialized iterator");
181 return FirstInterference;
184 // Scan the vector of interfering virtual registers in this union. Assume it's
186 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
187 SmallVectorImpl<LiveInterval*>::const_iterator I =
188 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
189 return I != InterferingVRegs.end();
192 // Count the number of virtual registers in this union that interfere with this
193 // query's live virtual register.
195 // The number of times that we either advance IR.VirtRegI or call
196 // LiveUnion.upperBound() will be no more than the number of holes in
197 // VirtReg. So each invocation of collectInterferingVRegs() takes
198 // time proportional to |VirtReg Holes| * time(LiveUnion.upperBound()).
200 // For comments on how to speed it up, see Query::findIntersection().
201 unsigned LiveIntervalUnion::Query::
202 collectInterferingVRegs(unsigned MaxInterferingRegs) {
203 if (InterferingVRegs.size() >= MaxInterferingRegs)
204 return InterferingVRegs.size();
205 InterferenceResult IR = firstInterference();
206 LiveInterval::iterator VirtRegEnd = VirtReg->end();
207 LiveInterval *RecentInterferingVReg = NULL;
208 if (IR.VirtRegI != VirtRegEnd) while (IR.LiveUnionI.valid()) {
209 // Advance the union's iterator to reach an unseen interfering vreg.
211 if (IR.LiveUnionI.value() == RecentInterferingVReg)
214 if (!isSeenInterference(IR.LiveUnionI.value()))
217 // Cache the most recent interfering vreg to bypass isSeenInterference.
218 RecentInterferingVReg = IR.LiveUnionI.value();
220 } while ((++IR.LiveUnionI).valid());
221 if (!IR.LiveUnionI.valid())
224 // Advance the VirtReg iterator until surpassing the next segment in
226 IR.VirtRegI = VirtReg->advanceTo(IR.VirtRegI, IR.LiveUnionI.start());
227 if (IR.VirtRegI == VirtRegEnd)
230 // Check for intersection with the union's segment.
231 if (overlap(*IR.VirtRegI, IR.LiveUnionI)) {
233 if (!IR.LiveUnionI.value()->isSpillable())
234 SeenUnspillableVReg = true;
236 if (InterferingVRegs.size() == MaxInterferingRegs)
237 // Leave SeenAllInterferences set to false to indicate that at least one
238 // interference exists beyond those we collected.
239 return MaxInterferingRegs;
241 InterferingVRegs.push_back(IR.LiveUnionI.value());
243 // Cache the most recent interfering vreg to bypass isSeenInterference.
244 RecentInterferingVReg = IR.LiveUnionI.value();
249 // VirtRegI may have advanced far beyond LiveUnionI,
250 // do a fast intersection test to "catch up"
251 IR.LiveUnionI.advanceTo(IR.VirtRegI->start);
253 SeenAllInterferences = true;
254 return InterferingVRegs.size();
257 bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
258 // VirtReg is likely live throughout the loop, so start by checking LIU-Loop
260 IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
261 Overlaps(LiveUnion->getMap(), Loop->getMap());
262 if (!Overlaps.valid())
265 // The loop is overlapping an LIU assignment. Check VirtReg as well.
266 LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
269 if (VRI == VirtReg->end())
271 if (VRI->start < Overlaps.stop())
274 Overlaps.advanceTo(VRI->start);
275 if (!Overlaps.valid())
277 if (Overlaps.start() < VRI->end)
280 VRI = VirtReg->advanceTo(VRI, Overlaps.start());