1 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
14 #include "LiveRangeEdit.h"
15 #include "VirtRegMap.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
25 LiveInterval &LiveRangeEdit::create(MachineRegisterInfo &mri,
28 const TargetRegisterClass *RC = mri.getRegClass(getReg());
29 unsigned VReg = mri.createVirtualRegister(RC);
31 vrm.setIsSplitFromReg(VReg, vrm.getOriginal(getReg()));
32 LiveInterval &li = lis.getOrCreateInterval(VReg);
33 newRegs_.push_back(&li);
37 void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
38 const TargetInstrInfo &tii,
40 for (LiveInterval::vni_iterator I = parent_.vni_begin(),
41 E = parent_.vni_end(); I != E; ++I) {
45 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
48 if (tii.isTriviallyReMaterializable(DefMI, aa))
49 remattable_.insert(VNI);
51 scannedRemattable_ = true;
54 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
55 const TargetInstrInfo &tii,
57 if (!scannedRemattable_)
58 scanRemattable(lis, tii, aa);
59 return !remattable_.empty();
62 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
63 /// OrigIdx are also available with the same value at UseIdx.
64 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
68 OrigIdx = OrigIdx.getUseIndex();
69 UseIdx = UseIdx.getUseIndex();
70 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
71 const MachineOperand &MO = OrigMI->getOperand(i);
72 if (!MO.isReg() || !MO.getReg() || MO.getReg() == getReg())
74 // Reserved registers are OK.
75 if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
77 // We don't want to move any defs.
80 // We cannot depend on virtual registers in uselessRegs_.
82 for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
83 if ((*uselessRegs_)[ui]->reg == MO.getReg())
86 LiveInterval &li = lis.getInterval(MO.getReg());
87 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
90 if (OVNI != li.getVNInfoAt(UseIdx))
96 bool LiveRangeEdit::canRematerializeAt(Remat &RM,
100 assert(scannedRemattable_ && "Call anyRematerializable first");
102 // Use scanRemattable info.
103 if (!remattable_.count(RM.ParentVNI))
106 // No defining instruction.
107 RM.OrigMI = lis.getInstructionFromIndex(RM.ParentVNI->def);
108 assert(RM.OrigMI && "Defining instruction for remattable value disappeared");
110 // If only cheap remats were requested, bail out early.
111 if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
114 // Verify that all used registers are available with the same values.
115 if (!allUsesAvailableAt(RM.OrigMI, RM.ParentVNI->def, UseIdx, lis))
121 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator MI,
126 const TargetInstrInfo &tii,
127 const TargetRegisterInfo &tri) {
128 assert(RM.OrigMI && "Invalid remat");
129 tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
130 rematted_.insert(RM.ParentVNI);
131 return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
134 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
135 if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
136 LIS.removeInterval(Reg);
139 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
141 const TargetInstrInfo &TII) {
142 SetVector<LiveInterval*,
143 SmallVector<LiveInterval*, 8>,
144 SmallPtrSet<LiveInterval*, 8> > ToShrink;
147 // Erase all dead defs.
148 while (!Dead.empty()) {
149 MachineInstr *MI = Dead.pop_back_val();
150 assert(MI->allDefsAreDead() && "Def isn't really dead");
151 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
153 // Never delete inline asm.
154 if (MI->isInlineAsm()) {
155 DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
159 // Use the same criteria as DeadMachineInstructionElim.
160 bool SawStore = false;
161 if (!MI->isSafeToMove(&TII, 0, SawStore)) {
162 DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
166 DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
168 // Check for live intervals that may shrink
169 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
170 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
173 unsigned Reg = MOI->getReg();
174 if (!TargetRegisterInfo::isVirtualRegister(Reg))
176 LiveInterval &LI = LIS.getInterval(Reg);
178 // Shrink read registers.
179 if (MI->readsVirtualRegister(Reg))
180 ToShrink.insert(&LI);
182 // Remove defined value.
184 if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
187 ToShrink.remove(&LI);
188 eraseVirtReg(Reg, LIS);
195 delegate_->LRE_WillEraseInstruction(MI);
196 LIS.RemoveMachineInstrFromMaps(MI);
197 MI->eraseFromParent();
200 if (ToShrink.empty())
203 // Shrink just one live interval. Then delete new dead defs.
204 LiveInterval *LI = ToShrink.back();
207 delegate_->LRE_WillShrinkVirtReg(LI->reg);
208 LIS.shrinkToUses(LI, &Dead);