1 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "LiveRangeEdit.h"
16 #include "VirtRegMap.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/CodeGen/CalcSpillWeights.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
27 LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg,
30 MachineRegisterInfo &MRI = VRM.getRegInfo();
31 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
33 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
34 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
35 newRegs_.push_back(&LI);
39 void LiveRangeEdit::checkRematerializable(VNInfo *VNI,
40 const MachineInstr *DefMI,
41 const TargetInstrInfo &tii,
43 assert(DefMI && "Missing instruction");
44 if (tii.isTriviallyReMaterializable(DefMI, aa))
45 remattable_.insert(VNI);
46 scannedRemattable_ = true;
49 void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
50 const TargetInstrInfo &tii,
52 for (LiveInterval::vni_iterator I = parent_.vni_begin(),
53 E = parent_.vni_end(); I != E; ++I) {
57 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
60 checkRematerializable(VNI, DefMI, tii, aa);
64 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
65 const TargetInstrInfo &tii,
67 if (!scannedRemattable_)
68 scanRemattable(lis, tii, aa);
69 return !remattable_.empty();
72 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
73 /// OrigIdx are also available with the same value at UseIdx.
74 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
78 OrigIdx = OrigIdx.getUseIndex();
79 UseIdx = UseIdx.getUseIndex();
80 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
81 const MachineOperand &MO = OrigMI->getOperand(i);
82 if (!MO.isReg() || !MO.getReg() || MO.isDef())
84 // Reserved registers are OK.
85 if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
87 // We cannot depend on virtual registers in uselessRegs_.
89 for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
90 if ((*uselessRegs_)[ui]->reg == MO.getReg())
93 LiveInterval &li = lis.getInterval(MO.getReg());
94 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
97 if (OVNI != li.getVNInfoAt(UseIdx))
103 bool LiveRangeEdit::canRematerializeAt(Remat &RM,
106 LiveIntervals &lis) {
107 assert(scannedRemattable_ && "Call anyRematerializable first");
109 // Use scanRemattable info.
110 if (!remattable_.count(RM.ParentVNI))
113 // No defining instruction provided.
116 DefIdx = lis.getInstructionIndex(RM.OrigMI);
118 DefIdx = RM.ParentVNI->def;
119 RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
120 assert(RM.OrigMI && "No defining instruction for remattable value");
123 // If only cheap remats were requested, bail out early.
124 if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
127 // Verify that all used registers are available with the same values.
128 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
134 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator MI,
139 const TargetInstrInfo &tii,
140 const TargetRegisterInfo &tri) {
141 assert(RM.OrigMI && "Invalid remat");
142 tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
143 rematted_.insert(RM.ParentVNI);
144 return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
147 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
148 if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
149 LIS.removeInterval(Reg);
152 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
153 SmallVectorImpl<MachineInstr*> &Dead,
154 MachineRegisterInfo &MRI,
156 const TargetInstrInfo &TII) {
157 MachineInstr *DefMI = 0, *UseMI = 0;
159 // Check that there is a single def and a single use.
160 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
161 E = MRI.reg_nodbg_end(); I != E; ++I) {
162 MachineOperand &MO = I.getOperand();
163 MachineInstr *MI = MO.getParent();
165 if (DefMI && DefMI != MI)
167 if (!MI->getDesc().canFoldAsLoad())
170 } else if (!MO.isUndef()) {
171 if (UseMI && UseMI != MI)
173 // FIXME: Targets don't know how to fold subreg uses.
179 if (!DefMI || !UseMI)
182 DEBUG(dbgs() << "Try to fold single def: " << *DefMI
183 << " into single use: " << *UseMI);
185 SmallVector<unsigned, 8> Ops;
186 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
189 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
192 DEBUG(dbgs() << " folded: " << *FoldMI);
193 LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
194 UseMI->eraseFromParent();
195 DefMI->addRegisterDead(LI->reg, 0);
196 Dead.push_back(DefMI);
200 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
201 LiveIntervals &LIS, VirtRegMap &VRM,
202 const TargetInstrInfo &TII) {
203 SetVector<LiveInterval*,
204 SmallVector<LiveInterval*, 8>,
205 SmallPtrSet<LiveInterval*, 8> > ToShrink;
208 // Erase all dead defs.
209 while (!Dead.empty()) {
210 MachineInstr *MI = Dead.pop_back_val();
211 assert(MI->allDefsAreDead() && "Def isn't really dead");
212 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
214 // Never delete inline asm.
215 if (MI->isInlineAsm()) {
216 DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
220 // Use the same criteria as DeadMachineInstructionElim.
221 bool SawStore = false;
222 if (!MI->isSafeToMove(&TII, 0, SawStore)) {
223 DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
227 DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
229 // Check for live intervals that may shrink
230 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
231 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
234 unsigned Reg = MOI->getReg();
235 if (!TargetRegisterInfo::isVirtualRegister(Reg))
237 LiveInterval &LI = LIS.getInterval(Reg);
239 // Shrink read registers.
240 if (MI->readsVirtualRegister(Reg))
241 ToShrink.insert(&LI);
243 // Remove defined value.
245 if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
247 delegate_->LRE_WillShrinkVirtReg(LI.reg);
250 ToShrink.remove(&LI);
251 eraseVirtReg(Reg, LIS);
258 delegate_->LRE_WillEraseInstruction(MI);
259 LIS.RemoveMachineInstrFromMaps(MI);
260 MI->eraseFromParent();
263 if (ToShrink.empty())
266 // Shrink just one live interval. Then delete new dead defs.
267 LiveInterval *LI = ToShrink.back();
269 if (foldAsLoad(LI, Dead, VRM.getRegInfo(), LIS, TII))
272 delegate_->LRE_WillShrinkVirtReg(LI->reg);
273 if (!LIS.shrinkToUses(LI, &Dead))
276 // LI may have been separated, create new intervals.
277 LI->RenumberValues(LIS);
278 ConnectedVNInfoEqClasses ConEQ(LIS);
279 unsigned NumComp = ConEQ.Classify(LI);
282 DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
283 SmallVector<LiveInterval*, 8> Dups(1, LI);
284 for (unsigned i = 1; i != NumComp; ++i) {
285 Dups.push_back(&createFrom(LI->reg, LIS, VRM));
287 delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
289 ConEQ.Distribute(&Dups[0], VRM.getRegInfo());
293 void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
295 const MachineLoopInfo &Loops) {
296 VirtRegAuxInfo VRAI(MF, LIS, Loops);
297 for (iterator I = begin(), E = end(); I != E; ++I) {
298 LiveInterval &LI = **I;
299 VRAI.CalculateRegClass(LI.reg);
300 VRAI.CalculateWeightAndHint(LI);