1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
13 // The parent register is never changed. Instead, a number of new virtual
14 // registers are created and added to the newRegs vector.
16 //===----------------------------------------------------------------------===//
18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
19 #define LLVM_CODEGEN_LIVERANGEEDIT_H
21 #include "llvm/CodeGen/LiveInterval.h"
22 #include "llvm/ADT/SmallPtrSet.h"
28 class MachineLoopInfo;
29 class MachineRegisterInfo;
34 /// Callback methods for LiveRangeEdit owners.
36 /// Called immediately before erasing a dead machine instruction.
37 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
39 /// Called when a virtual register is no longer used. Return false to defer
40 /// its deletion from LiveIntervals.
41 virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
43 /// Called before shrinking the live range of a virtual register.
44 virtual void LRE_WillShrinkVirtReg(unsigned) {}
46 virtual ~Delegate() {}
50 LiveInterval &parent_;
51 SmallVectorImpl<LiveInterval*> &newRegs_;
52 Delegate *const delegate_;
53 const SmallVectorImpl<LiveInterval*> *uselessRegs_;
55 /// firstNew_ - Index of the first register added to newRegs_.
56 const unsigned firstNew_;
58 /// scannedRemattable_ - true when remattable values have been identified.
59 bool scannedRemattable_;
61 /// remattable_ - Values defined by remattable instructions as identified by
62 /// tii.isTriviallyReMaterializable().
63 SmallPtrSet<const VNInfo*,4> remattable_;
65 /// rematted_ - Values that were actually rematted, and so need to have their
66 /// live range trimmed or entirely removed.
67 SmallPtrSet<const VNInfo*,4> rematted_;
69 /// scanRemattable - Identify the parent_ values that may rematerialize.
70 void scanRemattable(LiveIntervals &lis,
71 const TargetInstrInfo &tii,
74 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
75 /// OrigIdx are also available with the same value at UseIdx.
76 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
77 SlotIndex UseIdx, LiveIntervals &lis);
80 /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
81 /// @param parent The register being spilled or split.
82 /// @param newRegs List to receive any new registers created. This needn't be
83 /// empty initially, any existing registers are ignored.
84 /// @param uselessRegs List of registers that can't be used when
85 /// rematerializing values because they are about to be removed.
86 LiveRangeEdit(LiveInterval &parent,
87 SmallVectorImpl<LiveInterval*> &newRegs,
88 Delegate *delegate = 0,
89 const SmallVectorImpl<LiveInterval*> *uselessRegs = 0)
90 : parent_(parent), newRegs_(newRegs),
92 uselessRegs_(uselessRegs),
93 firstNew_(newRegs.size()),
94 scannedRemattable_(false) {}
96 LiveInterval &getParent() const { return parent_; }
97 unsigned getReg() const { return parent_.reg; }
99 /// Iterator for accessing the new registers added by this edit.
100 typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
101 iterator begin() const { return newRegs_.begin()+firstNew_; }
102 iterator end() const { return newRegs_.end(); }
103 unsigned size() const { return newRegs_.size()-firstNew_; }
104 bool empty() const { return size() == 0; }
105 LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
107 /// FIXME: Temporary accessors until we can get rid of
108 /// LiveIntervals::AddIntervalsForSpills
109 SmallVectorImpl<LiveInterval*> *getNewVRegs() { return &newRegs_; }
110 const SmallVectorImpl<LiveInterval*> *getUselessVRegs() {
114 /// createFrom - Create a new virtual register based on OldReg.
115 LiveInterval &createFrom(unsigned OldReg, LiveIntervals&, VirtRegMap&);
117 /// create - Create a new register with the same class and original slot as
119 LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {
120 return createFrom(getReg(), LIS, VRM);
123 /// anyRematerializable - Return true if any parent values may be
124 /// rematerializable.
125 /// This function must be called before any rematerialization is attempted.
126 bool anyRematerializable(LiveIntervals&, const TargetInstrInfo&,
129 /// checkRematerializable - Manually add VNI to the list of rematerializable
130 /// values if DefMI may be rematerializable.
131 void checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
132 const TargetInstrInfo&, AliasAnalysis*);
134 /// Remat - Information needed to rematerialize at a specific location.
136 VNInfo *ParentVNI; // parent_'s value at the remat location.
137 MachineInstr *OrigMI; // Instruction defining ParentVNI.
138 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
141 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
142 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
143 /// When cheapAsAMove is set, only cheap remats are allowed.
144 bool canRematerializeAt(Remat &RM,
149 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
150 /// instruction into MBB before MI. The new instruction is mapped, but
151 /// liveness is not updated.
152 /// Return the SlotIndex of the new instruction.
153 SlotIndex rematerializeAt(MachineBasicBlock &MBB,
154 MachineBasicBlock::iterator MI,
158 const TargetInstrInfo&,
159 const TargetRegisterInfo&);
161 /// markRematerialized - explicitly mark a value as rematerialized after doing
163 void markRematerialized(const VNInfo *ParentVNI) {
164 rematted_.insert(ParentVNI);
167 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
168 bool didRematerialize(const VNInfo *ParentVNI) const {
169 return rematted_.count(ParentVNI);
172 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
173 /// to erase it from LIS.
174 void eraseVirtReg(unsigned Reg, LiveIntervals &LIS);
176 /// eliminateDeadDefs - Try to delete machine instructions that are now dead
177 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
178 /// and further dead efs to be eliminated.
179 void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
180 LiveIntervals&, VirtRegMap&,
181 const TargetInstrInfo&);
183 /// calculateRegClassAndHint - Recompute register class and hint for each new
185 void calculateRegClassAndHint(MachineFunction&, LiveIntervals&,
186 const MachineLoopInfo&);