1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/CFG.h"
34 #include "Support/DepthFirstIterator.h"
38 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
40 const std::pair<MachineBasicBlock*, unsigned> &
41 LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{
42 return BBMap.find(MBB->getBasicBlock())->second;
45 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
46 assert(RegIdx >= MRegisterInfo::FirstVirtualRegister &&
47 "getVarInfo: not a virtual register!");
48 RegIdx -= MRegisterInfo::FirstVirtualRegister;
49 if (RegIdx >= VirtRegInfo.size()) {
50 if (RegIdx >= 2*VirtRegInfo.size())
51 VirtRegInfo.resize(RegIdx*2);
53 VirtRegInfo.resize(2*VirtRegInfo.size());
55 return VirtRegInfo[RegIdx];
60 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
61 const BasicBlock *BB) {
62 const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
63 MachineBasicBlock *MBB = Info.first;
64 unsigned BBNum = Info.second;
66 // Check to see if this basic block is one of the killing blocks. If so,
68 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
69 if (VRInfo.Kills[i].first == MBB) {
70 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
74 if (MBB == VRInfo.DefBlock) return; // Terminate recursion
76 if (VRInfo.AliveBlocks.size() <= BBNum)
77 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
79 if (VRInfo.AliveBlocks[BBNum])
80 return; // We already know the block is live
82 // Mark the variable known alive in this bb
83 VRInfo.AliveBlocks[BBNum] = true;
85 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
86 MarkVirtRegAliveInBlock(VRInfo, *PI);
89 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
91 // Check to see if this basic block is already a kill block...
92 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
93 // Yes, this register is killed in this basic block already. Increase the
94 // live range by updating the kill instruction.
95 VRInfo.Kills.back().second = MI;
100 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
101 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
104 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
106 // Add a new kill entry for this basic block.
107 VRInfo.Kills.push_back(std::make_pair(MBB, MI));
109 // Update all dominating blocks to mark them known live.
110 const BasicBlock *BB = MBB->getBasicBlock();
111 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB);
113 MarkVirtRegAliveInBlock(VRInfo, *PI);
116 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
117 if (PhysRegInfo[Reg]) {
118 PhysRegInfo[Reg] = MI;
119 PhysRegUsed[Reg] = true;
121 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
122 *AliasSet; ++AliasSet) {
123 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
124 PhysRegInfo[*AliasSet] = MI;
125 PhysRegUsed[*AliasSet] = true;
131 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
132 // Does this kill a previous version of this register?
133 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
134 if (PhysRegUsed[Reg])
135 RegistersKilled.insert(std::make_pair(LastUse, Reg));
137 RegistersDead.insert(std::make_pair(LastUse, Reg));
139 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
140 *AliasSet; ++AliasSet) {
141 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
142 if (PhysRegUsed[*AliasSet])
143 RegistersKilled.insert(std::make_pair(LastUse, *AliasSet));
145 RegistersDead.insert(std::make_pair(LastUse, *AliasSet));
146 PhysRegInfo[*AliasSet] = 0; // Kill the aliased register
150 PhysRegInfo[Reg] = MI;
151 PhysRegUsed[Reg] = false;
154 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
155 // First time though, initialize AllocatablePhysicalRegisters for the target
156 if (AllocatablePhysicalRegisters.empty()) {
157 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
158 assert(&MRI && "Target doesn't have register information?");
160 // Make space, initializing to false...
161 AllocatablePhysicalRegisters.resize(MRegisterInfo::FirstVirtualRegister);
163 // Loop over all of the register classes...
164 for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(),
165 E = MRI.regclass_end(); RCI != E; ++RCI)
166 // Loop over all of the allocatable registers in the function...
167 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
168 E = (*RCI)->allocation_order_end(MF); I != E; ++I)
169 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
174 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
175 BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++);
177 // PhysRegInfo - Keep track of which instruction was the last use of a
178 // physical register. This is a purely local property, because all physical
179 // register references as presumed dead across basic blocks.
181 MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
182 bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
183 std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
185 PhysRegInfo = PhysRegInfoA;
186 PhysRegUsed = PhysRegUsedA;
188 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
189 RegInfo = MF.getTarget().getRegisterInfo();
191 /// Get some space for a respectable number of registers...
192 VirtRegInfo.resize(64);
194 // Calculate live variable information in depth first order on the CFG of the
195 // function. This guarantees that we will see the definition of a virtual
196 // register before its uses due to dominance properties of SSA (except for PHI
197 // nodes, which are treated as a special case).
199 const BasicBlock *Entry = MF.getFunction()->begin();
200 for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
202 const BasicBlock *BB = *DFI;
203 std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second;
204 MachineBasicBlock *MBB = BBRec.first;
205 unsigned BBNum = BBRec.second;
207 // Loop over all of the instructions, processing them.
208 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
210 MachineInstr *MI = *I;
211 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
213 // Process all of the operands of the instruction...
214 unsigned NumOperandsToProcess = MI->getNumOperands();
216 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
217 // of the uses. They will be handled in other basic blocks.
218 if (MI->getOpcode() == TargetInstrInfo::PHI)
219 NumOperandsToProcess = 1;
221 // Loop over implicit uses, using them.
222 for (const unsigned *ImplicitUses = MID.ImplicitUses;
223 *ImplicitUses; ++ImplicitUses)
224 HandlePhysRegUse(*ImplicitUses, MI);
226 // Process all explicit uses...
227 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
229 if (MO.opIsUse() || MO.opIsDefAndUse()) {
230 if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
231 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
232 } else if (MO.isPhysicalRegister() &&
233 AllocatablePhysicalRegisters[MO.getReg()]) {
234 HandlePhysRegUse(MO.getReg(), MI);
239 // Loop over implicit defs, defining them.
240 for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
241 *ImplicitDefs; ++ImplicitDefs)
242 HandlePhysRegDef(*ImplicitDefs, MI);
244 // Process all explicit defs...
245 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
246 MachineOperand &MO = MI->getOperand(i);
247 if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
248 if (MO.isVirtualRegister()) {
249 VarInfo &VRInfo = getVarInfo(MO.getReg());
251 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
252 VRInfo.DefBlock = MBB; // Created here...
254 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
255 } else if (MO.isPhysicalRegister() &&
256 AllocatablePhysicalRegisters[MO.getReg()]) {
257 HandlePhysRegDef(MO.getReg(), MI);
263 // Handle any virtual assignments from PHI nodes which might be at the
264 // bottom of this basic block. We check all of our successor blocks to see
265 // if they have PHI nodes, and if so, we simulate an assignment at the end
266 // of the current block.
267 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB);
269 MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
271 // PHI nodes are guaranteed to be at the top of the block...
272 for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
273 I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
274 MachineInstr *MI = *I;
275 for (unsigned i = 1; ; i += 2)
276 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
277 MachineOperand &MO = MI->getOperand(i);
278 if (!MO.getVRegValueOrNull()) {
279 VarInfo &VRInfo = getVarInfo(MO.getReg());
281 // Only mark it alive only in the block we are representing...
282 MarkVirtRegAliveInBlock(VRInfo, BB);
283 break; // Found the PHI entry for this block...
289 // Loop over PhysRegInfo, killing any registers that are available at the
290 // end of the basic block. This also resets the PhysRegInfo map.
291 for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i)
293 HandlePhysRegDef(i, 0);
296 // Convert the information we have gathered into VirtRegInfo and transform it
297 // into a form usable by RegistersKilled.
299 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
300 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
301 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
302 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
303 i + MRegisterInfo::FirstVirtualRegister));
306 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
307 i + MRegisterInfo::FirstVirtualRegister));
313 } // End llvm namespace