1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/MRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Config/alloca.h"
41 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
43 void LiveVariables::VarInfo::dump() const {
44 std::cerr << "Register Defined by: ";
46 std::cerr << *DefInst;
48 std::cerr << "<null>\n";
49 std::cerr << " Alive in blocks: ";
50 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
51 if (AliveBlocks[i]) std::cerr << i << ", ";
52 std::cerr << "\n Killed by:";
54 std::cerr << " No instructions.\n";
56 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
57 std::cerr << "\n #" << i << ": " << *Kills[i];
62 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
63 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
64 "getVarInfo: not a virtual register!");
65 RegIdx -= MRegisterInfo::FirstVirtualRegister;
66 if (RegIdx >= VirtRegInfo.size()) {
67 if (RegIdx >= 2*VirtRegInfo.size())
68 VirtRegInfo.resize(RegIdx*2);
70 VirtRegInfo.resize(2*VirtRegInfo.size());
72 return VirtRegInfo[RegIdx];
75 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
76 std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
77 RegistersKilled.find(MI);
78 if (I == RegistersKilled.end()) return false;
80 // Do a binary search, as these lists can grow pretty big, particularly for
81 // call instructions on targets with lots of call-clobbered registers.
82 return std::binary_search(I->second.begin(), I->second.end(), Reg);
85 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
86 std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
87 RegistersDead.find(MI);
88 if (I == RegistersDead.end()) return false;
90 // Do a binary search, as these lists can grow pretty big, particularly for
91 // call instructions on targets with lots of call-clobbered registers.
92 return std::binary_search(I->second.begin(), I->second.end(), Reg);
95 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
96 MachineBasicBlock *MBB) {
97 unsigned BBNum = MBB->getNumber();
99 // Check to see if this basic block is one of the killing blocks. If so,
101 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
102 if (VRInfo.Kills[i]->getParent() == MBB) {
103 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
107 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
109 if (VRInfo.AliveBlocks.size() <= BBNum)
110 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
112 if (VRInfo.AliveBlocks[BBNum])
113 return; // We already know the block is live
115 // Mark the variable known alive in this bb
116 VRInfo.AliveBlocks[BBNum] = true;
118 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
119 E = MBB->pred_end(); PI != E; ++PI)
120 MarkVirtRegAliveInBlock(VRInfo, *PI);
123 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
125 assert(VRInfo.DefInst && "Register use before def!");
127 // Check to see if this basic block is already a kill block...
128 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
129 // Yes, this register is killed in this basic block already. Increase the
130 // live range by updating the kill instruction.
131 VRInfo.Kills.back() = MI;
136 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
137 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
140 assert(MBB != VRInfo.DefInst->getParent() &&
141 "Should have kill for defblock!");
143 // Add a new kill entry for this basic block.
144 VRInfo.Kills.push_back(MI);
146 // Update all dominating blocks to mark them known live.
147 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
148 E = MBB->pred_end(); PI != E; ++PI)
149 MarkVirtRegAliveInBlock(VRInfo, *PI);
152 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
153 PhysRegInfo[Reg] = MI;
154 PhysRegUsed[Reg] = true;
156 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
157 unsigned Alias = *AliasSet; ++AliasSet) {
158 PhysRegInfo[Alias] = MI;
159 PhysRegUsed[Alias] = true;
163 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
164 // Does this kill a previous version of this register?
165 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
166 if (PhysRegUsed[Reg])
167 RegistersKilled[LastUse].push_back(Reg);
169 RegistersDead[LastUse].push_back(Reg);
171 PhysRegInfo[Reg] = MI;
172 PhysRegUsed[Reg] = false;
174 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
175 unsigned Alias = *AliasSet; ++AliasSet) {
176 if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
177 if (PhysRegUsed[Alias])
178 RegistersKilled[LastUse].push_back(Alias);
180 RegistersDead[LastUse].push_back(Alias);
182 PhysRegInfo[Alias] = MI;
183 PhysRegUsed[Alias] = false;
187 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
188 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
189 RegInfo = MF.getTarget().getRegisterInfo();
190 assert(RegInfo && "Target doesn't have register information?");
192 AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
194 // PhysRegInfo - Keep track of which instruction was the last use of a
195 // physical register. This is a purely local property, because all physical
196 // register references as presumed dead across basic blocks.
198 PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
199 RegInfo->getNumRegs());
200 PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
201 std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
203 /// Get some space for a respectable number of registers...
204 VirtRegInfo.resize(64);
206 // Mark live-in registers as live-in.
207 for (MachineFunction::livein_iterator I = MF.livein_begin(),
208 E = MF.livein_end(); I != E; ++I) {
209 assert(MRegisterInfo::isPhysicalRegister(I->first) &&
210 "Cannot have a live-in virtual register!");
211 HandlePhysRegDef(I->first, 0);
216 // Calculate live variable information in depth first order on the CFG of the
217 // function. This guarantees that we will see the definition of a virtual
218 // register before its uses due to dominance properties of SSA (except for PHI
219 // nodes, which are treated as a special case).
221 MachineBasicBlock *Entry = MF.begin();
222 std::set<MachineBasicBlock*> Visited;
223 for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
224 E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
225 MachineBasicBlock *MBB = *DFI;
226 unsigned BBNum = MBB->getNumber();
228 // Loop over all of the instructions, processing them.
229 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
231 MachineInstr *MI = I;
232 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
234 // Process all of the operands of the instruction...
235 unsigned NumOperandsToProcess = MI->getNumOperands();
237 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
238 // of the uses. They will be handled in other basic blocks.
239 if (MI->getOpcode() == TargetInstrInfo::PHI)
240 NumOperandsToProcess = 1;
242 // Loop over implicit uses, using them.
243 if (MID.ImplicitUses) {
244 for (const unsigned *ImplicitUses = MID.ImplicitUses;
245 *ImplicitUses; ++ImplicitUses)
246 HandlePhysRegUse(*ImplicitUses, MI);
249 // Process all explicit uses...
250 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
251 MachineOperand &MO = MI->getOperand(i);
252 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
253 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
254 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
255 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
256 AllocatablePhysicalRegisters[MO.getReg()]) {
257 HandlePhysRegUse(MO.getReg(), MI);
262 // Loop over implicit defs, defining them.
263 if (MID.ImplicitDefs) {
264 for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
265 *ImplicitDefs; ++ImplicitDefs)
266 HandlePhysRegDef(*ImplicitDefs, MI);
269 // Process all explicit defs...
270 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
271 MachineOperand &MO = MI->getOperand(i);
272 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
273 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
274 VarInfo &VRInfo = getVarInfo(MO.getReg());
276 assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
279 VRInfo.Kills.push_back(MI);
280 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
281 AllocatablePhysicalRegisters[MO.getReg()]) {
282 HandlePhysRegDef(MO.getReg(), MI);
288 // Handle any virtual assignments from PHI nodes which might be at the
289 // bottom of this basic block. We check all of our successor blocks to see
290 // if they have PHI nodes, and if so, we simulate an assignment at the end
291 // of the current block.
292 if (!PHIVarInfo[MBB].empty()) {
293 std::vector<unsigned>& VarInfoVec = PHIVarInfo[MBB];
295 for (std::vector<unsigned>::iterator I = VarInfoVec.begin(),
296 E = VarInfoVec.end(); I != E; ++I) {
297 VarInfo& VRInfo = getVarInfo(*I);
298 assert(VRInfo.DefInst && "Register use before def (or no def)!");
300 // Only mark it alive only in the block we are representing.
301 MarkVirtRegAliveInBlock(VRInfo, MBB);
305 // Finally, if the last block in the function is a return, make sure to mark
306 // it as using all of the live-out values in the function.
307 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
308 MachineInstr *Ret = &MBB->back();
309 for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
310 E = MF.liveout_end(); I != E; ++I) {
311 assert(MRegisterInfo::isPhysicalRegister(*I) &&
312 "Cannot have a live-in virtual register!");
313 HandlePhysRegUse(*I, Ret);
317 // Loop over PhysRegInfo, killing any registers that are available at the
318 // end of the basic block. This also resets the PhysRegInfo map.
319 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
321 HandlePhysRegDef(i, 0);
324 // Convert the information we have gathered into VirtRegInfo and transform it
325 // into a form usable by RegistersKilled.
327 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
328 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
329 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
330 RegistersDead[VirtRegInfo[i].Kills[j]].push_back(
331 i + MRegisterInfo::FirstVirtualRegister);
334 RegistersKilled[VirtRegInfo[i].Kills[j]].push_back(
335 i + MRegisterInfo::FirstVirtualRegister);
338 // Walk through the RegistersKilled/Dead sets, and sort the registers killed
339 // or dead. This allows us to use efficient binary search for membership
341 for (std::map<MachineInstr*, std::vector<unsigned> >::iterator
342 I = RegistersKilled.begin(), E = RegistersKilled.end(); I != E; ++I)
343 std::sort(I->second.begin(), I->second.end());
344 for (std::map<MachineInstr*, std::vector<unsigned> >::iterator
345 I = RegistersDead.begin(), E = RegistersDead.end(); I != E; ++I)
346 std::sort(I->second.begin(), I->second.end());
348 // Check to make sure there are no unreachable blocks in the MC CFG for the
349 // function. If so, it is due to a bug in the instruction selector or some
350 // other part of the code generator if this happens.
352 for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
353 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
360 /// instructionChanged - When the address of an instruction changes, this
361 /// method should be called so that live variables can update its internal
362 /// data structures. This removes the records for OldMI, transfering them to
363 /// the records for NewMI.
364 void LiveVariables::instructionChanged(MachineInstr *OldMI,
365 MachineInstr *NewMI) {
366 // If the instruction defines any virtual registers, update the VarInfo for
368 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
369 MachineOperand &MO = OldMI->getOperand(i);
370 if (MO.isRegister() && MO.getReg() &&
371 MRegisterInfo::isVirtualRegister(MO.getReg())) {
372 unsigned Reg = MO.getReg();
373 VarInfo &VI = getVarInfo(Reg);
375 // Update the defining instruction.
376 if (VI.DefInst == OldMI)
380 // If this is a kill of the value, update the VI kills list.
381 if (VI.removeKill(OldMI))
382 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
387 // Move the killed information over...
388 killed_iterator I, E;
389 tie(I, E) = killed_range(OldMI);
391 std::vector<unsigned> &V = RegistersKilled[NewMI];
392 bool WasEmpty = V.empty();
393 V.insert(V.end(), I, E);
395 std::sort(V.begin(), V.end()); // Keep the reg list sorted.
396 RegistersKilled.erase(OldMI);
399 // Move the dead information over...
400 tie(I, E) = dead_range(OldMI);
402 std::vector<unsigned> &V = RegistersDead[NewMI];
403 bool WasEmpty = V.empty();
404 V.insert(V.end(), I, E);
406 std::sort(V.begin(), V.end()); // Keep the reg list sorted.
407 RegistersDead.erase(OldMI);
411 /// removeVirtualRegistersKilled - Remove all killed info for the specified
413 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
414 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
415 RegistersKilled.find(MI);
416 if (I == RegistersKilled.end()) return;
418 std::vector<unsigned> &Regs = I->second;
419 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
420 if (MRegisterInfo::isVirtualRegister(Regs[i])) {
421 bool removed = getVarInfo(Regs[i]).removeKill(MI);
422 assert(removed && "kill not in register's VarInfo?");
425 RegistersKilled.erase(I);
428 /// removeVirtualRegistersDead - Remove all of the dead registers for the
429 /// specified instruction from the live variable information.
430 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
431 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
432 RegistersDead.find(MI);
433 if (I == RegistersDead.end()) return;
435 std::vector<unsigned> &Regs = I->second;
436 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
437 if (MRegisterInfo::isVirtualRegister(Regs[i])) {
438 bool removed = getVarInfo(Regs[i]).removeKill(MI);
439 assert(removed && "kill not in register's VarInfo?");
442 RegistersDead.erase(I);
445 /// analyzePHINodes - Gather information about the PHI nodes in here. In
446 /// particular, we want to map the variable information of a virtual
447 /// register which is used in a PHI node. We map that to the BB the vreg is
450 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
451 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
453 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
454 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
455 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
456 PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()].
457 push_back(BBI->getOperand(i).getReg());