1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/ADT/DepthFirstIterator.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/STLExtras.h"
44 char LiveVariables::ID = 0;
45 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
48 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
49 AU.addRequiredID(UnreachableMachineBlockElimID);
51 MachineFunctionPass::getAnalysisUsage(AU);
55 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
56 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
57 if (Kills[i]->getParent() == MBB)
62 void LiveVariables::VarInfo::dump() const {
63 dbgs() << " Alive in blocks: ";
64 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
65 E = AliveBlocks.end(); I != E; ++I)
67 dbgs() << "\n Killed by:";
69 dbgs() << " No instructions.\n";
71 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
72 dbgs() << "\n #" << i << ": " << *Kills[i];
77 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
78 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
79 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
80 "getVarInfo: not a virtual register!");
81 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
82 if (RegIdx >= VirtRegInfo.size()) {
83 if (RegIdx >= 2*VirtRegInfo.size())
84 VirtRegInfo.resize(RegIdx*2);
86 VirtRegInfo.resize(2*VirtRegInfo.size());
88 return VirtRegInfo[RegIdx];
91 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
92 MachineBasicBlock *DefBlock,
93 MachineBasicBlock *MBB,
94 std::vector<MachineBasicBlock*> &WorkList) {
95 unsigned BBNum = MBB->getNumber();
97 // Check to see if this basic block is one of the killing blocks. If so,
99 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
100 if (VRInfo.Kills[i]->getParent() == MBB) {
101 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
105 if (MBB == DefBlock) return; // Terminate recursion
107 if (VRInfo.AliveBlocks.test(BBNum))
108 return; // We already know the block is live
110 // Mark the variable known alive in this bb
111 VRInfo.AliveBlocks.set(BBNum);
113 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
114 E = MBB->pred_rend(); PI != E; ++PI)
115 WorkList.push_back(*PI);
118 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
119 MachineBasicBlock *DefBlock,
120 MachineBasicBlock *MBB) {
121 std::vector<MachineBasicBlock*> WorkList;
122 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
124 while (!WorkList.empty()) {
125 MachineBasicBlock *Pred = WorkList.back();
127 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
131 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
133 assert(MRI->getVRegDef(reg) && "Register use before def!");
135 unsigned BBNum = MBB->getNumber();
137 VarInfo& VRInfo = getVarInfo(reg);
140 // Check to see if this basic block is already a kill block.
141 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
142 // Yes, this register is killed in this basic block already. Increase the
143 // live range by updating the kill instruction.
144 VRInfo.Kills.back() = MI;
149 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
150 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
153 // This situation can occur:
158 // | t2 = phi ... t1 ...
162 // | ... = ... t1 ...
166 // where there is a use in a PHI node that's a predecessor to the defining
167 // block. We don't want to mark all predecessors as having the value "alive"
169 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
171 // Add a new kill entry for this basic block. If this virtual register is
172 // already marked as alive in this basic block, that means it is alive in at
173 // least one of the successor blocks, it's not a kill.
174 if (!VRInfo.AliveBlocks.test(BBNum))
175 VRInfo.Kills.push_back(MI);
177 // Update all dominating blocks to mark them as "known live".
178 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
179 E = MBB->pred_end(); PI != E; ++PI)
180 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
183 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
184 VarInfo &VRInfo = getVarInfo(Reg);
186 if (VRInfo.AliveBlocks.empty())
187 // If vr is not alive in any block, then defaults to dead.
188 VRInfo.Kills.push_back(MI);
191 /// FindLastPartialDef - Return the last partial def of the specified register.
192 /// Also returns the sub-registers that're defined by the instruction.
193 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
194 SmallSet<unsigned,4> &PartDefRegs) {
195 unsigned LastDefReg = 0;
196 unsigned LastDefDist = 0;
197 MachineInstr *LastDef = NULL;
198 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
199 unsigned SubReg = *SubRegs; ++SubRegs) {
200 MachineInstr *Def = PhysRegDef[SubReg];
203 unsigned Dist = DistanceMap[Def];
204 if (Dist > LastDefDist) {
214 PartDefRegs.insert(LastDefReg);
215 for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
216 MachineOperand &MO = LastDef->getOperand(i);
217 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
219 unsigned DefReg = MO.getReg();
220 if (TRI->isSubRegister(Reg, DefReg)) {
221 PartDefRegs.insert(DefReg);
222 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
223 unsigned SubReg = *SubRegs; ++SubRegs)
224 PartDefRegs.insert(SubReg);
230 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
231 /// implicit defs to a machine instruction if there was an earlier def of its
233 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
234 MachineInstr *LastDef = PhysRegDef[Reg];
235 // If there was a previous use or a "full" def all is well.
236 if (!LastDef && !PhysRegUse[Reg]) {
237 // Otherwise, the last sub-register def implicitly defines this register.
240 // AL = ... <imp-def EAX>, <imp-kill AH>
244 // All of the sub-registers must have been defined before the use of Reg!
245 SmallSet<unsigned, 4> PartDefRegs;
246 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
247 // If LastPartialDef is NULL, it must be using a livein register.
248 if (LastPartialDef) {
249 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
251 PhysRegDef[Reg] = LastPartialDef;
252 SmallSet<unsigned, 8> Processed;
253 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
254 unsigned SubReg = *SubRegs; ++SubRegs) {
255 if (Processed.count(SubReg))
257 if (PartDefRegs.count(SubReg))
259 // This part of Reg was defined before the last partial def. It's killed
261 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
264 PhysRegDef[SubReg] = LastPartialDef;
265 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
266 Processed.insert(*SS);
270 else if (LastDef && !PhysRegUse[Reg] &&
271 !LastDef->findRegisterDefOperand(Reg))
272 // Last def defines the super register, add an implicit def of reg.
273 LastDef->addOperand(MachineOperand::CreateReg(Reg,
274 true/*IsDef*/, true/*IsImp*/));
276 // Remember this use.
277 PhysRegUse[Reg] = MI;
278 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
279 unsigned SubReg = *SubRegs; ++SubRegs)
280 PhysRegUse[SubReg] = MI;
283 /// FindLastRefOrPartRef - Return the last reference or partial reference of
284 /// the specified register.
285 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
286 MachineInstr *LastDef = PhysRegDef[Reg];
287 MachineInstr *LastUse = PhysRegUse[Reg];
288 if (!LastDef && !LastUse)
291 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
292 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
293 MachineInstr *LastPartDef = 0;
294 unsigned LastPartDefDist = 0;
295 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
296 unsigned SubReg = *SubRegs; ++SubRegs) {
297 MachineInstr *Def = PhysRegDef[SubReg];
298 if (Def && Def != LastDef) {
299 // There was a def of this sub-register in between. This is a partial
300 // def, keep track of the last one.
301 unsigned Dist = DistanceMap[Def];
302 if (Dist > LastPartDefDist) {
303 LastPartDefDist = Dist;
308 if (MachineInstr *Use = PhysRegUse[SubReg]) {
309 unsigned Dist = DistanceMap[Use];
310 if (Dist > LastRefOrPartRefDist) {
311 LastRefOrPartRefDist = Dist;
312 LastRefOrPartRef = Use;
317 return LastRefOrPartRef;
320 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
321 MachineInstr *LastDef = PhysRegDef[Reg];
322 MachineInstr *LastUse = PhysRegUse[Reg];
323 if (!LastDef && !LastUse)
326 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
327 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
328 // The whole register is used.
333 // = AL, AX<imp-use, kill>
336 // Or whole register is defined, but not used at all.
341 // Or whole register is defined, but only partly used.
342 // AX<dead> = AL<imp-def>
345 MachineInstr *LastPartDef = 0;
346 unsigned LastPartDefDist = 0;
347 SmallSet<unsigned, 8> PartUses;
348 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
349 unsigned SubReg = *SubRegs; ++SubRegs) {
350 MachineInstr *Def = PhysRegDef[SubReg];
351 if (Def && Def != LastDef) {
352 // There was a def of this sub-register in between. This is a partial
353 // def, keep track of the last one.
354 unsigned Dist = DistanceMap[Def];
355 if (Dist > LastPartDefDist) {
356 LastPartDefDist = Dist;
361 if (MachineInstr *Use = PhysRegUse[SubReg]) {
362 PartUses.insert(SubReg);
363 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
364 PartUses.insert(*SS);
365 unsigned Dist = DistanceMap[Use];
366 if (Dist > LastRefOrPartRefDist) {
367 LastRefOrPartRefDist = Dist;
368 LastRefOrPartRef = Use;
373 if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
375 // The last partial def kills the register.
376 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
377 true/*IsImp*/, true/*IsKill*/));
380 LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
381 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
382 // If the last reference is the last def, then it's not used at all.
383 // That is, unless we are currently processing the last reference itself.
384 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
386 // If we are adding a subreg def and the superreg def is marked early
387 // clobber, add an early clobber marker to the subreg def.
388 MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
390 MO->setIsEarlyClobber();
393 } else if (!PhysRegUse[Reg]) {
394 // Partial uses. Mark register def dead and add implicit def of
395 // sub-registers which are used.
396 // EAX<dead> = op AL<imp-def>
397 // That is, EAX def is dead but AL def extends pass it.
398 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
399 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
400 unsigned SubReg = *SubRegs; ++SubRegs) {
401 if (!PartUses.count(SubReg))
404 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
405 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
408 assert(!MO->isDead());
412 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
413 true/*IsDef*/, true/*IsImp*/));
414 MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
416 LastSubRef->addRegisterKilled(SubReg, TRI, true);
418 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
419 PhysRegUse[SubReg] = LastRefOrPartRef;
420 for (const unsigned *SSRegs = TRI->getSubRegisters(SubReg);
421 unsigned SSReg = *SSRegs; ++SSRegs)
422 PhysRegUse[SSReg] = LastRefOrPartRef;
424 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
428 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
432 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
433 SmallVector<unsigned, 4> &Defs) {
434 // What parts of the register are previously defined?
435 SmallSet<unsigned, 32> Live;
436 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
438 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
441 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
442 unsigned SubReg = *SubRegs; ++SubRegs) {
443 // If a register isn't itself defined, but all parts that make up of it
444 // are defined, then consider it also defined.
449 if (Live.count(SubReg))
451 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
453 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
459 // Start from the largest piece, find the last time any part of the register
461 HandlePhysRegKill(Reg, MI);
462 // Only some of the sub-registers are used.
463 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
464 unsigned SubReg = *SubRegs; ++SubRegs) {
465 if (!Live.count(SubReg))
466 // Skip if this sub-register isn't defined.
468 HandlePhysRegKill(SubReg, MI);
472 Defs.push_back(Reg); // Remember this def.
475 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
476 SmallVector<unsigned, 4> &Defs) {
477 while (!Defs.empty()) {
478 unsigned Reg = Defs.back();
480 PhysRegDef[Reg] = MI;
481 PhysRegUse[Reg] = NULL;
482 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
483 unsigned SubReg = *SubRegs; ++SubRegs) {
484 PhysRegDef[SubReg] = MI;
485 PhysRegUse[SubReg] = NULL;
492 const TargetRegisterInfo *TRI;
494 RegSorter(const TargetRegisterInfo *tri) : TRI(tri) { }
495 bool operator()(unsigned A, unsigned B) {
496 if (TRI->isSubRegister(A, B))
498 else if (TRI->isSubRegister(B, A))
505 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
507 MRI = &mf.getRegInfo();
508 TRI = MF->getTarget().getRegisterInfo();
510 ReservedRegisters = TRI->getReservedRegs(mf);
512 unsigned NumRegs = TRI->getNumRegs();
513 PhysRegDef = new MachineInstr*[NumRegs];
514 PhysRegUse = new MachineInstr*[NumRegs];
515 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
516 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
517 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
519 /// Get some space for a respectable number of registers.
520 VirtRegInfo.resize(64);
524 // Calculate live variable information in depth first order on the CFG of the
525 // function. This guarantees that we will see the definition of a virtual
526 // register before its uses due to dominance properties of SSA (except for PHI
527 // nodes, which are treated as a special case).
528 MachineBasicBlock *Entry = MF->begin();
529 SmallPtrSet<MachineBasicBlock*,16> Visited;
531 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
532 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
534 MachineBasicBlock *MBB = *DFI;
536 // Mark live-in registers as live-in.
537 SmallVector<unsigned, 4> Defs;
538 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
539 EE = MBB->livein_end(); II != EE; ++II) {
540 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
541 "Cannot have a live-in virtual register!");
542 HandlePhysRegDef(*II, 0, Defs);
545 // Loop over all of the instructions, processing them.
548 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
550 MachineInstr *MI = I;
551 DistanceMap.insert(std::make_pair(MI, Dist++));
553 // Process all of the operands of the instruction...
554 unsigned NumOperandsToProcess = MI->getNumOperands();
556 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
557 // of the uses. They will be handled in other basic blocks.
558 if (MI->getOpcode() == TargetInstrInfo::PHI)
559 NumOperandsToProcess = 1;
561 SmallVector<unsigned, 4> UseRegs;
562 SmallVector<unsigned, 4> DefRegs;
563 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
564 const MachineOperand &MO = MI->getOperand(i);
565 if (!MO.isReg() || MO.getReg() == 0)
567 unsigned MOReg = MO.getReg();
569 UseRegs.push_back(MOReg);
571 DefRegs.push_back(MOReg);
575 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
576 unsigned MOReg = UseRegs[i];
577 if (TargetRegisterInfo::isVirtualRegister(MOReg))
578 HandleVirtRegUse(MOReg, MBB, MI);
579 else if (!ReservedRegisters[MOReg])
580 HandlePhysRegUse(MOReg, MI);
584 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
585 unsigned MOReg = DefRegs[i];
586 if (TargetRegisterInfo::isVirtualRegister(MOReg))
587 HandleVirtRegDef(MOReg, MI);
588 else if (!ReservedRegisters[MOReg])
589 HandlePhysRegDef(MOReg, MI, Defs);
591 UpdatePhysRegDefs(MI, Defs);
594 // Handle any virtual assignments from PHI nodes which might be at the
595 // bottom of this basic block. We check all of our successor blocks to see
596 // if they have PHI nodes, and if so, we simulate an assignment at the end
597 // of the current block.
598 if (!PHIVarInfo[MBB->getNumber()].empty()) {
599 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
601 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
602 E = VarInfoVec.end(); I != E; ++I)
603 // Mark it alive only in the block we are representing.
604 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
608 // Finally, if the last instruction in the block is a return, make sure to
609 // mark it as using all of the live-out values in the function.
610 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
611 MachineInstr *Ret = &MBB->back();
613 for (MachineRegisterInfo::liveout_iterator
614 I = MF->getRegInfo().liveout_begin(),
615 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
616 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
617 "Cannot have a live-out virtual register!");
618 HandlePhysRegUse(*I, Ret);
620 // Add live-out registers as implicit uses.
621 if (!Ret->readsRegister(*I))
622 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
626 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
627 // available at the end of the basic block.
628 for (unsigned i = 0; i != NumRegs; ++i)
629 if (PhysRegDef[i] || PhysRegUse[i])
630 HandlePhysRegDef(i, 0, Defs);
632 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
633 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
636 // Convert and transfer the dead / killed information we have gathered into
637 // VirtRegInfo onto MI's.
638 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
639 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
640 if (VirtRegInfo[i].Kills[j] ==
641 MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
643 .Kills[j]->addRegisterDead(i +
644 TargetRegisterInfo::FirstVirtualRegister,
648 .Kills[j]->addRegisterKilled(i +
649 TargetRegisterInfo::FirstVirtualRegister,
652 // Check to make sure there are no unreachable blocks in the MC CFG for the
653 // function. If so, it is due to a bug in the instruction selector or some
654 // other part of the code generator if this happens.
656 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
657 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
667 /// replaceKillInstruction - Update register kill info by replacing a kill
668 /// instruction with a new one.
669 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
670 MachineInstr *NewMI) {
671 VarInfo &VI = getVarInfo(Reg);
672 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
675 /// removeVirtualRegistersKilled - Remove all killed info for the specified
677 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
678 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
679 MachineOperand &MO = MI->getOperand(i);
680 if (MO.isReg() && MO.isKill()) {
682 unsigned Reg = MO.getReg();
683 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
684 bool removed = getVarInfo(Reg).removeKill(MI);
685 assert(removed && "kill not in register's VarInfo?");
692 /// analyzePHINodes - Gather information about the PHI nodes in here. In
693 /// particular, we want to map the variable information of a virtual register
694 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
696 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
697 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
699 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
700 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
701 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
702 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
703 .push_back(BBI->getOperand(i).getReg());
706 bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
708 MachineRegisterInfo &MRI) {
709 unsigned Num = MBB.getNumber();
711 // Reg is live-through.
712 if (AliveBlocks.test(Num))
715 // Registers defined in MBB cannot be live in.
716 const MachineInstr *Def = MRI.getVRegDef(Reg);
717 if (Def && Def->getParent() == &MBB)
720 // Reg was not defined in MBB, was it killed here?
721 return findKill(&MBB);
724 bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
725 LiveVariables::VarInfo &VI = getVarInfo(Reg);
727 // Loop over all of the successors of the basic block, checking to see if
728 // the value is either live in the block, or if it is killed in the block.
729 std::vector<MachineBasicBlock*> OpSuccBlocks;
730 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
731 E = MBB.succ_end(); SI != E; ++SI) {
732 MachineBasicBlock *SuccMBB = *SI;
734 // Is it alive in this successor?
735 unsigned SuccIdx = SuccMBB->getNumber();
736 if (VI.AliveBlocks.test(SuccIdx))
738 OpSuccBlocks.push_back(SuccMBB);
741 // Check to see if this value is live because there is a use in a successor
743 switch (OpSuccBlocks.size()) {
745 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
746 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
747 if (VI.Kills[i]->getParent() == SuccMBB)
752 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
753 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
754 if (VI.Kills[i]->getParent() == SuccMBB1 ||
755 VI.Kills[i]->getParent() == SuccMBB2)
760 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
761 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
762 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
763 VI.Kills[i]->getParent()))
769 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
770 /// variables that are live out of DomBB will be marked as passing live through
772 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
773 MachineBasicBlock *DomBB,
774 MachineBasicBlock *SuccBB) {
775 const unsigned NumNew = BB->getNumber();
777 // All registers used by PHI nodes in SuccBB must be live through BB.
778 for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(),
780 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
781 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
782 if (BBI->getOperand(i+1).getMBB() == BB)
783 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
785 // Update info for all live variables
786 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
787 E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) {
788 VarInfo &VI = getVarInfo(Reg);
789 if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
790 VI.AliveBlocks.set(NumNew);