1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/STLExtras.h"
43 char LiveVariables::ID = 0;
44 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
47 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
48 AU.addRequiredID(UnreachableMachineBlockElimID);
50 MachineFunctionPass::getAnalysisUsage(AU);
53 void LiveVariables::VarInfo::dump() const {
54 errs() << " Alive in blocks: ";
55 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
56 E = AliveBlocks.end(); I != E; ++I)
58 errs() << "\n Killed by:";
60 errs() << " No instructions.\n";
62 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
63 errs() << "\n #" << i << ": " << *Kills[i];
68 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
69 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
70 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
71 "getVarInfo: not a virtual register!");
72 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
73 if (RegIdx >= VirtRegInfo.size()) {
74 if (RegIdx >= 2*VirtRegInfo.size())
75 VirtRegInfo.resize(RegIdx*2);
77 VirtRegInfo.resize(2*VirtRegInfo.size());
79 return VirtRegInfo[RegIdx];
82 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
83 MachineBasicBlock *DefBlock,
84 MachineBasicBlock *MBB,
85 std::vector<MachineBasicBlock*> &WorkList) {
86 unsigned BBNum = MBB->getNumber();
88 // Check to see if this basic block is one of the killing blocks. If so,
90 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
91 if (VRInfo.Kills[i]->getParent() == MBB) {
92 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
96 if (MBB == DefBlock) return; // Terminate recursion
98 if (VRInfo.AliveBlocks.test(BBNum))
99 return; // We already know the block is live
101 // Mark the variable known alive in this bb
102 VRInfo.AliveBlocks.set(BBNum);
104 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
105 E = MBB->pred_rend(); PI != E; ++PI)
106 WorkList.push_back(*PI);
109 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
110 MachineBasicBlock *DefBlock,
111 MachineBasicBlock *MBB) {
112 std::vector<MachineBasicBlock*> WorkList;
113 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
115 while (!WorkList.empty()) {
116 MachineBasicBlock *Pred = WorkList.back();
118 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
122 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
124 assert(MRI->getVRegDef(reg) && "Register use before def!");
126 unsigned BBNum = MBB->getNumber();
128 VarInfo& VRInfo = getVarInfo(reg);
131 // Check to see if this basic block is already a kill block.
132 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
133 // Yes, this register is killed in this basic block already. Increase the
134 // live range by updating the kill instruction.
135 VRInfo.Kills.back() = MI;
140 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
141 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
144 // This situation can occur:
149 // | t2 = phi ... t1 ...
153 // | ... = ... t1 ...
157 // where there is a use in a PHI node that's a predecessor to the defining
158 // block. We don't want to mark all predecessors as having the value "alive"
160 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
162 // Add a new kill entry for this basic block. If this virtual register is
163 // already marked as alive in this basic block, that means it is alive in at
164 // least one of the successor blocks, it's not a kill.
165 if (!VRInfo.AliveBlocks.test(BBNum))
166 VRInfo.Kills.push_back(MI);
168 // Update all dominating blocks to mark them as "known live".
169 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
170 E = MBB->pred_end(); PI != E; ++PI)
171 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
174 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
175 VarInfo &VRInfo = getVarInfo(Reg);
177 if (VRInfo.AliveBlocks.empty())
178 // If vr is not alive in any block, then defaults to dead.
179 VRInfo.Kills.push_back(MI);
182 /// FindLastPartialDef - Return the last partial def of the specified register.
183 /// Also returns the sub-registers that're defined by the instruction.
184 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
185 SmallSet<unsigned,4> &PartDefRegs) {
186 unsigned LastDefReg = 0;
187 unsigned LastDefDist = 0;
188 MachineInstr *LastDef = NULL;
189 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
190 unsigned SubReg = *SubRegs; ++SubRegs) {
191 MachineInstr *Def = PhysRegDef[SubReg];
194 unsigned Dist = DistanceMap[Def];
195 if (Dist > LastDefDist) {
205 PartDefRegs.insert(LastDefReg);
206 for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
207 MachineOperand &MO = LastDef->getOperand(i);
208 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
210 unsigned DefReg = MO.getReg();
211 if (TRI->isSubRegister(Reg, DefReg)) {
212 PartDefRegs.insert(DefReg);
213 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
214 unsigned SubReg = *SubRegs; ++SubRegs)
215 PartDefRegs.insert(SubReg);
221 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
222 /// implicit defs to a machine instruction if there was an earlier def of its
224 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
225 // If there was a previous use or a "full" def all is well.
226 if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) {
227 // Otherwise, the last sub-register def implicitly defines this register.
230 // AL = ... <imp-def EAX>, <imp-kill AH>
234 // All of the sub-registers must have been defined before the use of Reg!
235 SmallSet<unsigned, 4> PartDefRegs;
236 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
237 // If LastPartialDef is NULL, it must be using a livein register.
238 if (LastPartialDef) {
239 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
241 PhysRegDef[Reg] = LastPartialDef;
242 SmallSet<unsigned, 8> Processed;
243 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
244 unsigned SubReg = *SubRegs; ++SubRegs) {
245 if (Processed.count(SubReg))
247 if (PartDefRegs.count(SubReg))
249 // This part of Reg was defined before the last partial def. It's killed
251 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
254 PhysRegDef[SubReg] = LastPartialDef;
255 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
256 Processed.insert(*SS);
261 // Remember this use.
262 PhysRegUse[Reg] = MI;
263 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
264 unsigned SubReg = *SubRegs; ++SubRegs)
265 PhysRegUse[SubReg] = MI;
268 /// hasRegisterUseBelow - Return true if the specified register is used after
269 /// the current instruction and before it's next definition.
270 bool LiveVariables::hasRegisterUseBelow(unsigned Reg,
271 MachineBasicBlock::iterator I,
272 MachineBasicBlock *MBB) {
276 // First find out if there are any uses / defs below.
277 bool hasDistInfo = true;
278 unsigned CurDist = DistanceMap[I];
279 SmallVector<MachineInstr*, 4> Uses;
280 SmallVector<MachineInstr*, 4> Defs;
281 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
282 RE = MRI->reg_end(); RI != RE; ++RI) {
283 MachineOperand &UDO = RI.getOperand();
284 MachineInstr *UDMI = &*RI;
285 if (UDMI->getParent() != MBB)
287 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
288 bool isBelow = false;
289 if (DI == DistanceMap.end()) {
290 // Must be below if it hasn't been assigned a distance yet.
293 } else if (DI->second > CurDist)
297 Uses.push_back(UDMI);
299 Defs.push_back(UDMI);
306 else if (!Uses.empty() && Defs.empty())
307 // There are uses below but no defs below.
309 // There are both uses and defs below. We need to know which comes first.
311 // Complete DistanceMap for this MBB. This information is computed only
315 for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I, ++CurDist)
316 DistanceMap.insert(std::make_pair(I, CurDist));
319 unsigned EarliestUse = DistanceMap[Uses[0]];
320 for (unsigned i = 1, e = Uses.size(); i != e; ++i) {
321 unsigned Dist = DistanceMap[Uses[i]];
322 if (Dist < EarliestUse)
325 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
326 unsigned Dist = DistanceMap[Defs[i]];
327 if (Dist < EarliestUse)
328 // The register is defined before its first use below.
334 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
335 if (!PhysRegUse[Reg] && !PhysRegDef[Reg])
338 MachineInstr *LastRefOrPartRef = PhysRegUse[Reg]
339 ? PhysRegUse[Reg] : PhysRegDef[Reg];
340 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
341 // The whole register is used.
346 // = AL, AX<imp-use, kill>
349 // Or whole register is defined, but not used at all.
354 // Or whole register is defined, but only partly used.
355 // AX<dead> = AL<imp-def>
358 SmallSet<unsigned, 8> PartUses;
359 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
360 unsigned SubReg = *SubRegs; ++SubRegs) {
361 if (MachineInstr *Use = PhysRegUse[SubReg]) {
362 PartUses.insert(SubReg);
363 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
364 PartUses.insert(*SS);
365 unsigned Dist = DistanceMap[Use];
366 if (Dist > LastRefOrPartRefDist) {
367 LastRefOrPartRefDist = Dist;
368 LastRefOrPartRef = Use;
373 if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI)
374 // If the last reference is the last def, then it's not used at all.
375 // That is, unless we are currently processing the last reference itself.
376 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
378 // Partial uses. Mark register def dead and add implicit def of
379 // sub-registers which are used.
380 // EAX<dead> = op AL<imp-def>
381 // That is, EAX def is dead but AL def extends pass it.
382 // Enable this after live interval analysis is fixed to improve codegen!
383 else if (!PhysRegUse[Reg]) {
384 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
385 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
386 unsigned SubReg = *SubRegs; ++SubRegs) {
387 if (PartUses.count(SubReg)) {
389 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
390 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
393 assert(!MO->isDead());
397 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
399 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
400 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
406 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
410 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
411 SmallVector<unsigned, 4> &Defs,
412 SmallVector<unsigned, 4> &SuperDefs) {
413 // What parts of the register are previously defined?
414 SmallSet<unsigned, 32> Live;
415 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
417 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
420 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
421 unsigned SubReg = *SubRegs; ++SubRegs) {
422 // If a register isn't itself defined, but all parts that make up of it
423 // are defined, then consider it also defined.
428 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
430 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
436 // Start from the largest piece, find the last time any part of the register
438 if (!HandlePhysRegKill(Reg, MI)) {
439 // Only some of the sub-registers are used.
440 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
441 unsigned SubReg = *SubRegs; ++SubRegs) {
442 if (!Live.count(SubReg))
443 // Skip if this sub-register isn't defined.
445 if (HandlePhysRegKill(SubReg, MI)) {
447 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
451 assert(Live.empty() && "Not all defined registers are killed / dead?");
455 // Does this extend the live range of a super-register?
456 SmallSet<unsigned, 8> Processed;
457 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
458 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
459 if (Processed.count(SuperReg))
461 MachineInstr *LastRef = PhysRegUse[SuperReg]
462 ? PhysRegUse[SuperReg] : PhysRegDef[SuperReg];
463 if (LastRef && LastRef != MI) {
464 // The larger register is previously defined. Now a smaller part is
465 // being re-defined. Treat it as read/mod/write if there are uses
468 // AX = EAX<imp-use,kill>, EAX<imp-def>
471 SuperDefs.push_back(SuperReg);
472 Processed.insert(SuperReg);
473 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS)
474 Processed.insert(*SS);
478 // Remember this def.
483 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
484 SmallVector<unsigned, 4> &Defs) {
485 while (!Defs.empty()) {
486 unsigned Reg = Defs.back();
488 PhysRegDef[Reg] = MI;
489 PhysRegUse[Reg] = NULL;
490 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
491 unsigned SubReg = *SubRegs; ++SubRegs) {
492 PhysRegDef[SubReg] = MI;
493 PhysRegUse[SubReg] = NULL;
500 const TargetRegisterInfo *TRI;
502 RegSorter(const TargetRegisterInfo *tri) : TRI(tri) { }
503 bool operator()(unsigned A, unsigned B) {
504 if (TRI->isSubRegister(A, B))
506 else if (TRI->isSubRegister(B, A))
513 void LiveVariables::UpdateSuperRegDefs(MachineInstr *MI,
514 SmallVector<unsigned, 4> &SuperDefs) {
515 // This instruction has defined part of some registers. If there are no
516 // more uses below MI, then the last use / def becomes kill / dead.
517 if (SuperDefs.empty())
521 std::sort(SuperDefs.begin(), SuperDefs.end(), RS);
522 SmallSet<unsigned, 4> Processed;
523 for (unsigned j = 0, ee = SuperDefs.size(); j != ee; ++j) {
524 unsigned SuperReg = SuperDefs[j];
525 if (!Processed.insert(SuperReg))
527 if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
528 // Previous use / def is not the last use / dead def. It's now
529 // partially re-defined.
530 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
531 true/*IsImp*/,true/*IsKill*/));
532 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
534 PhysRegDef[SuperReg] = MI;
535 PhysRegUse[SuperReg] = NULL;
536 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
537 Processed.insert(*SS);
538 PhysRegDef[*SS] = MI;
539 PhysRegUse[*SS] = NULL;
542 // Previous use / def is kill / dead. It's not being re-defined.
543 HandlePhysRegKill(SuperReg, MI);
544 PhysRegDef[SuperReg] = 0;
545 PhysRegUse[SuperReg] = NULL;
546 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
547 Processed.insert(*SS);
548 if (PhysRegDef[*SS] == MI)
549 continue; // This instruction may have defined it.
550 PhysRegDef[*SS] = MI;
551 PhysRegUse[*SS] = NULL;
558 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
560 MRI = &mf.getRegInfo();
561 TRI = MF->getTarget().getRegisterInfo();
563 ReservedRegisters = TRI->getReservedRegs(mf);
565 unsigned NumRegs = TRI->getNumRegs();
566 PhysRegDef = new MachineInstr*[NumRegs];
567 PhysRegUse = new MachineInstr*[NumRegs];
568 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
569 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
570 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
572 /// Get some space for a respectable number of registers.
573 VirtRegInfo.resize(64);
577 // Calculate live variable information in depth first order on the CFG of the
578 // function. This guarantees that we will see the definition of a virtual
579 // register before its uses due to dominance properties of SSA (except for PHI
580 // nodes, which are treated as a special case).
581 MachineBasicBlock *Entry = MF->begin();
582 SmallPtrSet<MachineBasicBlock*,16> Visited;
584 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
585 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
587 MachineBasicBlock *MBB = *DFI;
589 // Mark live-in registers as live-in.
590 SmallVector<unsigned, 4> Defs;
591 SmallVector<unsigned, 4> SuperDefs;
592 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
593 EE = MBB->livein_end(); II != EE; ++II) {
594 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
595 "Cannot have a live-in virtual register!");
596 HandlePhysRegDef(*II, 0, Defs, SuperDefs);
597 UpdatePhysRegDefs(0, Defs);
601 // Loop over all of the instructions, processing them.
604 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
606 MachineInstr *MI = I;
607 DistanceMap.insert(std::make_pair(MI, Dist++));
609 // Process all of the operands of the instruction...
610 unsigned NumOperandsToProcess = MI->getNumOperands();
612 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
613 // of the uses. They will be handled in other basic blocks.
614 if (MI->getOpcode() == TargetInstrInfo::PHI)
615 NumOperandsToProcess = 1;
617 SmallVector<unsigned, 4> UseRegs;
618 SmallVector<unsigned, 4> DefRegs;
619 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
620 const MachineOperand &MO = MI->getOperand(i);
621 if (!MO.isReg() || MO.getReg() == 0)
623 unsigned MOReg = MO.getReg();
625 UseRegs.push_back(MOReg);
627 DefRegs.push_back(MOReg);
631 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
632 unsigned MOReg = UseRegs[i];
633 if (TargetRegisterInfo::isVirtualRegister(MOReg))
634 HandleVirtRegUse(MOReg, MBB, MI);
635 else if (!ReservedRegisters[MOReg])
636 HandlePhysRegUse(MOReg, MI);
640 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
641 unsigned MOReg = DefRegs[i];
642 if (TargetRegisterInfo::isVirtualRegister(MOReg))
643 HandleVirtRegDef(MOReg, MI);
644 else if (!ReservedRegisters[MOReg]) {
645 HandlePhysRegDef(MOReg, MI, Defs, SuperDefs);
649 UpdateSuperRegDefs(MI, SuperDefs);
650 UpdatePhysRegDefs(MI, Defs);
653 // Handle any virtual assignments from PHI nodes which might be at the
654 // bottom of this basic block. We check all of our successor blocks to see
655 // if they have PHI nodes, and if so, we simulate an assignment at the end
656 // of the current block.
657 if (!PHIVarInfo[MBB->getNumber()].empty()) {
658 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
660 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
661 E = VarInfoVec.end(); I != E; ++I)
662 // Mark it alive only in the block we are representing.
663 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
667 // Finally, if the last instruction in the block is a return, make sure to
668 // mark it as using all of the live-out values in the function.
669 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
670 MachineInstr *Ret = &MBB->back();
672 for (MachineRegisterInfo::liveout_iterator
673 I = MF->getRegInfo().liveout_begin(),
674 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
675 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
676 "Cannot have a live-out virtual register!");
677 HandlePhysRegUse(*I, Ret);
679 // Add live-out registers as implicit uses.
680 if (!Ret->readsRegister(*I))
681 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
685 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
686 // available at the end of the basic block.
687 for (unsigned i = 0; i != NumRegs; ++i)
688 if (PhysRegDef[i] || PhysRegUse[i]) {
689 HandlePhysRegDef(i, 0, Defs, SuperDefs);
690 UpdatePhysRegDefs(0, Defs);
694 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
695 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
698 // Convert and transfer the dead / killed information we have gathered into
699 // VirtRegInfo onto MI's.
700 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
701 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
702 if (VirtRegInfo[i].Kills[j] ==
703 MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
705 .Kills[j]->addRegisterDead(i +
706 TargetRegisterInfo::FirstVirtualRegister,
710 .Kills[j]->addRegisterKilled(i +
711 TargetRegisterInfo::FirstVirtualRegister,
714 // Check to make sure there are no unreachable blocks in the MC CFG for the
715 // function. If so, it is due to a bug in the instruction selector or some
716 // other part of the code generator if this happens.
718 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
719 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
729 /// replaceKillInstruction - Update register kill info by replacing a kill
730 /// instruction with a new one.
731 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
732 MachineInstr *NewMI) {
733 VarInfo &VI = getVarInfo(Reg);
734 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
737 /// removeVirtualRegistersKilled - Remove all killed info for the specified
739 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
740 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
741 MachineOperand &MO = MI->getOperand(i);
742 if (MO.isReg() && MO.isKill()) {
744 unsigned Reg = MO.getReg();
745 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
746 bool removed = getVarInfo(Reg).removeKill(MI);
747 assert(removed && "kill not in register's VarInfo?");
754 /// analyzePHINodes - Gather information about the PHI nodes in here. In
755 /// particular, we want to map the variable information of a virtual register
756 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
758 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
759 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
761 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
762 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
763 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
764 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
765 .push_back(BBI->getOperand(i).getReg());