1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/MRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Config/alloca.h"
41 char LiveVariables::ID = 0;
42 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
44 void LiveVariables::VarInfo::dump() const {
45 cerr << "Register Defined by: ";
50 cerr << " Alive in blocks: ";
51 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
52 if (AliveBlocks[i]) cerr << i << ", ";
53 cerr << "\n Killed by:";
55 cerr << " No instructions.\n";
57 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
58 cerr << "\n #" << i << ": " << *Kills[i];
63 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
64 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
65 "getVarInfo: not a virtual register!");
66 RegIdx -= MRegisterInfo::FirstVirtualRegister;
67 if (RegIdx >= VirtRegInfo.size()) {
68 if (RegIdx >= 2*VirtRegInfo.size())
69 VirtRegInfo.resize(RegIdx*2);
71 VirtRegInfo.resize(2*VirtRegInfo.size());
73 VarInfo &VI = VirtRegInfo[RegIdx];
74 VI.AliveBlocks.resize(MF->getNumBlockIDs());
78 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80 MachineOperand &MO = MI->getOperand(i);
81 if (MO.isReg() && MO.isKill()) {
82 if ((MO.getReg() == Reg) ||
83 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
84 MRegisterInfo::isPhysicalRegister(Reg) &&
85 RegInfo->isSubRegister(MO.getReg(), Reg)))
92 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
93 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
94 MachineOperand &MO = MI->getOperand(i);
95 if (MO.isReg() && MO.isDead()) {
96 if ((MO.getReg() == Reg) ||
97 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
98 MRegisterInfo::isPhysicalRegister(Reg) &&
99 RegInfo->isSubRegister(MO.getReg(), Reg)))
106 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
107 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
108 MachineOperand &MO = MI->getOperand(i);
109 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
115 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
116 MachineBasicBlock *MBB,
117 std::vector<MachineBasicBlock*> &WorkList) {
118 unsigned BBNum = MBB->getNumber();
120 // Check to see if this basic block is one of the killing blocks. If so,
122 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
123 if (VRInfo.Kills[i]->getParent() == MBB) {
124 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
128 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
130 if (VRInfo.AliveBlocks[BBNum])
131 return; // We already know the block is live
133 // Mark the variable known alive in this bb
134 VRInfo.AliveBlocks[BBNum] = true;
136 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
137 E = MBB->pred_rend(); PI != E; ++PI)
138 WorkList.push_back(*PI);
141 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
142 MachineBasicBlock *MBB) {
143 std::vector<MachineBasicBlock*> WorkList;
144 MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList);
145 while (!WorkList.empty()) {
146 MachineBasicBlock *Pred = WorkList.back();
148 MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList);
153 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
155 assert(VRInfo.DefInst && "Register use before def!");
159 // Check to see if this basic block is already a kill block...
160 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
161 // Yes, this register is killed in this basic block already. Increase the
162 // live range by updating the kill instruction.
163 VRInfo.Kills.back() = MI;
168 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
169 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
172 assert(MBB != VRInfo.DefInst->getParent() &&
173 "Should have kill for defblock!");
175 // Add a new kill entry for this basic block.
176 // If this virtual register is already marked as alive in this basic block,
177 // that means it is alive in at least one of the successor block, it's not
179 if (!VRInfo.AliveBlocks[MBB->getNumber()])
180 VRInfo.Kills.push_back(MI);
182 // Update all dominating blocks to mark them known live.
183 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
184 E = MBB->pred_end(); PI != E; ++PI)
185 MarkVirtRegAliveInBlock(VRInfo, *PI);
188 bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
189 bool AddIfNotFound) {
191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
192 MachineOperand &MO = MI->getOperand(i);
193 if (MO.isReg() && MO.isUse()) {
194 unsigned Reg = MO.getReg();
197 if (Reg == IncomingReg) {
201 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
202 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
203 RegInfo->isSuperRegister(IncomingReg, Reg) &&
205 // A super-register kill already exists.
210 // If not found, this means an alias of one of the operand is killed. Add a
211 // new implicit operand if required.
212 if (!Found && AddIfNotFound) {
213 MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
219 bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
220 bool AddIfNotFound) {
222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
223 MachineOperand &MO = MI->getOperand(i);
224 if (MO.isReg() && MO.isDef()) {
225 unsigned Reg = MO.getReg();
228 if (Reg == IncomingReg) {
232 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
233 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
234 RegInfo->isSuperRegister(IncomingReg, Reg) &&
236 // There exists a super-register that's marked dead.
241 // If not found, this means an alias of one of the operand is dead. Add a
242 // new implicit operand.
243 if (!Found && AddIfNotFound) {
244 MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
251 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
252 // Turn previous partial def's into read/mod/write.
253 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
254 MachineInstr *Def = PhysRegPartDef[Reg][i];
255 // First one is just a def. This means the use is reading some undef bits.
257 Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
258 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
260 PhysRegPartDef[Reg].clear();
262 // There was an earlier def of a super-register. Add implicit def to that MI.
265 // Add implicit def to A.
266 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
268 MachineInstr *Def = PhysRegInfo[Reg];
269 if (!Def->findRegisterDefOperand(Reg))
270 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
273 // There is a now a proper use, forget about the last partial use.
274 PhysRegPartUse[Reg] = NULL;
275 PhysRegInfo[Reg] = MI;
276 PhysRegUsed[Reg] = true;
278 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
279 unsigned SubReg = *SubRegs; ++SubRegs) {
280 PhysRegInfo[SubReg] = MI;
281 PhysRegUsed[SubReg] = true;
284 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
285 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
286 // Remember the partial use of this superreg if it was previously defined.
287 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
289 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
290 unsigned SSReg = *SSRegs; ++SSRegs) {
291 if (PhysRegInfo[SSReg] != NULL) {
298 PhysRegInfo[SuperReg] = MI;
299 PhysRegPartUse[SuperReg] = MI;
304 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
305 SmallSet<unsigned, 4> &SubKills) {
306 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
307 unsigned SubReg = *SubRegs; ++SubRegs) {
308 MachineInstr *LastRef = PhysRegInfo[SubReg];
309 if (LastRef != RefMI)
310 SubKills.insert(SubReg);
311 else if (!HandlePhysRegKill(SubReg, RefMI, SubKills))
312 SubKills.insert(SubReg);
315 if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
316 // No sub-registers, just check if reg is killed by RefMI.
317 if (PhysRegInfo[Reg] == RefMI)
319 } else if (SubKills.empty())
320 // None of the sub-registers are killed elsewhere...
325 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
326 SmallSet<unsigned, 4> &SubKills) {
327 if (SubKills.count(Reg) == 0)
328 addRegisterKilled(Reg, MI, true);
330 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
331 unsigned SubReg = *SubRegs; ++SubRegs)
332 addRegisterKills(SubReg, MI, SubKills);
336 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
337 SmallSet<unsigned, 4> SubKills;
338 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
339 addRegisterKilled(Reg, RefMI);
342 // Some sub-registers are killed by another MI.
343 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
344 unsigned SubReg = *SubRegs; ++SubRegs)
345 addRegisterKills(SubReg, RefMI, SubKills);
350 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
351 // Does this kill a previous version of this register?
352 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
353 if (PhysRegUsed[Reg]) {
354 if (!HandlePhysRegKill(Reg, LastRef)) {
355 if (PhysRegPartUse[Reg])
356 addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
358 } else if (PhysRegPartUse[Reg])
359 // Add implicit use / kill to last partial use.
360 addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
362 addRegisterDead(Reg, LastRef);
365 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
366 unsigned SubReg = *SubRegs; ++SubRegs) {
367 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
368 if (PhysRegUsed[SubReg]) {
369 if (!HandlePhysRegKill(SubReg, LastRef)) {
370 if (PhysRegPartUse[SubReg])
371 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
373 } else if (PhysRegPartUse[SubReg])
374 // Add implicit use / kill to last use of a sub-register.
375 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
376 else if (LastRef != MI)
377 // This must be a def of the subreg on the same MI.
378 addRegisterDead(SubReg, LastRef);
383 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
384 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
385 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
386 // The larger register is previously defined. Now a smaller part is
387 // being re-defined. Treat it as read/mod/write.
389 // AX = EAX<imp-use,kill>, EAX<imp-def>
390 MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
391 MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
392 PhysRegInfo[SuperReg] = MI;
393 PhysRegUsed[SuperReg] = false;
394 PhysRegPartUse[SuperReg] = NULL;
396 // Remember this partial def.
397 PhysRegPartDef[SuperReg].push_back(MI);
401 PhysRegInfo[Reg] = MI;
402 PhysRegUsed[Reg] = false;
403 PhysRegPartDef[Reg].clear();
404 PhysRegPartUse[Reg] = NULL;
405 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
406 unsigned SubReg = *SubRegs; ++SubRegs) {
407 PhysRegInfo[SubReg] = MI;
408 PhysRegUsed[SubReg] = false;
409 PhysRegPartDef[SubReg].clear();
410 PhysRegPartUse[SubReg] = NULL;
415 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
417 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
418 RegInfo = MF->getTarget().getRegisterInfo();
419 assert(RegInfo && "Target doesn't have register information?");
421 ReservedRegisters = RegInfo->getReservedRegs(mf);
423 unsigned NumRegs = RegInfo->getNumRegs();
424 PhysRegInfo = new MachineInstr*[NumRegs];
425 PhysRegUsed = new bool[NumRegs];
426 PhysRegPartUse = new MachineInstr*[NumRegs];
427 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
428 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
429 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
430 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
431 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
433 /// Get some space for a respectable number of registers...
434 VirtRegInfo.resize(64);
438 // Calculate live variable information in depth first order on the CFG of the
439 // function. This guarantees that we will see the definition of a virtual
440 // register before its uses due to dominance properties of SSA (except for PHI
441 // nodes, which are treated as a special case).
443 MachineBasicBlock *Entry = MF->begin();
444 SmallPtrSet<MachineBasicBlock*,16> Visited;
445 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
446 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
448 MachineBasicBlock *MBB = *DFI;
450 // Mark live-in registers as live-in.
451 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
452 EE = MBB->livein_end(); II != EE; ++II) {
453 assert(MRegisterInfo::isPhysicalRegister(*II) &&
454 "Cannot have a live-in virtual register!");
455 HandlePhysRegDef(*II, 0);
458 // Loop over all of the instructions, processing them.
459 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
461 MachineInstr *MI = I;
463 // Process all of the operands of the instruction...
464 unsigned NumOperandsToProcess = MI->getNumOperands();
466 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
467 // of the uses. They will be handled in other basic blocks.
468 if (MI->getOpcode() == TargetInstrInfo::PHI)
469 NumOperandsToProcess = 1;
471 // Process all uses...
472 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
473 MachineOperand &MO = MI->getOperand(i);
474 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
475 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
476 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
477 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
478 !ReservedRegisters[MO.getReg()]) {
479 HandlePhysRegUse(MO.getReg(), MI);
484 // Process all defs...
485 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
486 MachineOperand &MO = MI->getOperand(i);
487 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
488 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
489 VarInfo &VRInfo = getVarInfo(MO.getReg());
491 assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
494 VRInfo.Kills.push_back(MI);
495 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
496 !ReservedRegisters[MO.getReg()]) {
497 HandlePhysRegDef(MO.getReg(), MI);
503 // Handle any virtual assignments from PHI nodes which might be at the
504 // bottom of this basic block. We check all of our successor blocks to see
505 // if they have PHI nodes, and if so, we simulate an assignment at the end
506 // of the current block.
507 if (!PHIVarInfo[MBB->getNumber()].empty()) {
508 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
510 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
511 E = VarInfoVec.end(); I != E; ++I) {
512 VarInfo& VRInfo = getVarInfo(*I);
513 assert(VRInfo.DefInst && "Register use before def (or no def)!");
515 // Only mark it alive only in the block we are representing.
516 MarkVirtRegAliveInBlock(VRInfo, MBB);
520 // Finally, if the last instruction in the block is a return, make sure to mark
521 // it as using all of the live-out values in the function.
522 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
523 MachineInstr *Ret = &MBB->back();
524 for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
525 E = MF->liveout_end(); I != E; ++I) {
526 assert(MRegisterInfo::isPhysicalRegister(*I) &&
527 "Cannot have a live-in virtual register!");
528 HandlePhysRegUse(*I, Ret);
529 // Add live-out registers as implicit uses.
530 if (Ret->findRegisterUseOperandIdx(*I) == -1)
531 Ret->addRegOperand(*I, false, true);
535 // Loop over PhysRegInfo, killing any registers that are available at the
536 // end of the basic block. This also resets the PhysRegInfo map.
537 for (unsigned i = 0; i != NumRegs; ++i)
539 HandlePhysRegDef(i, 0);
541 // Clear some states between BB's. These are purely local information.
542 for (unsigned i = 0; i != NumRegs; ++i)
543 PhysRegPartDef[i].clear();
544 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
545 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
546 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
549 // Convert and transfer the dead / killed information we have gathered into
550 // VirtRegInfo onto MI's.
552 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
553 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
554 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
555 addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
556 VirtRegInfo[i].Kills[j]);
558 addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
559 VirtRegInfo[i].Kills[j]);
562 // Check to make sure there are no unreachable blocks in the MC CFG for the
563 // function. If so, it is due to a bug in the instruction selector or some
564 // other part of the code generator if this happens.
566 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
567 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
570 delete[] PhysRegInfo;
571 delete[] PhysRegUsed;
572 delete[] PhysRegPartUse;
573 delete[] PhysRegPartDef;
579 /// instructionChanged - When the address of an instruction changes, this
580 /// method should be called so that live variables can update its internal
581 /// data structures. This removes the records for OldMI, transfering them to
582 /// the records for NewMI.
583 void LiveVariables::instructionChanged(MachineInstr *OldMI,
584 MachineInstr *NewMI) {
585 // If the instruction defines any virtual registers, update the VarInfo,
586 // kill and dead information for the instruction.
587 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
588 MachineOperand &MO = OldMI->getOperand(i);
589 if (MO.isRegister() && MO.getReg() &&
590 MRegisterInfo::isVirtualRegister(MO.getReg())) {
591 unsigned Reg = MO.getReg();
592 VarInfo &VI = getVarInfo(Reg);
596 addVirtualRegisterDead(Reg, NewMI);
598 // Update the defining instruction.
599 if (VI.DefInst == OldMI)
604 addVirtualRegisterKilled(Reg, NewMI);
606 // If this is a kill of the value, update the VI kills list.
607 if (VI.removeKill(OldMI))
608 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
613 /// removeVirtualRegistersKilled - Remove all killed info for the specified
615 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
616 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
617 MachineOperand &MO = MI->getOperand(i);
618 if (MO.isReg() && MO.isKill()) {
620 unsigned Reg = MO.getReg();
621 if (MRegisterInfo::isVirtualRegister(Reg)) {
622 bool removed = getVarInfo(Reg).removeKill(MI);
623 assert(removed && "kill not in register's VarInfo?");
629 /// removeVirtualRegistersDead - Remove all of the dead registers for the
630 /// specified instruction from the live variable information.
631 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
632 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
633 MachineOperand &MO = MI->getOperand(i);
634 if (MO.isReg() && MO.isDead()) {
636 unsigned Reg = MO.getReg();
637 if (MRegisterInfo::isVirtualRegister(Reg)) {
638 bool removed = getVarInfo(Reg).removeKill(MI);
639 assert(removed && "kill not in register's VarInfo?");
645 /// analyzePHINodes - Gather information about the PHI nodes in here. In
646 /// particular, we want to map the variable information of a virtual
647 /// register which is used in a PHI node. We map that to the BB the vreg is
650 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
651 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
653 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
654 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
655 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
656 PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
657 push_back(BBI->getOperand(i).getReg());