1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/MRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Config/alloca.h"
40 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
42 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
43 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
44 "getVarInfo: not a virtual register!");
45 RegIdx -= MRegisterInfo::FirstVirtualRegister;
46 if (RegIdx >= VirtRegInfo.size()) {
47 if (RegIdx >= 2*VirtRegInfo.size())
48 VirtRegInfo.resize(RegIdx*2);
50 VirtRegInfo.resize(2*VirtRegInfo.size());
52 return VirtRegInfo[RegIdx];
55 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
56 std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
57 RegistersKilled.find(MI);
58 if (I == RegistersKilled.end()) return false;
60 // Do a binary search, as these lists can grow pretty big, particularly for
61 // call instructions on targets with lots of call-clobbered registers.
62 return std::binary_search(I->second.begin(), I->second.end(), Reg);
65 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
66 std::map<MachineInstr*, std::vector<unsigned> >::const_iterator I =
67 RegistersDead.find(MI);
68 if (I == RegistersDead.end()) return false;
70 // Do a binary search, as these lists can grow pretty big, particularly for
71 // call instructions on targets with lots of call-clobbered registers.
72 return std::binary_search(I->second.begin(), I->second.end(), Reg);
76 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
77 MachineBasicBlock *MBB) {
78 unsigned BBNum = MBB->getNumber();
80 // Check to see if this basic block is one of the killing blocks. If so,
82 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
83 if (VRInfo.Kills[i]->getParent() == MBB) {
84 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
88 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
90 if (VRInfo.AliveBlocks.size() <= BBNum)
91 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
93 if (VRInfo.AliveBlocks[BBNum])
94 return; // We already know the block is live
96 // Mark the variable known alive in this bb
97 VRInfo.AliveBlocks[BBNum] = true;
99 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
100 E = MBB->pred_end(); PI != E; ++PI)
101 MarkVirtRegAliveInBlock(VRInfo, *PI);
104 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
106 assert(VRInfo.DefInst && "Register use before def!");
108 // Check to see if this basic block is already a kill block...
109 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
110 // Yes, this register is killed in this basic block already. Increase the
111 // live range by updating the kill instruction.
112 VRInfo.Kills.back() = MI;
117 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
118 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
121 assert(MBB != VRInfo.DefInst->getParent() &&
122 "Should have kill for defblock!");
124 // Add a new kill entry for this basic block.
125 VRInfo.Kills.push_back(MI);
127 // Update all dominating blocks to mark them known live.
128 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
129 E = MBB->pred_end(); PI != E; ++PI)
130 MarkVirtRegAliveInBlock(VRInfo, *PI);
133 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
134 PhysRegInfo[Reg] = MI;
135 PhysRegUsed[Reg] = true;
137 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
138 unsigned Alias = *AliasSet; ++AliasSet) {
139 PhysRegInfo[Alias] = MI;
140 PhysRegUsed[Alias] = true;
144 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
145 // Does this kill a previous version of this register?
146 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
147 if (PhysRegUsed[Reg])
148 RegistersKilled[LastUse].push_back(Reg);
150 RegistersDead[LastUse].push_back(Reg);
152 PhysRegInfo[Reg] = MI;
153 PhysRegUsed[Reg] = false;
155 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
156 unsigned Alias = *AliasSet; ++AliasSet) {
157 if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
158 if (PhysRegUsed[Alias])
159 RegistersKilled[LastUse].push_back(Alias);
161 RegistersDead[LastUse].push_back(Alias);
163 PhysRegInfo[Alias] = MI;
164 PhysRegUsed[Alias] = false;
168 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
169 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
170 RegInfo = MF.getTarget().getRegisterInfo();
171 assert(RegInfo && "Target doesn't have register information?");
173 AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF);
175 // PhysRegInfo - Keep track of which instruction was the last use of a
176 // physical register. This is a purely local property, because all physical
177 // register references as presumed dead across basic blocks.
179 PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
180 RegInfo->getNumRegs());
181 PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
182 std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
184 /// Get some space for a respectable number of registers...
185 VirtRegInfo.resize(64);
187 // Mark live-in registers as live-in.
188 for (MachineFunction::livein_iterator I = MF.livein_begin(),
189 E = MF.livein_end(); I != E; ++I) {
190 assert(MRegisterInfo::isPhysicalRegister(I->first) &&
191 "Cannot have a live-in virtual register!");
192 HandlePhysRegDef(I->first, 0);
195 // Calculate live variable information in depth first order on the CFG of the
196 // function. This guarantees that we will see the definition of a virtual
197 // register before its uses due to dominance properties of SSA (except for PHI
198 // nodes, which are treated as a special case).
200 MachineBasicBlock *Entry = MF.begin();
201 std::set<MachineBasicBlock*> Visited;
202 for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
203 E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
204 MachineBasicBlock *MBB = *DFI;
205 unsigned BBNum = MBB->getNumber();
207 // Loop over all of the instructions, processing them.
208 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
210 MachineInstr *MI = I;
211 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
213 // Process all of the operands of the instruction...
214 unsigned NumOperandsToProcess = MI->getNumOperands();
216 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
217 // of the uses. They will be handled in other basic blocks.
218 if (MI->getOpcode() == TargetInstrInfo::PHI)
219 NumOperandsToProcess = 1;
221 // Loop over implicit uses, using them.
222 for (const unsigned *ImplicitUses = MID.ImplicitUses;
223 *ImplicitUses; ++ImplicitUses)
224 HandlePhysRegUse(*ImplicitUses, MI);
226 // Process all explicit uses...
227 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
229 if (MO.isUse() && MO.isRegister() && MO.getReg()) {
230 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
231 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
232 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
233 AllocatablePhysicalRegisters[MO.getReg()]) {
234 HandlePhysRegUse(MO.getReg(), MI);
239 // Loop over implicit defs, defining them.
240 for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
241 *ImplicitDefs; ++ImplicitDefs)
242 HandlePhysRegDef(*ImplicitDefs, MI);
244 // Process all explicit defs...
245 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
246 MachineOperand &MO = MI->getOperand(i);
247 if (MO.isDef() && MO.isRegister() && MO.getReg()) {
248 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
249 VarInfo &VRInfo = getVarInfo(MO.getReg());
251 assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
254 VRInfo.Kills.push_back(MI);
255 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
256 AllocatablePhysicalRegisters[MO.getReg()]) {
257 HandlePhysRegDef(MO.getReg(), MI);
263 // Handle any virtual assignments from PHI nodes which might be at the
264 // bottom of this basic block. We check all of our successor blocks to see
265 // if they have PHI nodes, and if so, we simulate an assignment at the end
266 // of the current block.
267 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
268 E = MBB->succ_end(); SI != E; ++SI) {
269 MachineBasicBlock *Succ = *SI;
271 // PHI nodes are guaranteed to be at the top of the block...
272 for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
273 MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
274 for (unsigned i = 1; ; i += 2) {
275 assert(MI->getNumOperands() > i+1 &&
276 "Didn't find an entry for our predecessor??");
277 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
278 MachineOperand &MO = MI->getOperand(i);
279 if (!MO.getVRegValueOrNull()) {
280 VarInfo &VRInfo = getVarInfo(MO.getReg());
281 assert(VRInfo.DefInst && "Register use before def (or no def)!");
283 // Only mark it alive only in the block we are representing.
284 MarkVirtRegAliveInBlock(VRInfo, MBB);
285 break; // Found the PHI entry for this block.
292 // Finally, if the last block in the function is a return, make sure to mark
293 // it as using all of the live-out values in the function.
294 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
295 MachineInstr *Ret = &MBB->back();
296 for (MachineFunction::liveout_iterator I = MF.liveout_begin(),
297 E = MF.liveout_end(); I != E; ++I) {
298 assert(MRegisterInfo::isPhysicalRegister(*I) &&
299 "Cannot have a live-in virtual register!");
300 HandlePhysRegUse(*I, Ret);
304 // Loop over PhysRegInfo, killing any registers that are available at the
305 // end of the basic block. This also resets the PhysRegInfo map.
306 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
308 HandlePhysRegDef(i, 0);
311 // Convert the information we have gathered into VirtRegInfo and transform it
312 // into a form usable by RegistersKilled.
314 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
315 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
316 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
317 RegistersDead[VirtRegInfo[i].Kills[j]].push_back(
318 i + MRegisterInfo::FirstVirtualRegister);
321 RegistersKilled[VirtRegInfo[i].Kills[j]].push_back(
322 i + MRegisterInfo::FirstVirtualRegister);
325 // Walk through the RegistersKilled/Dead sets, and sort the registers killed
326 // or dead. This allows us to use efficient binary search for membership
328 for (std::map<MachineInstr*, std::vector<unsigned> >::iterator
329 I = RegistersKilled.begin(), E = RegistersKilled.end(); I != E; ++I)
330 std::sort(I->second.begin(), I->second.end());
331 for (std::map<MachineInstr*, std::vector<unsigned> >::iterator
332 I = RegistersDead.begin(), E = RegistersDead.end(); I != E; ++I)
333 std::sort(I->second.begin(), I->second.end());
335 // Check to make sure there are no unreachable blocks in the MC CFG for the
336 // function. If so, it is due to a bug in the instruction selector or some
337 // other part of the code generator if this happens.
339 for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
340 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
346 /// instructionChanged - When the address of an instruction changes, this
347 /// method should be called so that live variables can update its internal
348 /// data structures. This removes the records for OldMI, transfering them to
349 /// the records for NewMI.
350 void LiveVariables::instructionChanged(MachineInstr *OldMI,
351 MachineInstr *NewMI) {
352 // If the instruction defines any virtual registers, update the VarInfo for
354 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
355 MachineOperand &MO = OldMI->getOperand(i);
356 if (MO.isRegister() && MO.getReg() &&
357 MRegisterInfo::isVirtualRegister(MO.getReg())) {
358 unsigned Reg = MO.getReg();
359 VarInfo &VI = getVarInfo(Reg);
361 // Update the defining instruction.
362 if (VI.DefInst == OldMI)
366 // If this is a kill of the value, update the VI kills list.
367 if (VI.removeKill(OldMI))
368 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
373 // Move the killed information over...
374 killed_iterator I, E;
375 tie(I, E) = killed_range(OldMI);
377 std::vector<unsigned> &V = RegistersKilled[NewMI];
378 bool WasEmpty = V.empty();
379 V.insert(V.end(), I, E);
381 std::sort(V.begin(), V.end()); // Keep the reg list sorted.
382 RegistersKilled.erase(OldMI);
385 // Move the dead information over...
386 tie(I, E) = dead_range(OldMI);
388 std::vector<unsigned> &V = RegistersDead[NewMI];
389 bool WasEmpty = V.empty();
390 V.insert(V.end(), I, E);
392 std::sort(V.begin(), V.end()); // Keep the reg list sorted.
393 RegistersDead.erase(OldMI);