1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/STLExtras.h"
43 char LiveVariables::ID = 0;
44 INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
45 "Live Variable Analysis", false, false)
46 INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
47 INITIALIZE_PASS_END(LiveVariables, "livevars",
48 "Live Variable Analysis", false, false)
51 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
52 AU.addRequiredID(UnreachableMachineBlockElimID);
54 MachineFunctionPass::getAnalysisUsage(AU);
58 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
59 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
60 if (Kills[i]->getParent() == MBB)
65 void LiveVariables::VarInfo::dump() const {
66 dbgs() << " Alive in blocks: ";
67 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
68 E = AliveBlocks.end(); I != E; ++I)
70 dbgs() << "\n Killed by:";
72 dbgs() << " No instructions.\n";
74 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
75 dbgs() << "\n #" << i << ": " << *Kills[i];
80 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
81 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
82 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
83 "getVarInfo: not a virtual register!");
84 VirtRegInfo.grow(RegIdx);
85 return VirtRegInfo[RegIdx];
88 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
89 MachineBasicBlock *DefBlock,
90 MachineBasicBlock *MBB,
91 std::vector<MachineBasicBlock*> &WorkList) {
92 unsigned BBNum = MBB->getNumber();
94 // Check to see if this basic block is one of the killing blocks. If so,
96 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
97 if (VRInfo.Kills[i]->getParent() == MBB) {
98 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
102 if (MBB == DefBlock) return; // Terminate recursion
104 if (VRInfo.AliveBlocks.test(BBNum))
105 return; // We already know the block is live
107 // Mark the variable known alive in this bb
108 VRInfo.AliveBlocks.set(BBNum);
110 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
113 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
114 MachineBasicBlock *DefBlock,
115 MachineBasicBlock *MBB) {
116 std::vector<MachineBasicBlock*> WorkList;
117 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
119 while (!WorkList.empty()) {
120 MachineBasicBlock *Pred = WorkList.back();
122 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
126 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
128 assert(MRI->getVRegDef(reg) && "Register use before def!");
130 unsigned BBNum = MBB->getNumber();
132 VarInfo& VRInfo = getVarInfo(reg);
134 // Check to see if this basic block is already a kill block.
135 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
136 // Yes, this register is killed in this basic block already. Increase the
137 // live range by updating the kill instruction.
138 VRInfo.Kills.back() = MI;
143 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
144 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
147 // This situation can occur:
152 // | t2 = phi ... t1 ...
156 // | ... = ... t1 ...
160 // where there is a use in a PHI node that's a predecessor to the defining
161 // block. We don't want to mark all predecessors as having the value "alive"
163 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
165 // Add a new kill entry for this basic block. If this virtual register is
166 // already marked as alive in this basic block, that means it is alive in at
167 // least one of the successor blocks, it's not a kill.
168 if (!VRInfo.AliveBlocks.test(BBNum))
169 VRInfo.Kills.push_back(MI);
171 // Update all dominating blocks to mark them as "known live".
172 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
173 E = MBB->pred_end(); PI != E; ++PI)
174 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
177 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
178 VarInfo &VRInfo = getVarInfo(Reg);
180 if (VRInfo.AliveBlocks.empty())
181 // If vr is not alive in any block, then defaults to dead.
182 VRInfo.Kills.push_back(MI);
185 /// FindLastPartialDef - Return the last partial def of the specified register.
186 /// Also returns the sub-registers that're defined by the instruction.
187 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
188 SmallSet<unsigned,4> &PartDefRegs) {
189 unsigned LastDefReg = 0;
190 unsigned LastDefDist = 0;
191 MachineInstr *LastDef = NULL;
192 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
193 unsigned SubReg = *SubRegs; ++SubRegs) {
194 MachineInstr *Def = PhysRegDef[SubReg];
197 unsigned Dist = DistanceMap[Def];
198 if (Dist > LastDefDist) {
208 PartDefRegs.insert(LastDefReg);
209 for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
210 MachineOperand &MO = LastDef->getOperand(i);
211 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
213 unsigned DefReg = MO.getReg();
214 if (TRI->isSubRegister(Reg, DefReg)) {
215 PartDefRegs.insert(DefReg);
216 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
217 unsigned SubReg = *SubRegs; ++SubRegs)
218 PartDefRegs.insert(SubReg);
224 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
225 /// implicit defs to a machine instruction if there was an earlier def of its
227 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
228 MachineInstr *LastDef = PhysRegDef[Reg];
229 // If there was a previous use or a "full" def all is well.
230 if (!LastDef && !PhysRegUse[Reg]) {
231 // Otherwise, the last sub-register def implicitly defines this register.
234 // AL = ... <imp-def EAX>, <imp-kill AH>
238 // All of the sub-registers must have been defined before the use of Reg!
239 SmallSet<unsigned, 4> PartDefRegs;
240 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
241 // If LastPartialDef is NULL, it must be using a livein register.
242 if (LastPartialDef) {
243 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
245 PhysRegDef[Reg] = LastPartialDef;
246 SmallSet<unsigned, 8> Processed;
247 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
248 unsigned SubReg = *SubRegs; ++SubRegs) {
249 if (Processed.count(SubReg))
251 if (PartDefRegs.count(SubReg))
253 // This part of Reg was defined before the last partial def. It's killed
255 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
258 PhysRegDef[SubReg] = LastPartialDef;
259 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
260 Processed.insert(*SS);
263 } else if (LastDef && !PhysRegUse[Reg] &&
264 !LastDef->findRegisterDefOperand(Reg))
265 // Last def defines the super register, add an implicit def of reg.
266 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
269 // Remember this use.
270 PhysRegUse[Reg] = MI;
271 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
272 unsigned SubReg = *SubRegs; ++SubRegs)
273 PhysRegUse[SubReg] = MI;
276 /// FindLastRefOrPartRef - Return the last reference or partial reference of
277 /// the specified register.
278 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
279 MachineInstr *LastDef = PhysRegDef[Reg];
280 MachineInstr *LastUse = PhysRegUse[Reg];
281 if (!LastDef && !LastUse)
284 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
285 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
286 unsigned LastPartDefDist = 0;
287 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
288 unsigned SubReg = *SubRegs; ++SubRegs) {
289 MachineInstr *Def = PhysRegDef[SubReg];
290 if (Def && Def != LastDef) {
291 // There was a def of this sub-register in between. This is a partial
292 // def, keep track of the last one.
293 unsigned Dist = DistanceMap[Def];
294 if (Dist > LastPartDefDist)
295 LastPartDefDist = Dist;
296 } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
297 unsigned Dist = DistanceMap[Use];
298 if (Dist > LastRefOrPartRefDist) {
299 LastRefOrPartRefDist = Dist;
300 LastRefOrPartRef = Use;
305 return LastRefOrPartRef;
308 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
309 MachineInstr *LastDef = PhysRegDef[Reg];
310 MachineInstr *LastUse = PhysRegUse[Reg];
311 if (!LastDef && !LastUse)
314 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
315 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
316 // The whole register is used.
321 // = AL, AX<imp-use, kill>
324 // Or whole register is defined, but not used at all.
329 // Or whole register is defined, but only partly used.
330 // AX<dead> = AL<imp-def>
333 MachineInstr *LastPartDef = 0;
334 unsigned LastPartDefDist = 0;
335 SmallSet<unsigned, 8> PartUses;
336 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
337 unsigned SubReg = *SubRegs; ++SubRegs) {
338 MachineInstr *Def = PhysRegDef[SubReg];
339 if (Def && Def != LastDef) {
340 // There was a def of this sub-register in between. This is a partial
341 // def, keep track of the last one.
342 unsigned Dist = DistanceMap[Def];
343 if (Dist > LastPartDefDist) {
344 LastPartDefDist = Dist;
349 if (MachineInstr *Use = PhysRegUse[SubReg]) {
350 PartUses.insert(SubReg);
351 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
352 PartUses.insert(*SS);
353 unsigned Dist = DistanceMap[Use];
354 if (Dist > LastRefOrPartRefDist) {
355 LastRefOrPartRefDist = Dist;
356 LastRefOrPartRef = Use;
361 if (!PhysRegUse[Reg]) {
362 // Partial uses. Mark register def dead and add implicit def of
363 // sub-registers which are used.
364 // EAX<dead> = op AL<imp-def>
365 // That is, EAX def is dead but AL def extends pass it.
366 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
367 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
368 unsigned SubReg = *SubRegs; ++SubRegs) {
369 if (!PartUses.count(SubReg))
372 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
373 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
376 assert(!MO->isDead());
380 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
381 true/*IsDef*/, true/*IsImp*/));
382 MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
384 LastSubRef->addRegisterKilled(SubReg, TRI, true);
386 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
387 PhysRegUse[SubReg] = LastRefOrPartRef;
388 for (const unsigned *SSRegs = TRI->getSubRegisters(SubReg);
389 unsigned SSReg = *SSRegs; ++SSRegs)
390 PhysRegUse[SSReg] = LastRefOrPartRef;
392 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
395 } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
397 // The last partial def kills the register.
398 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
399 true/*IsImp*/, true/*IsKill*/));
402 LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
403 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
404 // If the last reference is the last def, then it's not used at all.
405 // That is, unless we are currently processing the last reference itself.
406 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
408 // If we are adding a subreg def and the superreg def is marked early
409 // clobber, add an early clobber marker to the subreg def.
410 MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
412 MO->setIsEarlyClobber();
416 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
420 void LiveVariables::HandleRegMask(const MachineOperand &MO) {
421 // Call HandlePhysRegKill() for all live registers clobbered by Mask.
422 // Clobbered registers are always dead, sp there is no need to use
423 // HandlePhysRegDef().
424 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
426 if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
428 // Skip mask-preserved regs.
429 if (!MO.clobbersPhysReg(Reg))
431 // Kill the largest clobbered super-register.
432 // This avoids needless implicit operands.
433 unsigned Super = Reg;
434 for (const unsigned *SR = TRI->getSuperRegisters(Reg); *SR; ++SR)
435 if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
437 HandlePhysRegKill(Super, 0);
441 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
442 SmallVector<unsigned, 4> &Defs) {
443 // What parts of the register are previously defined?
444 SmallSet<unsigned, 32> Live;
445 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
447 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
450 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
451 unsigned SubReg = *SubRegs; ++SubRegs) {
452 // If a register isn't itself defined, but all parts that make up of it
453 // are defined, then consider it also defined.
458 if (Live.count(SubReg))
460 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
462 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
468 // Start from the largest piece, find the last time any part of the register
470 HandlePhysRegKill(Reg, MI);
471 // Only some of the sub-registers are used.
472 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
473 unsigned SubReg = *SubRegs; ++SubRegs) {
474 if (!Live.count(SubReg))
475 // Skip if this sub-register isn't defined.
477 HandlePhysRegKill(SubReg, MI);
481 Defs.push_back(Reg); // Remember this def.
484 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
485 SmallVector<unsigned, 4> &Defs) {
486 while (!Defs.empty()) {
487 unsigned Reg = Defs.back();
489 PhysRegDef[Reg] = MI;
490 PhysRegUse[Reg] = NULL;
491 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
492 unsigned SubReg = *SubRegs; ++SubRegs) {
493 PhysRegDef[SubReg] = MI;
494 PhysRegUse[SubReg] = NULL;
499 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
501 MRI = &mf.getRegInfo();
502 TRI = MF->getTarget().getRegisterInfo();
504 ReservedRegisters = TRI->getReservedRegs(mf);
506 unsigned NumRegs = TRI->getNumRegs();
507 PhysRegDef = new MachineInstr*[NumRegs];
508 PhysRegUse = new MachineInstr*[NumRegs];
509 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
510 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
511 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
516 // Calculate live variable information in depth first order on the CFG of the
517 // function. This guarantees that we will see the definition of a virtual
518 // register before its uses due to dominance properties of SSA (except for PHI
519 // nodes, which are treated as a special case).
520 MachineBasicBlock *Entry = MF->begin();
521 SmallPtrSet<MachineBasicBlock*,16> Visited;
523 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
524 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
526 MachineBasicBlock *MBB = *DFI;
528 // Mark live-in registers as live-in.
529 SmallVector<unsigned, 4> Defs;
530 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
531 EE = MBB->livein_end(); II != EE; ++II) {
532 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
533 "Cannot have a live-in virtual register!");
534 HandlePhysRegDef(*II, 0, Defs);
537 // Loop over all of the instructions, processing them.
540 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
542 MachineInstr *MI = I;
543 if (MI->isDebugValue())
545 DistanceMap.insert(std::make_pair(MI, Dist++));
547 // Process all of the operands of the instruction...
548 unsigned NumOperandsToProcess = MI->getNumOperands();
550 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
551 // of the uses. They will be handled in other basic blocks.
553 NumOperandsToProcess = 1;
555 // Clear kill and dead markers. LV will recompute them.
556 SmallVector<unsigned, 4> UseRegs;
557 SmallVector<unsigned, 4> DefRegs;
558 SmallVector<unsigned, 1> RegMasks;
559 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
560 MachineOperand &MO = MI->getOperand(i);
561 if (MO.isRegMask()) {
562 RegMasks.push_back(i);
565 if (!MO.isReg() || MO.getReg() == 0)
567 unsigned MOReg = MO.getReg();
570 UseRegs.push_back(MOReg);
571 } else /*MO.isDef()*/ {
573 DefRegs.push_back(MOReg);
578 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
579 unsigned MOReg = UseRegs[i];
580 if (TargetRegisterInfo::isVirtualRegister(MOReg))
581 HandleVirtRegUse(MOReg, MBB, MI);
582 else if (!ReservedRegisters[MOReg])
583 HandlePhysRegUse(MOReg, MI);
586 // Process all masked registers. (Call clobbers).
587 for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
588 HandleRegMask(MI->getOperand(RegMasks[i]));
591 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
592 unsigned MOReg = DefRegs[i];
593 if (TargetRegisterInfo::isVirtualRegister(MOReg))
594 HandleVirtRegDef(MOReg, MI);
595 else if (!ReservedRegisters[MOReg])
596 HandlePhysRegDef(MOReg, MI, Defs);
598 UpdatePhysRegDefs(MI, Defs);
601 // Handle any virtual assignments from PHI nodes which might be at the
602 // bottom of this basic block. We check all of our successor blocks to see
603 // if they have PHI nodes, and if so, we simulate an assignment at the end
604 // of the current block.
605 if (!PHIVarInfo[MBB->getNumber()].empty()) {
606 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
608 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
609 E = VarInfoVec.end(); I != E; ++I)
610 // Mark it alive only in the block we are representing.
611 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
615 // Finally, if the last instruction in the block is a return, make sure to
616 // mark it as using all of the live-out values in the function.
617 // Things marked both call and return are tail calls; do not do this for
618 // them. The tail callee need not take the same registers as input
619 // that it produces as output, and there are dependencies for its input
620 // registers elsewhere.
621 if (!MBB->empty() && MBB->back().isReturn()
622 && !MBB->back().isCall()) {
623 MachineInstr *Ret = &MBB->back();
625 for (MachineRegisterInfo::liveout_iterator
626 I = MF->getRegInfo().liveout_begin(),
627 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
628 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
629 "Cannot have a live-out virtual register!");
630 HandlePhysRegUse(*I, Ret);
632 // Add live-out registers as implicit uses.
633 if (!Ret->readsRegister(*I))
634 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
638 // MachineCSE may CSE instructions which write to non-allocatable physical
639 // registers across MBBs. Remember if any reserved register is liveout.
640 SmallSet<unsigned, 4> LiveOuts;
641 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
642 SE = MBB->succ_end(); SI != SE; ++SI) {
643 MachineBasicBlock *SuccMBB = *SI;
644 if (SuccMBB->isLandingPad())
646 for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
647 LE = SuccMBB->livein_end(); LI != LE; ++LI) {
649 if (!TRI->isInAllocatableClass(LReg))
650 // Ignore other live-ins, e.g. those that are live into landing pads.
651 LiveOuts.insert(LReg);
655 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
656 // available at the end of the basic block.
657 for (unsigned i = 0; i != NumRegs; ++i)
658 if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
659 HandlePhysRegDef(i, 0, Defs);
661 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
662 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
665 // Convert and transfer the dead / killed information we have gathered into
666 // VirtRegInfo onto MI's.
667 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
668 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
669 for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
670 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
671 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
673 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
676 // Check to make sure there are no unreachable blocks in the MC CFG for the
677 // function. If so, it is due to a bug in the instruction selector or some
678 // other part of the code generator if this happens.
680 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
681 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
691 /// replaceKillInstruction - Update register kill info by replacing a kill
692 /// instruction with a new one.
693 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
694 MachineInstr *NewMI) {
695 VarInfo &VI = getVarInfo(Reg);
696 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
699 /// removeVirtualRegistersKilled - Remove all killed info for the specified
701 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
702 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
703 MachineOperand &MO = MI->getOperand(i);
704 if (MO.isReg() && MO.isKill()) {
706 unsigned Reg = MO.getReg();
707 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
708 bool removed = getVarInfo(Reg).removeKill(MI);
709 assert(removed && "kill not in register's VarInfo?");
716 /// analyzePHINodes - Gather information about the PHI nodes in here. In
717 /// particular, we want to map the variable information of a virtual register
718 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
720 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
721 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
723 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
724 BBI != BBE && BBI->isPHI(); ++BBI)
725 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
726 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
727 .push_back(BBI->getOperand(i).getReg());
730 bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
732 MachineRegisterInfo &MRI) {
733 unsigned Num = MBB.getNumber();
735 // Reg is live-through.
736 if (AliveBlocks.test(Num))
739 // Registers defined in MBB cannot be live in.
740 const MachineInstr *Def = MRI.getVRegDef(Reg);
741 if (Def && Def->getParent() == &MBB)
744 // Reg was not defined in MBB, was it killed here?
745 return findKill(&MBB);
748 bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
749 LiveVariables::VarInfo &VI = getVarInfo(Reg);
751 // Loop over all of the successors of the basic block, checking to see if
752 // the value is either live in the block, or if it is killed in the block.
753 SmallVector<MachineBasicBlock*, 8> OpSuccBlocks;
754 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
755 E = MBB.succ_end(); SI != E; ++SI) {
756 MachineBasicBlock *SuccMBB = *SI;
758 // Is it alive in this successor?
759 unsigned SuccIdx = SuccMBB->getNumber();
760 if (VI.AliveBlocks.test(SuccIdx))
762 OpSuccBlocks.push_back(SuccMBB);
765 // Check to see if this value is live because there is a use in a successor
767 switch (OpSuccBlocks.size()) {
769 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
770 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
771 if (VI.Kills[i]->getParent() == SuccMBB)
776 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
777 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
778 if (VI.Kills[i]->getParent() == SuccMBB1 ||
779 VI.Kills[i]->getParent() == SuccMBB2)
784 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
785 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
786 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
787 VI.Kills[i]->getParent()))
793 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
794 /// variables that are live out of DomBB will be marked as passing live through
796 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
797 MachineBasicBlock *DomBB,
798 MachineBasicBlock *SuccBB) {
799 const unsigned NumNew = BB->getNumber();
801 // All registers used by PHI nodes in SuccBB must be live through BB.
802 for (MachineBasicBlock::iterator BBI = SuccBB->begin(),
803 BBE = SuccBB->end(); BBI != BBE && BBI->isPHI(); ++BBI)
804 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
805 if (BBI->getOperand(i+1).getMBB() == BB)
806 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
808 // Update info for all live variables
809 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
810 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
811 VarInfo &VI = getVarInfo(Reg);
812 if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
813 VI.AliveBlocks.set(NumNew);