1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Config/alloca.h"
44 char LiveVariables::ID = 0;
45 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
48 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
49 AU.addRequiredID(UnreachableMachineBlockElimID);
53 void LiveVariables::VarInfo::dump() const {
54 cerr << " Alive in blocks: ";
55 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
56 E = AliveBlocks.end(); I != E; ++I)
58 cerr << "\n Killed by:";
60 cerr << " No instructions.\n";
62 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
63 cerr << "\n #" << i << ": " << *Kills[i];
68 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
69 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
70 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
71 "getVarInfo: not a virtual register!");
72 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
73 if (RegIdx >= VirtRegInfo.size()) {
74 if (RegIdx >= 2*VirtRegInfo.size())
75 VirtRegInfo.resize(RegIdx*2);
77 VirtRegInfo.resize(2*VirtRegInfo.size());
79 return VirtRegInfo[RegIdx];
82 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
83 MachineBasicBlock *DefBlock,
84 MachineBasicBlock *MBB,
85 std::vector<MachineBasicBlock*> &WorkList) {
86 unsigned BBNum = MBB->getNumber();
88 // Check to see if this basic block is one of the killing blocks. If so,
90 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
91 if (VRInfo.Kills[i]->getParent() == MBB) {
92 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
96 if (MBB == DefBlock) return; // Terminate recursion
98 if (VRInfo.AliveBlocks.test(BBNum))
99 return; // We already know the block is live
101 // Mark the variable known alive in this bb
102 VRInfo.AliveBlocks.set(BBNum);
104 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
105 E = MBB->pred_rend(); PI != E; ++PI)
106 WorkList.push_back(*PI);
109 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
110 MachineBasicBlock *DefBlock,
111 MachineBasicBlock *MBB) {
112 std::vector<MachineBasicBlock*> WorkList;
113 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
115 while (!WorkList.empty()) {
116 MachineBasicBlock *Pred = WorkList.back();
118 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
122 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
124 assert(MRI->getVRegDef(reg) && "Register use before def!");
126 unsigned BBNum = MBB->getNumber();
128 VarInfo& VRInfo = getVarInfo(reg);
131 // Check to see if this basic block is already a kill block.
132 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
133 // Yes, this register is killed in this basic block already. Increase the
134 // live range by updating the kill instruction.
135 VRInfo.Kills.back() = MI;
140 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
141 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
144 // This situation can occur:
149 // | t2 = phi ... t1 ...
153 // | ... = ... t1 ...
157 // where there is a use in a PHI node that's a predecessor to the defining
158 // block. We don't want to mark all predecessors as having the value "alive"
160 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
162 // Add a new kill entry for this basic block. If this virtual register is
163 // already marked as alive in this basic block, that means it is alive in at
164 // least one of the successor blocks, it's not a kill.
165 if (!VRInfo.AliveBlocks.test(BBNum))
166 VRInfo.Kills.push_back(MI);
168 // Update all dominating blocks to mark them as "known live".
169 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
170 E = MBB->pred_end(); PI != E; ++PI)
171 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
174 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
175 VarInfo &VRInfo = getVarInfo(Reg);
177 if (VRInfo.AliveBlocks.empty())
178 // If vr is not alive in any block, then defaults to dead.
179 VRInfo.Kills.push_back(MI);
182 /// FindLastPartialDef - Return the last partial def of the specified register.
183 /// Also returns the sub-register that's defined.
184 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
185 unsigned &PartDefReg) {
186 unsigned LastDefReg = 0;
187 unsigned LastDefDist = 0;
188 MachineInstr *LastDef = NULL;
189 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
190 unsigned SubReg = *SubRegs; ++SubRegs) {
191 MachineInstr *Def = PhysRegDef[SubReg];
194 unsigned Dist = DistanceMap[Def];
195 if (Dist > LastDefDist) {
201 PartDefReg = LastDefReg;
205 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
206 /// implicit defs to a machine instruction if there was an earlier def of its
208 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
209 // If there was a previous use or a "full" def all is well.
210 if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) {
211 // Otherwise, the last sub-register def implicitly defines this register.
214 // AL = ... <imp-def EAX>, <imp-kill AH>
218 // All of the sub-registers must have been defined before the use of Reg!
219 unsigned PartDefReg = 0;
220 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg);
221 // If LastPartialDef is NULL, it must be using a livein register.
222 if (LastPartialDef) {
223 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
225 PhysRegDef[Reg] = LastPartialDef;
226 SmallSet<unsigned, 8> Processed;
227 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
228 unsigned SubReg = *SubRegs; ++SubRegs) {
229 if (Processed.count(SubReg))
231 if (SubReg == PartDefReg || TRI->isSubRegister(PartDefReg, SubReg))
233 // This part of Reg was defined before the last partial def. It's killed
235 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
238 PhysRegDef[SubReg] = LastPartialDef;
239 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
240 Processed.insert(*SS);
245 // Remember this use.
246 PhysRegUse[Reg] = MI;
247 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
248 unsigned SubReg = *SubRegs; ++SubRegs)
249 PhysRegUse[SubReg] = MI;
252 /// hasRegisterUseBelow - Return true if the specified register is used after
253 /// the current instruction and before it's next definition.
254 bool LiveVariables::hasRegisterUseBelow(unsigned Reg,
255 MachineBasicBlock::iterator I,
256 MachineBasicBlock *MBB) {
260 // First find out if there are any uses / defs below.
261 bool hasDistInfo = true;
262 unsigned CurDist = DistanceMap[I];
263 SmallVector<MachineInstr*, 4> Uses;
264 SmallVector<MachineInstr*, 4> Defs;
265 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
266 RE = MRI->reg_end(); RI != RE; ++RI) {
267 MachineOperand &UDO = RI.getOperand();
268 MachineInstr *UDMI = &*RI;
269 if (UDMI->getParent() != MBB)
271 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
272 bool isBelow = false;
273 if (DI == DistanceMap.end()) {
274 // Must be below if it hasn't been assigned a distance yet.
277 } else if (DI->second > CurDist)
281 Uses.push_back(UDMI);
283 Defs.push_back(UDMI);
290 else if (!Uses.empty() && Defs.empty())
291 // There are uses below but no defs below.
293 // There are both uses and defs below. We need to know which comes first.
295 // Complete DistanceMap for this MBB. This information is computed only
299 for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I, ++CurDist)
300 DistanceMap.insert(std::make_pair(I, CurDist));
303 unsigned EarliestUse = DistanceMap[Uses[0]];
304 for (unsigned i = 1, e = Uses.size(); i != e; ++i) {
305 unsigned Dist = DistanceMap[Uses[i]];
306 if (Dist < EarliestUse)
309 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
310 unsigned Dist = DistanceMap[Defs[i]];
311 if (Dist < EarliestUse)
312 // The register is defined before its first use below.
318 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
319 if (!PhysRegUse[Reg] && !PhysRegDef[Reg])
322 MachineInstr *LastRefOrPartRef = PhysRegUse[Reg]
323 ? PhysRegUse[Reg] : PhysRegDef[Reg];
324 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
325 // The whole register is used.
330 // = AL, AX<imp-use, kill>
333 // Or whole register is defined, but not used at all.
338 // Or whole register is defined, but only partly used.
339 // AX<dead> = AL<imp-def>
342 SmallSet<unsigned, 8> PartUses;
343 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
344 unsigned SubReg = *SubRegs; ++SubRegs) {
345 if (MachineInstr *Use = PhysRegUse[SubReg]) {
346 PartUses.insert(SubReg);
347 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
348 PartUses.insert(*SS);
349 unsigned Dist = DistanceMap[Use];
350 if (Dist > LastRefOrPartRefDist) {
351 LastRefOrPartRefDist = Dist;
352 LastRefOrPartRef = Use;
357 if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI)
358 // If the last reference is the last def, then it's not used at all.
359 // That is, unless we are currently processing the last reference itself.
360 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
362 // Partial uses. Mark register def dead and add implicit def of
363 // sub-registers which are used.
364 // EAX<dead> = op AL<imp-def>
365 // That is, EAX def is dead but AL def extends pass it.
366 // Enable this after live interval analysis is fixed to improve codegen!
367 else if (!PhysRegUse[Reg]) {
368 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
369 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
370 unsigned SubReg = *SubRegs; ++SubRegs) {
371 if (PartUses.count(SubReg)) {
372 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
374 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
375 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
381 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
385 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
386 // What parts of the register are previously defined?
387 SmallSet<unsigned, 32> Live;
388 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
390 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
393 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
394 unsigned SubReg = *SubRegs; ++SubRegs) {
395 // If a register isn't itself defined, but all parts that make up of it
396 // are defined, then consider it also defined.
401 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
403 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
409 // Start from the largest piece, find the last time any part of the register
411 if (!HandlePhysRegKill(Reg, MI)) {
412 // Only some of the sub-registers are used.
413 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
414 unsigned SubReg = *SubRegs; ++SubRegs) {
415 if (!Live.count(SubReg))
416 // Skip if this sub-register isn't defined.
418 if (HandlePhysRegKill(SubReg, MI)) {
420 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
424 assert(Live.empty() && "Not all defined registers are killed / dead?");
428 // Does this extend the live range of a super-register?
429 SmallSet<unsigned, 8> Processed;
430 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
431 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
432 if (Processed.count(SuperReg))
434 MachineInstr *LastRef = PhysRegUse[SuperReg]
435 ? PhysRegUse[SuperReg] : PhysRegDef[SuperReg];
436 if (LastRef && LastRef != MI) {
437 // The larger register is previously defined. Now a smaller part is
438 // being re-defined. Treat it as read/mod/write if there are uses
441 // AX = EAX<imp-use,kill>, EAX<imp-def>
444 if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
445 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
446 true/*IsImp*/,true/*IsKill*/));
447 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
449 PhysRegDef[SuperReg] = MI;
450 PhysRegUse[SuperReg] = NULL;
451 Processed.insert(SuperReg);
452 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
453 PhysRegDef[*SS] = MI;
454 PhysRegUse[*SS] = NULL;
455 Processed.insert(*SS);
458 // Otherwise, the super register is killed.
459 if (HandlePhysRegKill(SuperReg, MI)) {
460 PhysRegDef[SuperReg] = NULL;
461 PhysRegUse[SuperReg] = NULL;
462 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
463 PhysRegDef[*SS] = NULL;
464 PhysRegUse[*SS] = NULL;
465 Processed.insert(*SS);
472 // Remember this def.
473 PhysRegDef[Reg] = MI;
474 PhysRegUse[Reg] = NULL;
475 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
476 unsigned SubReg = *SubRegs; ++SubRegs) {
477 PhysRegDef[SubReg] = MI;
478 PhysRegUse[SubReg] = NULL;
483 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
485 MRI = &mf.getRegInfo();
486 TRI = MF->getTarget().getRegisterInfo();
488 ReservedRegisters = TRI->getReservedRegs(mf);
490 unsigned NumRegs = TRI->getNumRegs();
491 PhysRegDef = new MachineInstr*[NumRegs];
492 PhysRegUse = new MachineInstr*[NumRegs];
493 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
494 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
495 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
497 /// Get some space for a respectable number of registers.
498 VirtRegInfo.resize(64);
502 // Calculate live variable information in depth first order on the CFG of the
503 // function. This guarantees that we will see the definition of a virtual
504 // register before its uses due to dominance properties of SSA (except for PHI
505 // nodes, which are treated as a special case).
506 MachineBasicBlock *Entry = MF->begin();
507 SmallPtrSet<MachineBasicBlock*,16> Visited;
509 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
510 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
512 MachineBasicBlock *MBB = *DFI;
514 // Mark live-in registers as live-in.
515 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
516 EE = MBB->livein_end(); II != EE; ++II) {
517 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
518 "Cannot have a live-in virtual register!");
519 HandlePhysRegDef(*II, 0);
522 // Loop over all of the instructions, processing them.
525 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
527 MachineInstr *MI = I;
528 DistanceMap.insert(std::make_pair(MI, Dist++));
530 // Process all of the operands of the instruction...
531 unsigned NumOperandsToProcess = MI->getNumOperands();
533 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
534 // of the uses. They will be handled in other basic blocks.
535 if (MI->getOpcode() == TargetInstrInfo::PHI)
536 NumOperandsToProcess = 1;
538 SmallVector<unsigned, 4> UseRegs;
539 SmallVector<unsigned, 4> DefRegs;
540 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
541 const MachineOperand &MO = MI->getOperand(i);
542 if (!MO.isReg() || MO.getReg() == 0)
544 unsigned MOReg = MO.getReg();
546 UseRegs.push_back(MOReg);
548 DefRegs.push_back(MOReg);
552 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
553 unsigned MOReg = UseRegs[i];
554 if (TargetRegisterInfo::isVirtualRegister(MOReg))
555 HandleVirtRegUse(MOReg, MBB, MI);
556 else if (!ReservedRegisters[MOReg])
557 HandlePhysRegUse(MOReg, MI);
561 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
562 unsigned MOReg = DefRegs[i];
563 if (TargetRegisterInfo::isVirtualRegister(MOReg))
564 HandleVirtRegDef(MOReg, MI);
565 else if (!ReservedRegisters[MOReg])
566 HandlePhysRegDef(MOReg, MI);
570 // Handle any virtual assignments from PHI nodes which might be at the
571 // bottom of this basic block. We check all of our successor blocks to see
572 // if they have PHI nodes, and if so, we simulate an assignment at the end
573 // of the current block.
574 if (!PHIVarInfo[MBB->getNumber()].empty()) {
575 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
577 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
578 E = VarInfoVec.end(); I != E; ++I)
579 // Mark it alive only in the block we are representing.
580 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
584 // Finally, if the last instruction in the block is a return, make sure to
585 // mark it as using all of the live-out values in the function.
586 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
587 MachineInstr *Ret = &MBB->back();
589 for (MachineRegisterInfo::liveout_iterator
590 I = MF->getRegInfo().liveout_begin(),
591 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
592 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
593 "Cannot have a live-out virtual register!");
594 HandlePhysRegUse(*I, Ret);
596 // Add live-out registers as implicit uses.
597 if (!Ret->readsRegister(*I))
598 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
602 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
603 // available at the end of the basic block.
604 for (unsigned i = 0; i != NumRegs; ++i)
605 if (PhysRegDef[i] || PhysRegUse[i])
606 HandlePhysRegDef(i, 0);
608 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
609 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
612 // Convert and transfer the dead / killed information we have gathered into
613 // VirtRegInfo onto MI's.
614 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
615 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
616 if (VirtRegInfo[i].Kills[j] ==
617 MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
619 .Kills[j]->addRegisterDead(i +
620 TargetRegisterInfo::FirstVirtualRegister,
624 .Kills[j]->addRegisterKilled(i +
625 TargetRegisterInfo::FirstVirtualRegister,
628 // Check to make sure there are no unreachable blocks in the MC CFG for the
629 // function. If so, it is due to a bug in the instruction selector or some
630 // other part of the code generator if this happens.
632 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
633 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
643 /// replaceKillInstruction - Update register kill info by replacing a kill
644 /// instruction with a new one.
645 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
646 MachineInstr *NewMI) {
647 VarInfo &VI = getVarInfo(Reg);
648 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
651 /// removeVirtualRegistersKilled - Remove all killed info for the specified
653 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
654 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
655 MachineOperand &MO = MI->getOperand(i);
656 if (MO.isReg() && MO.isKill()) {
658 unsigned Reg = MO.getReg();
659 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
660 bool removed = getVarInfo(Reg).removeKill(MI);
661 assert(removed && "kill not in register's VarInfo?");
668 /// analyzePHINodes - Gather information about the PHI nodes in here. In
669 /// particular, we want to map the variable information of a virtual register
670 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
672 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
673 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
675 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
676 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
677 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
678 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
679 .push_back(BBI->getOperand(i).getReg());