1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // This file implements the LiveVariable analysis pass. For each machine
4 // instruction in the function, this pass calculates the set of registers that
5 // are immediately dead after the instruction (i.e., the instruction calculates
6 // the value, but it is never used) and the set of registers that are used by
7 // the instruction, but are never used after the instruction (i.e., they are
10 // This class computes live variables using are sparse implementation based on
11 // the machine code SSA form. This class computes live variable information for
12 // each virtual and _register allocatable_ physical register in a function. It
13 // uses the dominance properties of SSA form to efficiently compute live
14 // variables for virtual registers, and assumes that physical registers are only
15 // live within a single basic block (allowing it to do a single local analysis
16 // to resolve physical register lifetimes in each basic block). If a physical
17 // register is not register allocatable, it is not tracked. This is useful for
18 // things like the stack pointer and condition codes.
20 //===----------------------------------------------------------------------===//
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/CFG.h"
27 #include "Support/DepthFirstIterator.h"
29 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
31 const std::pair<MachineBasicBlock*, unsigned> &
32 LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{
33 return BBMap.find(MBB->getBasicBlock())->second;
36 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
37 assert(RegIdx >= MRegisterInfo::FirstVirtualRegister &&
38 "getVarInfo: not a virtual register!");
39 RegIdx -= MRegisterInfo::FirstVirtualRegister;
40 if (RegIdx >= VirtRegInfo.size()) {
41 if (RegIdx >= 2*VirtRegInfo.size())
42 VirtRegInfo.resize(RegIdx*2);
44 VirtRegInfo.resize(2*VirtRegInfo.size());
46 return VirtRegInfo[RegIdx];
51 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
52 const BasicBlock *BB) {
53 const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second;
54 MachineBasicBlock *MBB = Info.first;
55 unsigned BBNum = Info.second;
57 // Check to see if this basic block is one of the killing blocks. If so,
59 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
60 if (VRInfo.Kills[i].first == MBB) {
61 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
65 if (MBB == VRInfo.DefBlock) return; // Terminate recursion
67 if (VRInfo.AliveBlocks.size() <= BBNum)
68 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
70 if (VRInfo.AliveBlocks[BBNum])
71 return; // We already know the block is live
73 // Mark the variable known alive in this bb
74 VRInfo.AliveBlocks[BBNum] = true;
76 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
77 MarkVirtRegAliveInBlock(VRInfo, *PI);
80 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
82 // Check to see if this basic block is already a kill block...
83 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
84 // Yes, this register is killed in this basic block already. Increase the
85 // live range by updating the kill instruction.
86 VRInfo.Kills.back().second = MI;
91 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
92 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
95 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
97 // Add a new kill entry for this basic block.
98 VRInfo.Kills.push_back(std::make_pair(MBB, MI));
100 // Update all dominating blocks to mark them known live.
101 const BasicBlock *BB = MBB->getBasicBlock();
102 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB);
104 MarkVirtRegAliveInBlock(VRInfo, *PI);
107 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
108 if (PhysRegInfo[Reg]) {
109 PhysRegInfo[Reg] = MI;
110 PhysRegUsed[Reg] = true;
111 } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
112 for (; unsigned NReg = AliasSet[0]; ++AliasSet)
113 if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
114 PhysRegInfo[NReg] = MI;
115 PhysRegUsed[NReg] = true;
120 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
121 // Does this kill a previous version of this register?
122 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
123 if (PhysRegUsed[Reg])
124 RegistersKilled.insert(std::make_pair(LastUse, Reg));
126 RegistersDead.insert(std::make_pair(LastUse, Reg));
127 } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
128 for (; unsigned NReg = AliasSet[0]; ++AliasSet)
129 if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
130 if (PhysRegUsed[NReg])
131 RegistersKilled.insert(std::make_pair(LastUse, NReg));
133 RegistersDead.insert(std::make_pair(LastUse, NReg));
134 PhysRegInfo[NReg] = 0; // Kill the aliased register
137 PhysRegInfo[Reg] = MI;
138 PhysRegUsed[Reg] = false;
141 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
142 // First time though, initialize AllocatablePhysicalRegisters for the target
143 if (AllocatablePhysicalRegisters.empty()) {
144 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
145 assert(&MRI && "Target doesn't have register information?");
147 // Make space, initializing to false...
148 AllocatablePhysicalRegisters.resize(MRegisterInfo::FirstVirtualRegister);
150 // Loop over all of the register classes...
151 for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(),
152 E = MRI.regclass_end(); RCI != E; ++RCI)
153 // Loop over all of the allocatable registers in the function...
154 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
155 E = (*RCI)->allocation_order_end(MF); I != E; ++I)
156 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
161 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
162 BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++);
164 // PhysRegInfo - Keep track of which instruction was the last use of a
165 // physical register. This is a purely local property, because all physical
166 // register references as presumed dead across basic blocks.
168 MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
169 bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
170 std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
172 PhysRegInfo = PhysRegInfoA;
173 PhysRegUsed = PhysRegUsedA;
175 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
176 RegInfo = MF.getTarget().getRegisterInfo();
178 /// Get some space for a respectable number of registers...
179 VirtRegInfo.resize(64);
181 // Calculate live variable information in depth first order on the CFG of the
182 // function. This guarantees that we will see the definition of a virtual
183 // register before its uses due to dominance properties of SSA (except for PHI
184 // nodes, which are treated as a special case).
186 const BasicBlock *Entry = MF.getFunction()->begin();
187 for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
189 const BasicBlock *BB = *DFI;
190 std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second;
191 MachineBasicBlock *MBB = BBRec.first;
192 unsigned BBNum = BBRec.second;
194 // Loop over all of the instructions, processing them.
195 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
197 MachineInstr *MI = *I;
198 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
200 // Process all of the operands of the instruction...
201 unsigned NumOperandsToProcess = MI->getNumOperands();
203 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
204 // of the uses. They will be handled in other basic blocks.
205 if (MI->getOpcode() == TargetInstrInfo::PHI)
206 NumOperandsToProcess = 1;
208 // Loop over implicit uses, using them.
209 if (const unsigned *ImplicitUses = MID.ImplicitUses)
210 for (unsigned i = 0; ImplicitUses[i]; ++i)
211 HandlePhysRegUse(ImplicitUses[i], MI);
213 // Process all explicit uses...
214 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
215 MachineOperand &MO = MI->getOperand(i);
216 if (MO.opIsUse() || MO.opIsDefAndUse()) {
217 if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
218 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
219 } else if (MO.isPhysicalRegister() &&
220 AllocatablePhysicalRegisters[MO.getReg()]) {
221 HandlePhysRegUse(MO.getReg(), MI);
226 // Loop over implicit defs, defining them.
227 if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
228 for (unsigned i = 0; ImplicitDefs[i]; ++i)
229 HandlePhysRegDef(ImplicitDefs[i], MI);
231 // Process all explicit defs...
232 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
233 MachineOperand &MO = MI->getOperand(i);
234 if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
235 if (MO.isVirtualRegister()) {
236 VarInfo &VRInfo = getVarInfo(MO.getReg());
238 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
239 VRInfo.DefBlock = MBB; // Created here...
241 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
242 } else if (MO.isPhysicalRegister() &&
243 AllocatablePhysicalRegisters[MO.getReg()]) {
244 HandlePhysRegDef(MO.getReg(), MI);
250 // Handle any virtual assignments from PHI nodes which might be at the
251 // bottom of this basic block. We check all of our successor blocks to see
252 // if they have PHI nodes, and if so, we simulate an assignment at the end
253 // of the current block.
254 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB);
256 MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
258 // PHI nodes are guaranteed to be at the top of the block...
259 for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
260 I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
261 MachineInstr *MI = *I;
262 for (unsigned i = 1; ; i += 2)
263 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
264 MachineOperand &MO = MI->getOperand(i);
265 if (!MO.getVRegValueOrNull()) {
266 VarInfo &VRInfo = getVarInfo(MO.getReg());
268 // Only mark it alive only in the block we are representing...
269 MarkVirtRegAliveInBlock(VRInfo, BB);
270 break; // Found the PHI entry for this block...
276 // Loop over PhysRegInfo, killing any registers that are available at the
277 // end of the basic block. This also resets the PhysRegInfo map.
278 for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i)
280 HandlePhysRegDef(i, 0);
283 // Convert the information we have gathered into VirtRegInfo and transform it
284 // into a form usable by RegistersKilled.
286 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
287 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
288 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
289 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
290 i + MRegisterInfo::FirstVirtualRegister));
293 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
294 i + MRegisterInfo::FirstVirtualRegister));