1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/STLExtras.h"
43 char LiveVariables::ID = 0;
44 INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
45 "Live Variable Analysis", false, false)
46 INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
47 INITIALIZE_PASS_END(LiveVariables, "livevars",
48 "Live Variable Analysis", false, false)
51 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
52 AU.addRequiredID(UnreachableMachineBlockElimID);
54 MachineFunctionPass::getAnalysisUsage(AU);
58 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
59 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
60 if (Kills[i]->getParent() == MBB)
65 void LiveVariables::VarInfo::dump() const {
66 dbgs() << " Alive in blocks: ";
67 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
68 E = AliveBlocks.end(); I != E; ++I)
70 dbgs() << "\n Killed by:";
72 dbgs() << " No instructions.\n";
74 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
75 dbgs() << "\n #" << i << ": " << *Kills[i];
80 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
81 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
82 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
83 "getVarInfo: not a virtual register!");
84 VirtRegInfo.grow(RegIdx);
85 return VirtRegInfo[RegIdx];
88 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
89 MachineBasicBlock *DefBlock,
90 MachineBasicBlock *MBB,
91 std::vector<MachineBasicBlock*> &WorkList) {
92 unsigned BBNum = MBB->getNumber();
94 // Check to see if this basic block is one of the killing blocks. If so,
96 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
97 if (VRInfo.Kills[i]->getParent() == MBB) {
98 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
102 if (MBB == DefBlock) return; // Terminate recursion
104 if (VRInfo.AliveBlocks.test(BBNum))
105 return; // We already know the block is live
107 // Mark the variable known alive in this bb
108 VRInfo.AliveBlocks.set(BBNum);
110 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
111 E = MBB->pred_rend(); PI != E; ++PI)
112 WorkList.push_back(*PI);
115 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
116 MachineBasicBlock *DefBlock,
117 MachineBasicBlock *MBB) {
118 std::vector<MachineBasicBlock*> WorkList;
119 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
121 while (!WorkList.empty()) {
122 MachineBasicBlock *Pred = WorkList.back();
124 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
128 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
130 assert(MRI->getVRegDef(reg) && "Register use before def!");
132 unsigned BBNum = MBB->getNumber();
134 VarInfo& VRInfo = getVarInfo(reg);
137 // Check to see if this basic block is already a kill block.
138 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
139 // Yes, this register is killed in this basic block already. Increase the
140 // live range by updating the kill instruction.
141 VRInfo.Kills.back() = MI;
146 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
147 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
150 // This situation can occur:
155 // | t2 = phi ... t1 ...
159 // | ... = ... t1 ...
163 // where there is a use in a PHI node that's a predecessor to the defining
164 // block. We don't want to mark all predecessors as having the value "alive"
166 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
168 // Add a new kill entry for this basic block. If this virtual register is
169 // already marked as alive in this basic block, that means it is alive in at
170 // least one of the successor blocks, it's not a kill.
171 if (!VRInfo.AliveBlocks.test(BBNum))
172 VRInfo.Kills.push_back(MI);
174 // Update all dominating blocks to mark them as "known live".
175 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
176 E = MBB->pred_end(); PI != E; ++PI)
177 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
180 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
181 VarInfo &VRInfo = getVarInfo(Reg);
183 if (VRInfo.AliveBlocks.empty())
184 // If vr is not alive in any block, then defaults to dead.
185 VRInfo.Kills.push_back(MI);
188 /// FindLastPartialDef - Return the last partial def of the specified register.
189 /// Also returns the sub-registers that're defined by the instruction.
190 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
191 SmallSet<unsigned,4> &PartDefRegs) {
192 unsigned LastDefReg = 0;
193 unsigned LastDefDist = 0;
194 MachineInstr *LastDef = NULL;
195 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
196 unsigned SubReg = *SubRegs; ++SubRegs) {
197 MachineInstr *Def = PhysRegDef[SubReg];
200 unsigned Dist = DistanceMap[Def];
201 if (Dist > LastDefDist) {
211 PartDefRegs.insert(LastDefReg);
212 for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
213 MachineOperand &MO = LastDef->getOperand(i);
214 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
216 unsigned DefReg = MO.getReg();
217 if (TRI->isSubRegister(Reg, DefReg)) {
218 PartDefRegs.insert(DefReg);
219 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
220 unsigned SubReg = *SubRegs; ++SubRegs)
221 PartDefRegs.insert(SubReg);
227 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
228 /// implicit defs to a machine instruction if there was an earlier def of its
230 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
231 MachineInstr *LastDef = PhysRegDef[Reg];
232 // If there was a previous use or a "full" def all is well.
233 if (!LastDef && !PhysRegUse[Reg]) {
234 // Otherwise, the last sub-register def implicitly defines this register.
237 // AL = ... <imp-def EAX>, <imp-kill AH>
241 // All of the sub-registers must have been defined before the use of Reg!
242 SmallSet<unsigned, 4> PartDefRegs;
243 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
244 // If LastPartialDef is NULL, it must be using a livein register.
245 if (LastPartialDef) {
246 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
248 PhysRegDef[Reg] = LastPartialDef;
249 SmallSet<unsigned, 8> Processed;
250 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
251 unsigned SubReg = *SubRegs; ++SubRegs) {
252 if (Processed.count(SubReg))
254 if (PartDefRegs.count(SubReg))
256 // This part of Reg was defined before the last partial def. It's killed
258 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
261 PhysRegDef[SubReg] = LastPartialDef;
262 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
263 Processed.insert(*SS);
267 else if (LastDef && !PhysRegUse[Reg] &&
268 !LastDef->findRegisterDefOperand(Reg))
269 // Last def defines the super register, add an implicit def of reg.
270 LastDef->addOperand(MachineOperand::CreateReg(Reg,
271 true/*IsDef*/, true/*IsImp*/));
273 // Remember this use.
274 PhysRegUse[Reg] = MI;
275 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
276 unsigned SubReg = *SubRegs; ++SubRegs)
277 PhysRegUse[SubReg] = MI;
280 /// FindLastRefOrPartRef - Return the last reference or partial reference of
281 /// the specified register.
282 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
283 MachineInstr *LastDef = PhysRegDef[Reg];
284 MachineInstr *LastUse = PhysRegUse[Reg];
285 if (!LastDef && !LastUse)
288 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
289 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
290 unsigned LastPartDefDist = 0;
291 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
292 unsigned SubReg = *SubRegs; ++SubRegs) {
293 MachineInstr *Def = PhysRegDef[SubReg];
294 if (Def && Def != LastDef) {
295 // There was a def of this sub-register in between. This is a partial
296 // def, keep track of the last one.
297 unsigned Dist = DistanceMap[Def];
298 if (Dist > LastPartDefDist)
299 LastPartDefDist = Dist;
300 } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
301 unsigned Dist = DistanceMap[Use];
302 if (Dist > LastRefOrPartRefDist) {
303 LastRefOrPartRefDist = Dist;
304 LastRefOrPartRef = Use;
309 return LastRefOrPartRef;
312 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
313 MachineInstr *LastDef = PhysRegDef[Reg];
314 MachineInstr *LastUse = PhysRegUse[Reg];
315 if (!LastDef && !LastUse)
318 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
319 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
320 // The whole register is used.
325 // = AL, AX<imp-use, kill>
328 // Or whole register is defined, but not used at all.
333 // Or whole register is defined, but only partly used.
334 // AX<dead> = AL<imp-def>
337 MachineInstr *LastPartDef = 0;
338 unsigned LastPartDefDist = 0;
339 SmallSet<unsigned, 8> PartUses;
340 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
341 unsigned SubReg = *SubRegs; ++SubRegs) {
342 MachineInstr *Def = PhysRegDef[SubReg];
343 if (Def && Def != LastDef) {
344 // There was a def of this sub-register in between. This is a partial
345 // def, keep track of the last one.
346 unsigned Dist = DistanceMap[Def];
347 if (Dist > LastPartDefDist) {
348 LastPartDefDist = Dist;
353 if (MachineInstr *Use = PhysRegUse[SubReg]) {
354 PartUses.insert(SubReg);
355 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
356 PartUses.insert(*SS);
357 unsigned Dist = DistanceMap[Use];
358 if (Dist > LastRefOrPartRefDist) {
359 LastRefOrPartRefDist = Dist;
360 LastRefOrPartRef = Use;
365 if (!PhysRegUse[Reg]) {
366 // Partial uses. Mark register def dead and add implicit def of
367 // sub-registers which are used.
368 // EAX<dead> = op AL<imp-def>
369 // That is, EAX def is dead but AL def extends pass it.
370 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
371 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
372 unsigned SubReg = *SubRegs; ++SubRegs) {
373 if (!PartUses.count(SubReg))
376 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
377 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
380 assert(!MO->isDead());
384 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
385 true/*IsDef*/, true/*IsImp*/));
386 MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
388 LastSubRef->addRegisterKilled(SubReg, TRI, true);
390 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
391 PhysRegUse[SubReg] = LastRefOrPartRef;
392 for (const unsigned *SSRegs = TRI->getSubRegisters(SubReg);
393 unsigned SSReg = *SSRegs; ++SSRegs)
394 PhysRegUse[SSReg] = LastRefOrPartRef;
396 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
399 } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
401 // The last partial def kills the register.
402 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
403 true/*IsImp*/, true/*IsKill*/));
406 LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
407 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
408 // If the last reference is the last def, then it's not used at all.
409 // That is, unless we are currently processing the last reference itself.
410 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
412 // If we are adding a subreg def and the superreg def is marked early
413 // clobber, add an early clobber marker to the subreg def.
414 MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
416 MO->setIsEarlyClobber();
420 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
424 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
425 SmallVector<unsigned, 4> &Defs) {
426 // What parts of the register are previously defined?
427 SmallSet<unsigned, 32> Live;
428 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
430 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
433 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
434 unsigned SubReg = *SubRegs; ++SubRegs) {
435 // If a register isn't itself defined, but all parts that make up of it
436 // are defined, then consider it also defined.
441 if (Live.count(SubReg))
443 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
445 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
451 // Start from the largest piece, find the last time any part of the register
453 HandlePhysRegKill(Reg, MI);
454 // Only some of the sub-registers are used.
455 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
456 unsigned SubReg = *SubRegs; ++SubRegs) {
457 if (!Live.count(SubReg))
458 // Skip if this sub-register isn't defined.
460 HandlePhysRegKill(SubReg, MI);
464 Defs.push_back(Reg); // Remember this def.
467 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
468 SmallVector<unsigned, 4> &Defs) {
469 while (!Defs.empty()) {
470 unsigned Reg = Defs.back();
472 PhysRegDef[Reg] = MI;
473 PhysRegUse[Reg] = NULL;
474 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
475 unsigned SubReg = *SubRegs; ++SubRegs) {
476 PhysRegDef[SubReg] = MI;
477 PhysRegUse[SubReg] = NULL;
482 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
484 MRI = &mf.getRegInfo();
485 TRI = MF->getTarget().getRegisterInfo();
487 ReservedRegisters = TRI->getReservedRegs(mf);
489 unsigned NumRegs = TRI->getNumRegs();
490 PhysRegDef = new MachineInstr*[NumRegs];
491 PhysRegUse = new MachineInstr*[NumRegs];
492 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
493 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
494 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
499 // Calculate live variable information in depth first order on the CFG of the
500 // function. This guarantees that we will see the definition of a virtual
501 // register before its uses due to dominance properties of SSA (except for PHI
502 // nodes, which are treated as a special case).
503 MachineBasicBlock *Entry = MF->begin();
504 SmallPtrSet<MachineBasicBlock*,16> Visited;
506 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
507 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
509 MachineBasicBlock *MBB = *DFI;
511 // Mark live-in registers as live-in.
512 SmallVector<unsigned, 4> Defs;
513 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
514 EE = MBB->livein_end(); II != EE; ++II) {
515 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
516 "Cannot have a live-in virtual register!");
517 HandlePhysRegDef(*II, 0, Defs);
520 // Loop over all of the instructions, processing them.
523 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
525 MachineInstr *MI = I;
526 if (MI->isDebugValue())
528 DistanceMap.insert(std::make_pair(MI, Dist++));
530 // Process all of the operands of the instruction...
531 unsigned NumOperandsToProcess = MI->getNumOperands();
533 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
534 // of the uses. They will be handled in other basic blocks.
536 NumOperandsToProcess = 1;
538 // Clear kill and dead markers. LV will recompute them.
539 SmallVector<unsigned, 4> UseRegs;
540 SmallVector<unsigned, 4> DefRegs;
541 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
542 MachineOperand &MO = MI->getOperand(i);
543 if (!MO.isReg() || MO.getReg() == 0)
545 unsigned MOReg = MO.getReg();
548 UseRegs.push_back(MOReg);
549 } else /*MO.isDef()*/ {
551 DefRegs.push_back(MOReg);
556 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
557 unsigned MOReg = UseRegs[i];
558 if (TargetRegisterInfo::isVirtualRegister(MOReg))
559 HandleVirtRegUse(MOReg, MBB, MI);
560 else if (!ReservedRegisters[MOReg])
561 HandlePhysRegUse(MOReg, MI);
565 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
566 unsigned MOReg = DefRegs[i];
567 if (TargetRegisterInfo::isVirtualRegister(MOReg))
568 HandleVirtRegDef(MOReg, MI);
569 else if (!ReservedRegisters[MOReg])
570 HandlePhysRegDef(MOReg, MI, Defs);
572 UpdatePhysRegDefs(MI, Defs);
575 // Handle any virtual assignments from PHI nodes which might be at the
576 // bottom of this basic block. We check all of our successor blocks to see
577 // if they have PHI nodes, and if so, we simulate an assignment at the end
578 // of the current block.
579 if (!PHIVarInfo[MBB->getNumber()].empty()) {
580 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
582 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
583 E = VarInfoVec.end(); I != E; ++I)
584 // Mark it alive only in the block we are representing.
585 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
589 // Finally, if the last instruction in the block is a return, make sure to
590 // mark it as using all of the live-out values in the function.
591 // Things marked both call and return are tail calls; do not do this for
592 // them. The tail callee need not take the same registers as input
593 // that it produces as output, and there are dependencies for its input
594 // registers elsewhere.
595 if (!MBB->empty() && MBB->back().getDesc().isReturn()
596 && !MBB->back().getDesc().isCall()) {
597 MachineInstr *Ret = &MBB->back();
599 for (MachineRegisterInfo::liveout_iterator
600 I = MF->getRegInfo().liveout_begin(),
601 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
602 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
603 "Cannot have a live-out virtual register!");
604 HandlePhysRegUse(*I, Ret);
606 // Add live-out registers as implicit uses.
607 if (!Ret->readsRegister(*I))
608 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
612 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
613 // available at the end of the basic block.
614 for (unsigned i = 0; i != NumRegs; ++i)
615 if (PhysRegDef[i] || PhysRegUse[i])
616 HandlePhysRegDef(i, 0, Defs);
618 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
619 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
622 // Convert and transfer the dead / killed information we have gathered into
623 // VirtRegInfo onto MI's.
624 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
625 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
626 for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
627 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
628 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
630 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
633 // Check to make sure there are no unreachable blocks in the MC CFG for the
634 // function. If so, it is due to a bug in the instruction selector or some
635 // other part of the code generator if this happens.
637 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
638 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
648 /// replaceKillInstruction - Update register kill info by replacing a kill
649 /// instruction with a new one.
650 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
651 MachineInstr *NewMI) {
652 VarInfo &VI = getVarInfo(Reg);
653 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
656 /// removeVirtualRegistersKilled - Remove all killed info for the specified
658 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
659 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
660 MachineOperand &MO = MI->getOperand(i);
661 if (MO.isReg() && MO.isKill()) {
663 unsigned Reg = MO.getReg();
664 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
665 bool removed = getVarInfo(Reg).removeKill(MI);
666 assert(removed && "kill not in register's VarInfo?");
673 /// analyzePHINodes - Gather information about the PHI nodes in here. In
674 /// particular, we want to map the variable information of a virtual register
675 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
677 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
678 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
680 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
681 BBI != BBE && BBI->isPHI(); ++BBI)
682 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
683 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
684 .push_back(BBI->getOperand(i).getReg());
687 bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
689 MachineRegisterInfo &MRI) {
690 unsigned Num = MBB.getNumber();
692 // Reg is live-through.
693 if (AliveBlocks.test(Num))
696 // Registers defined in MBB cannot be live in.
697 const MachineInstr *Def = MRI.getVRegDef(Reg);
698 if (Def && Def->getParent() == &MBB)
701 // Reg was not defined in MBB, was it killed here?
702 return findKill(&MBB);
705 bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
706 LiveVariables::VarInfo &VI = getVarInfo(Reg);
708 // Loop over all of the successors of the basic block, checking to see if
709 // the value is either live in the block, or if it is killed in the block.
710 std::vector<MachineBasicBlock*> OpSuccBlocks;
711 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
712 E = MBB.succ_end(); SI != E; ++SI) {
713 MachineBasicBlock *SuccMBB = *SI;
715 // Is it alive in this successor?
716 unsigned SuccIdx = SuccMBB->getNumber();
717 if (VI.AliveBlocks.test(SuccIdx))
719 OpSuccBlocks.push_back(SuccMBB);
722 // Check to see if this value is live because there is a use in a successor
724 switch (OpSuccBlocks.size()) {
726 MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
727 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
728 if (VI.Kills[i]->getParent() == SuccMBB)
733 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
734 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
735 if (VI.Kills[i]->getParent() == SuccMBB1 ||
736 VI.Kills[i]->getParent() == SuccMBB2)
741 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
742 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
743 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
744 VI.Kills[i]->getParent()))
750 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
751 /// variables that are live out of DomBB will be marked as passing live through
753 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
754 MachineBasicBlock *DomBB,
755 MachineBasicBlock *SuccBB) {
756 const unsigned NumNew = BB->getNumber();
758 // All registers used by PHI nodes in SuccBB must be live through BB.
759 for (MachineBasicBlock::const_iterator BBI = SuccBB->begin(),
760 BBE = SuccBB->end(); BBI != BBE && BBI->isPHI(); ++BBI)
761 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
762 if (BBI->getOperand(i+1).getMBB() == BB)
763 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
765 // Update info for all live variables
766 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
767 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
768 VarInfo &VI = getVarInfo(Reg);
769 if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
770 VI.AliveBlocks.set(NumNew);