1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/MRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "Support/DepthFirstIterator.h"
35 #include "Support/STLExtras.h"
38 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
40 /// getIndexMachineBasicBlock() - Given a block index, return the
41 /// MachineBasicBlock corresponding to it.
42 MachineBasicBlock *LiveVariables::getIndexMachineBasicBlock(unsigned Idx) {
43 if (BBIdxMap.empty()) {
44 BBIdxMap.resize(BBMap.size());
45 for (std::map<MachineBasicBlock*, unsigned>::iterator I = BBMap.begin(),
46 E = BBMap.end(); I != E; ++I) {
47 assert(BBIdxMap.size() > I->second && "Indices are not sequential");
48 assert(BBIdxMap[I->second] == 0 && "Multiple idx collision!");
49 BBIdxMap[I->second] = I->first;
52 assert(Idx < BBIdxMap.size() && "BB Index out of range!");
56 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
57 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
58 "getVarInfo: not a virtual register!");
59 RegIdx -= MRegisterInfo::FirstVirtualRegister;
60 if (RegIdx >= VirtRegInfo.size()) {
61 if (RegIdx >= 2*VirtRegInfo.size())
62 VirtRegInfo.resize(RegIdx*2);
64 VirtRegInfo.resize(2*VirtRegInfo.size());
66 return VirtRegInfo[RegIdx];
71 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
72 MachineBasicBlock *MBB) {
73 unsigned BBNum = getMachineBasicBlockIndex(MBB);
75 // Check to see if this basic block is one of the killing blocks. If so,
77 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
78 if (VRInfo.Kills[i].first == MBB) {
79 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
83 if (MBB == VRInfo.DefBlock) return; // Terminate recursion
85 if (VRInfo.AliveBlocks.size() <= BBNum)
86 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
88 if (VRInfo.AliveBlocks[BBNum])
89 return; // We already know the block is live
91 // Mark the variable known alive in this bb
92 VRInfo.AliveBlocks[BBNum] = true;
94 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
95 E = MBB->pred_end(); PI != E; ++PI)
96 MarkVirtRegAliveInBlock(VRInfo, *PI);
99 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
101 // Check to see if this basic block is already a kill block...
102 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
103 // Yes, this register is killed in this basic block already. Increase the
104 // live range by updating the kill instruction.
105 VRInfo.Kills.back().second = MI;
110 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
111 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
114 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
116 // Add a new kill entry for this basic block.
117 VRInfo.Kills.push_back(std::make_pair(MBB, MI));
119 // Update all dominating blocks to mark them known live.
120 const BasicBlock *BB = MBB->getBasicBlock();
121 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
122 E = MBB->pred_end(); PI != E; ++PI)
123 MarkVirtRegAliveInBlock(VRInfo, *PI);
126 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
127 PhysRegInfo[Reg] = MI;
128 PhysRegUsed[Reg] = true;
131 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
132 // Does this kill a previous version of this register?
133 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
134 if (PhysRegUsed[Reg])
135 RegistersKilled.insert(std::make_pair(LastUse, Reg));
137 RegistersDead.insert(std::make_pair(LastUse, Reg));
139 PhysRegInfo[Reg] = MI;
140 PhysRegUsed[Reg] = false;
142 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
143 *AliasSet; ++AliasSet) {
144 unsigned Alias = *AliasSet;
145 if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
146 if (PhysRegUsed[Alias])
147 RegistersKilled.insert(std::make_pair(LastUse, Alias));
149 RegistersDead.insert(std::make_pair(LastUse, Alias));
151 PhysRegInfo[Alias] = MI;
152 PhysRegUsed[Alias] = false;
156 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
157 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
158 RegInfo = MF.getTarget().getRegisterInfo();
159 assert(RegInfo && "Target doesn't have register information?");
161 // First time though, initialize AllocatablePhysicalRegisters for the target
162 if (AllocatablePhysicalRegisters.empty()) {
163 // Make space, initializing to false...
164 AllocatablePhysicalRegisters.resize(RegInfo->getNumRegs());
166 // Loop over all of the register classes...
167 for (MRegisterInfo::regclass_iterator RCI = RegInfo->regclass_begin(),
168 E = RegInfo->regclass_end(); RCI != E; ++RCI)
169 // Loop over all of the allocatable registers in the function...
170 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
171 E = (*RCI)->allocation_order_end(MF); I != E; ++I)
172 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
177 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
180 // PhysRegInfo - Keep track of which instruction was the last use of a
181 // physical register. This is a purely local property, because all physical
182 // register references as presumed dead across basic blocks.
184 MachineInstr *PhysRegInfoA[RegInfo->getNumRegs()];
185 bool PhysRegUsedA[RegInfo->getNumRegs()];
186 std::fill(PhysRegInfoA, PhysRegInfoA+RegInfo->getNumRegs(), (MachineInstr*)0);
187 PhysRegInfo = PhysRegInfoA;
188 PhysRegUsed = PhysRegUsedA;
190 /// Get some space for a respectable number of registers...
191 VirtRegInfo.resize(64);
193 // Calculate live variable information in depth first order on the CFG of the
194 // function. This guarantees that we will see the definition of a virtual
195 // register before its uses due to dominance properties of SSA (except for PHI
196 // nodes, which are treated as a special case).
198 MachineBasicBlock *Entry = MF.begin();
199 for (df_iterator<MachineBasicBlock*> DFI = df_begin(Entry), E = df_end(Entry);
201 MachineBasicBlock *MBB = *DFI;
202 unsigned BBNum = getMachineBasicBlockIndex(MBB);
204 // Loop over all of the instructions, processing them.
205 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
207 MachineInstr *MI = I;
208 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
210 // Process all of the operands of the instruction...
211 unsigned NumOperandsToProcess = MI->getNumOperands();
213 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
214 // of the uses. They will be handled in other basic blocks.
215 if (MI->getOpcode() == TargetInstrInfo::PHI)
216 NumOperandsToProcess = 1;
218 // Loop over implicit uses, using them.
219 for (const unsigned *ImplicitUses = MID.ImplicitUses;
220 *ImplicitUses; ++ImplicitUses)
221 HandlePhysRegUse(*ImplicitUses, MI);
223 // Process all explicit uses...
224 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
225 MachineOperand &MO = MI->getOperand(i);
226 if (MO.isUse() && MO.isRegister() && MO.getReg()) {
227 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
228 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
229 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
230 AllocatablePhysicalRegisters[MO.getReg()]) {
231 HandlePhysRegUse(MO.getReg(), MI);
236 // Loop over implicit defs, defining them.
237 for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
238 *ImplicitDefs; ++ImplicitDefs)
239 HandlePhysRegDef(*ImplicitDefs, MI);
241 // Process all explicit defs...
242 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
243 MachineOperand &MO = MI->getOperand(i);
244 if (MO.isDef() && MO.isRegister() && MO.getReg()) {
245 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
246 VarInfo &VRInfo = getVarInfo(MO.getReg());
248 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
249 VRInfo.DefBlock = MBB; // Created here...
251 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
252 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
253 AllocatablePhysicalRegisters[MO.getReg()]) {
254 HandlePhysRegDef(MO.getReg(), MI);
260 // Handle any virtual assignments from PHI nodes which might be at the
261 // bottom of this basic block. We check all of our successor blocks to see
262 // if they have PHI nodes, and if so, we simulate an assignment at the end
263 // of the current block.
264 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
265 E = MBB->succ_end(); SI != E; ++SI) {
266 MachineBasicBlock *Succ = *SI;
268 // PHI nodes are guaranteed to be at the top of the block...
269 for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
270 MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
271 for (unsigned i = 1; ; i += 2) {
272 assert(MI->getNumOperands() > i+1 &&
273 "Didn't find an entry for our predecessor??");
274 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
275 MachineOperand &MO = MI->getOperand(i);
276 if (!MO.getVRegValueOrNull()) {
277 VarInfo &VRInfo = getVarInfo(MO.getReg());
279 // Only mark it alive only in the block we are representing...
280 MarkVirtRegAliveInBlock(VRInfo, MBB);
281 break; // Found the PHI entry for this block...
288 // Loop over PhysRegInfo, killing any registers that are available at the
289 // end of the basic block. This also resets the PhysRegInfo map.
290 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
292 HandlePhysRegDef(i, 0);
295 // Convert the information we have gathered into VirtRegInfo and transform it
296 // into a form usable by RegistersKilled.
298 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
299 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
300 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
301 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
302 i + MRegisterInfo::FirstVirtualRegister));
305 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
306 i + MRegisterInfo::FirstVirtualRegister));
312 /// instructionChanged - When the address of an instruction changes, this
313 /// method should be called so that live variables can update its internal
314 /// data structures. This removes the records for OldMI, transfering them to
315 /// the records for NewMI.
316 void LiveVariables::instructionChanged(MachineInstr *OldMI,
317 MachineInstr *NewMI) {
318 // If the instruction defines any virtual registers, update the VarInfo for
320 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
321 MachineOperand &MO = OldMI->getOperand(i);
322 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
323 MRegisterInfo::isVirtualRegister(MO.getReg())) {
324 unsigned Reg = MO.getReg();
325 VarInfo &VI = getVarInfo(Reg);
326 if (VI.DefInst == OldMI)
331 // Move the killed information over...
332 killed_iterator I, E;
333 tie(I, E) = killed_range(OldMI);
334 std::vector<unsigned> Regs;
335 for (killed_iterator A = I; A != E; ++A)
336 Regs.push_back(A->second);
337 RegistersKilled.erase(I, E);
339 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
340 RegistersKilled.insert(std::make_pair(NewMI, Regs[i]));
344 // Move the dead information over...
345 tie(I, E) = dead_range(OldMI);
346 for (killed_iterator A = I; A != E; ++A)
347 Regs.push_back(A->second);
348 RegistersDead.erase(I, E);
350 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
351 RegistersDead.insert(std::make_pair(NewMI, Regs[i]));