1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 /// runOnMachineFunction - pass entry point
34 bool runOnMachineFunction(MachineFunction&);
36 bool LowerExtract(MachineInstr *MI);
37 bool LowerInsert(MachineInstr *MI);
38 bool LowerSubregToReg(MachineInstr *MI);
41 char LowerSubregsInstructionPass::ID = 0;
44 FunctionPass *llvm::createLowerSubregsPass() {
45 return new LowerSubregsInstructionPass();
48 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
49 MachineBasicBlock *MBB = MI->getParent();
50 MachineFunction &MF = *MBB->getParent();
51 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
52 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
54 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
55 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
56 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
58 unsigned DstReg = MI->getOperand(0).getReg();
59 unsigned SuperReg = MI->getOperand(1).getReg();
60 unsigned SubIdx = MI->getOperand(2).getImm();
61 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
63 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
64 "Extract supperg source must be a physical register");
65 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
66 "Insert destination must be in a physical register");
68 DOUT << "subreg: CONVERTING: " << *MI;
70 if (SrcReg != DstReg) {
71 const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
72 assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
73 "Extract subreg and Dst must be of same register class");
74 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
77 MachineBasicBlock::iterator dMI = MI;
78 DOUT << "subreg: " << *(--dMI);
87 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
88 MachineBasicBlock *MBB = MI->getParent();
89 MachineFunction &MF = *MBB->getParent();
90 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
91 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
92 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
93 MI->getOperand(1).isImmediate() &&
94 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
95 MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg");
97 unsigned DstReg = MI->getOperand(0).getReg();
98 unsigned InsReg = MI->getOperand(2).getReg();
99 unsigned SubIdx = MI->getOperand(3).getImm();
101 assert(SubIdx != 0 && "Invalid index for insert_subreg");
102 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
104 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
105 "Insert destination must be in a physical register");
106 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
107 "Inserted value must be in a physical register");
109 DOUT << "subreg: CONVERTING: " << *MI;
111 // Insert sub-register copy
112 const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg);
113 const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
114 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
117 MachineBasicBlock::iterator dMI = MI;
118 DOUT << "subreg: " << *(--dMI);
126 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
127 MachineBasicBlock *MBB = MI->getParent();
128 MachineFunction &MF = *MBB->getParent();
129 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
130 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
131 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
132 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
133 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
134 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
136 unsigned DstReg = MI->getOperand(0).getReg();
137 unsigned SrcReg = MI->getOperand(1).getReg();
138 unsigned InsReg = MI->getOperand(2).getReg();
139 unsigned SubIdx = MI->getOperand(3).getImm();
141 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
142 assert(SubIdx != 0 && "Invalid index for insert_subreg");
143 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
145 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
146 "Insert superreg source must be in a physical register");
147 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
148 "Inserted value must be in a physical register");
150 DOUT << "subreg: CONVERTING: " << *MI;
152 // Insert sub-register copy
153 const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg);
154 const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
155 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
158 MachineBasicBlock::iterator dMI = MI;
159 DOUT << "subreg: " << *(--dMI);
167 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
170 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
171 DOUT << "Machine Function\n";
173 bool MadeChange = false;
175 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
176 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
178 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
179 mbbi != mbbe; ++mbbi) {
180 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
182 MachineInstr *MI = mi++;
184 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
185 MadeChange |= LowerExtract(MI);
186 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
187 MadeChange |= LowerInsert(MI);
188 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
189 MadeChange |= LowerSubregToReg(MI);