1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
32 struct LowerSubregsInstructionPass : public MachineFunctionPass {
34 const TargetRegisterInfo *TRI;
35 const TargetInstrInfo *TII;
38 static char ID; // Pass identification, replacement for typeid
39 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
41 const char *getPassName() const {
42 return "Subregister lowering instruction pass";
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addPreservedID(MachineLoopInfoID);
48 AU.addPreservedID(MachineDominatorsID);
49 MachineFunctionPass::getAnalysisUsage(AU);
52 /// runOnMachineFunction - pass entry point
53 bool runOnMachineFunction(MachineFunction&);
56 bool LowerExtract(MachineInstr *MI);
57 bool LowerInsert(MachineInstr *MI);
58 bool LowerSubregToReg(MachineInstr *MI);
60 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
61 const TargetRegisterInfo *TRI);
62 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
63 const TargetRegisterInfo *TRI,
64 bool AddIfNotFound = false);
67 char LowerSubregsInstructionPass::ID = 0;
70 FunctionPass *llvm::createLowerSubregsPass() {
71 return new LowerSubregsInstructionPass();
74 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
75 /// and the lowered replacement instructions immediately precede it.
76 /// Mark the replacement instructions with the dead flag.
78 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
80 const TargetRegisterInfo *TRI) {
81 for (MachineBasicBlock::iterator MII =
82 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
83 if (MII->addRegisterDead(DstReg, TRI))
85 assert(MII != MI->getParent()->begin() &&
86 "copyRegToReg output doesn't reference destination register!");
90 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
91 /// and the lowered replacement instructions immediately precede it.
92 /// Mark the replacement instructions with the kill flag.
94 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
96 const TargetRegisterInfo *TRI,
98 for (MachineBasicBlock::iterator MII =
99 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
100 if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
102 assert(MII != MI->getParent()->begin() &&
103 "copyRegToReg output doesn't reference source register!");
107 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
108 MachineBasicBlock *MBB = MI->getParent();
110 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
111 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
112 MI->getOperand(2).isImm() && "Malformed extract_subreg");
114 unsigned DstReg = MI->getOperand(0).getReg();
115 unsigned SuperReg = MI->getOperand(1).getReg();
116 unsigned SubIdx = MI->getOperand(2).getImm();
117 unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
119 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
120 "Extract supperg source must be a physical register");
121 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
122 "Extract destination must be in a physical register");
123 assert(SrcReg && "invalid subregister index for register");
125 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
127 if (SrcReg == DstReg) {
128 // No need to insert an identity copy instruction.
129 if (MI->getOperand(1).isKill()) {
130 // We must make sure the super-register gets killed. Replace the
131 // instruction with KILL.
132 MI->setDesc(TII->get(TargetInstrInfo::KILL));
133 MI->RemoveOperand(2); // SubIdx
134 DEBUG(dbgs() << "subreg: replace by: " << *MI);
138 DEBUG(dbgs() << "subreg: eliminated!");
141 const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
142 const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
143 bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
145 assert(Emitted && "Subreg and Dst must be of compatible register class");
146 // Transfer the kill/dead flags, if needed.
147 if (MI->getOperand(0).isDead())
148 TransferDeadFlag(MI, DstReg, TRI);
149 if (MI->getOperand(1).isKill())
150 TransferKillFlag(MI, SuperReg, TRI, true);
152 MachineBasicBlock::iterator dMI = MI;
153 dbgs() << "subreg: " << *(--dMI);
157 DEBUG(dbgs() << '\n');
162 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
163 MachineBasicBlock *MBB = MI->getParent();
164 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
165 MI->getOperand(1).isImm() &&
166 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
167 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
169 unsigned DstReg = MI->getOperand(0).getReg();
170 unsigned InsReg = MI->getOperand(2).getReg();
171 unsigned InsSIdx = MI->getOperand(2).getSubReg();
172 unsigned SubIdx = MI->getOperand(3).getImm();
174 assert(SubIdx != 0 && "Invalid index for insert_subreg");
175 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
177 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
178 "Insert destination must be in a physical register");
179 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
180 "Inserted value must be in a physical register");
182 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
184 if (DstSubReg == InsReg && InsSIdx == 0) {
185 // No need to insert an identify copy instruction.
186 // Watch out for case like this:
188 // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
189 // The first def is defining RAX, not EAX so the top bits were not
191 DEBUG(dbgs() << "subreg: eliminated!");
193 // Insert sub-register copy
194 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
195 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
196 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
198 assert(Emitted && "Subreg and Dst must be of compatible register class");
199 // Transfer the kill/dead flags, if needed.
200 if (MI->getOperand(0).isDead())
201 TransferDeadFlag(MI, DstSubReg, TRI);
202 if (MI->getOperand(2).isKill())
203 TransferKillFlag(MI, InsReg, TRI);
205 MachineBasicBlock::iterator dMI = MI;
206 dbgs() << "subreg: " << *(--dMI);
210 DEBUG(dbgs() << '\n');
215 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
216 MachineBasicBlock *MBB = MI->getParent();
217 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
218 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
219 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
220 MI->getOperand(3).isImm() && "Invalid insert_subreg");
222 unsigned DstReg = MI->getOperand(0).getReg();
224 unsigned SrcReg = MI->getOperand(1).getReg();
226 unsigned InsReg = MI->getOperand(2).getReg();
227 unsigned SubIdx = MI->getOperand(3).getImm();
229 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
230 assert(SubIdx != 0 && "Invalid index for insert_subreg");
231 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
232 assert(DstSubReg && "invalid subregister index for register");
233 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
234 "Insert superreg source must be in a physical register");
235 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
236 "Inserted value must be in a physical register");
238 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
240 if (DstSubReg == InsReg) {
241 // No need to insert an identity copy instruction. If the SrcReg was
242 // <undef>, we need to make sure it is alive by inserting a KILL
243 if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
244 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
245 TII->get(TargetInstrInfo::KILL), DstReg);
246 if (MI->getOperand(2).isUndef())
247 MIB.addReg(InsReg, RegState::Undef);
249 MIB.addReg(InsReg, RegState::Kill);
251 DEBUG(dbgs() << "subreg: eliminated!\n");
256 // Insert sub-register copy
257 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
258 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
259 if (MI->getOperand(2).isUndef())
260 // If the source register being inserted is undef, then this becomes a
262 BuildMI(*MBB, MI, MI->getDebugLoc(),
263 TII->get(TargetInstrInfo::KILL), DstSubReg);
265 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
267 assert(Emitted && "Subreg and Dst must be of compatible register class");
269 MachineBasicBlock::iterator CopyMI = MI;
272 // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
273 if (!MI->getOperand(1).isUndef())
274 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
276 // Transfer the kill/dead flags, if needed.
277 if (MI->getOperand(0).isDead()) {
278 TransferDeadFlag(MI, DstSubReg, TRI);
280 // Make sure the full DstReg is live after this replacement.
281 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
284 // Make sure the inserted register gets killed
285 if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
286 TransferKillFlag(MI, InsReg, TRI);
290 MachineBasicBlock::iterator dMI = MI;
291 dbgs() << "subreg: " << *(--dMI) << "\n";
298 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
301 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
302 DEBUG(dbgs() << "Machine Function\n"
303 << "********** LOWERING SUBREG INSTRS **********\n"
304 << "********** Function: "
305 << MF.getFunction()->getName() << '\n');
306 TRI = MF.getTarget().getRegisterInfo();
307 TII = MF.getTarget().getInstrInfo();
309 bool MadeChange = false;
311 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
312 mbbi != mbbe; ++mbbi) {
313 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
315 MachineBasicBlock::iterator nmi = llvm::next(mi);
316 MachineInstr *MI = mi;
317 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
318 MadeChange |= LowerExtract(MI);
319 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
320 MadeChange |= LowerInsert(MI);
321 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
322 MadeChange |= LowerSubregToReg(MI);