1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
32 struct LowerSubregsInstructionPass : public MachineFunctionPass {
34 const TargetRegisterInfo *TRI;
35 const TargetInstrInfo *TII;
38 static char ID; // Pass identification, replacement for typeid
39 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
41 const char *getPassName() const {
42 return "Subregister lowering instruction pass";
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addPreservedID(MachineLoopInfoID);
48 AU.addPreservedID(MachineDominatorsID);
49 MachineFunctionPass::getAnalysisUsage(AU);
52 /// runOnMachineFunction - pass entry point
53 bool runOnMachineFunction(MachineFunction&);
56 bool LowerExtract(MachineInstr *MI);
57 bool LowerInsert(MachineInstr *MI);
58 bool LowerSubregToReg(MachineInstr *MI);
60 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
61 const TargetRegisterInfo *TRI);
62 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
63 const TargetRegisterInfo *TRI,
64 bool AddIfNotFound = false);
65 void TransferImplicitDefs(MachineInstr *MI);
68 char LowerSubregsInstructionPass::ID = 0;
71 FunctionPass *llvm::createLowerSubregsPass() {
72 return new LowerSubregsInstructionPass();
75 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
76 /// and the lowered replacement instructions immediately precede it.
77 /// Mark the replacement instructions with the dead flag.
79 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
81 const TargetRegisterInfo *TRI) {
82 for (MachineBasicBlock::iterator MII =
83 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
84 if (MII->addRegisterDead(DstReg, TRI))
86 assert(MII != MI->getParent()->begin() &&
87 "copyRegToReg output doesn't reference destination register!");
91 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
92 /// and the lowered replacement instructions immediately precede it.
93 /// Mark the replacement instructions with the kill flag.
95 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
97 const TargetRegisterInfo *TRI,
99 for (MachineBasicBlock::iterator MII =
100 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
101 if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
103 assert(MII != MI->getParent()->begin() &&
104 "copyRegToReg output doesn't reference source register!");
108 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
109 /// replacement instructions immediately precede it. Copy any implicit-def
110 /// operands from MI to the replacement instruction.
112 LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
113 MachineBasicBlock::iterator CopyMI = MI;
116 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
117 MachineOperand &MO = MI->getOperand(i);
118 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
120 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
124 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
125 MachineBasicBlock *MBB = MI->getParent();
127 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
128 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
129 MI->getOperand(2).isImm() && "Malformed extract_subreg");
131 unsigned DstReg = MI->getOperand(0).getReg();
132 unsigned SuperReg = MI->getOperand(1).getReg();
133 unsigned SubIdx = MI->getOperand(2).getImm();
134 unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
136 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
137 "Extract supperg source must be a physical register");
138 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
139 "Extract destination must be in a physical register");
140 assert(SrcReg && "invalid subregister index for register");
142 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
144 if (SrcReg == DstReg) {
145 // No need to insert an identity copy instruction.
146 if (MI->getOperand(1).isKill()) {
147 // We must make sure the super-register gets killed. Replace the
148 // instruction with KILL.
149 MI->setDesc(TII->get(TargetOpcode::KILL));
150 MI->RemoveOperand(2); // SubIdx
151 DEBUG(dbgs() << "subreg: replace by: " << *MI);
155 DEBUG(dbgs() << "subreg: eliminated!");
158 const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
159 const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
160 bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS,
163 assert(Emitted && "Subreg and Dst must be of compatible register class");
164 // Transfer the kill/dead flags, if needed.
165 if (MI->getOperand(0).isDead())
166 TransferDeadFlag(MI, DstReg, TRI);
167 if (MI->getOperand(1).isKill())
168 TransferKillFlag(MI, SuperReg, TRI, true);
169 TransferImplicitDefs(MI);
171 MachineBasicBlock::iterator dMI = MI;
172 dbgs() << "subreg: " << *(--dMI);
176 DEBUG(dbgs() << '\n');
181 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
182 MachineBasicBlock *MBB = MI->getParent();
183 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
184 MI->getOperand(1).isImm() &&
185 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
186 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
188 unsigned DstReg = MI->getOperand(0).getReg();
189 unsigned InsReg = MI->getOperand(2).getReg();
190 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
191 unsigned SubIdx = MI->getOperand(3).getImm();
193 assert(SubIdx != 0 && "Invalid index for insert_subreg");
194 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
196 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
197 "Insert destination must be in a physical register");
198 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
199 "Inserted value must be in a physical register");
201 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
203 if (DstSubReg == InsReg) {
204 // No need to insert an identify copy instruction.
205 // Watch out for case like this:
206 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
207 // We must leave %RAX live.
208 if (DstReg != InsReg) {
209 MI->setDesc(TII->get(TargetOpcode::KILL));
210 MI->RemoveOperand(3); // SubIdx
211 MI->RemoveOperand(1); // Imm
212 DEBUG(dbgs() << "subreg: replace by: " << *MI);
215 DEBUG(dbgs() << "subreg: eliminated!");
217 // Insert sub-register copy
218 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
219 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
220 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
223 assert(Emitted && "Subreg and Dst must be of compatible register class");
224 // Transfer the kill/dead flags, if needed.
225 if (MI->getOperand(0).isDead())
226 TransferDeadFlag(MI, DstSubReg, TRI);
227 if (MI->getOperand(2).isKill())
228 TransferKillFlag(MI, InsReg, TRI);
230 MachineBasicBlock::iterator dMI = MI;
231 dbgs() << "subreg: " << *(--dMI);
235 DEBUG(dbgs() << '\n');
240 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
241 MachineBasicBlock *MBB = MI->getParent();
242 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
243 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
244 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
245 MI->getOperand(3).isImm() && "Invalid insert_subreg");
247 unsigned DstReg = MI->getOperand(0).getReg();
249 unsigned SrcReg = MI->getOperand(1).getReg();
251 unsigned InsReg = MI->getOperand(2).getReg();
252 unsigned SubIdx = MI->getOperand(3).getImm();
254 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
255 assert(SubIdx != 0 && "Invalid index for insert_subreg");
256 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
257 assert(DstSubReg && "invalid subregister index for register");
258 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
259 "Insert superreg source must be in a physical register");
260 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
261 "Inserted value must be in a physical register");
263 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
265 if (DstSubReg == InsReg) {
266 // No need to insert an identity copy instruction. If the SrcReg was
267 // <undef>, we need to make sure it is alive by inserting a KILL
268 if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
269 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
270 TII->get(TargetOpcode::KILL), DstReg);
271 if (MI->getOperand(2).isUndef())
272 MIB.addReg(InsReg, RegState::Undef);
274 MIB.addReg(InsReg, RegState::Kill);
276 DEBUG(dbgs() << "subreg: eliminated!\n");
281 // Insert sub-register copy
282 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
283 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
284 if (MI->getOperand(2).isUndef())
285 // If the source register being inserted is undef, then this becomes a
287 BuildMI(*MBB, MI, MI->getDebugLoc(),
288 TII->get(TargetOpcode::KILL), DstSubReg);
290 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
293 assert(Emitted && "Subreg and Dst must be of compatible register class");
295 MachineBasicBlock::iterator CopyMI = MI;
298 // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
299 if (!MI->getOperand(1).isUndef())
300 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
302 // Transfer the kill/dead flags, if needed.
303 if (MI->getOperand(0).isDead()) {
304 TransferDeadFlag(MI, DstSubReg, TRI);
306 // Make sure the full DstReg is live after this replacement.
307 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
310 // Make sure the inserted register gets killed
311 if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
312 TransferKillFlag(MI, InsReg, TRI);
316 MachineBasicBlock::iterator dMI = MI;
317 dbgs() << "subreg: " << *(--dMI) << "\n";
324 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
327 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
328 DEBUG(dbgs() << "Machine Function\n"
329 << "********** LOWERING SUBREG INSTRS **********\n"
330 << "********** Function: "
331 << MF.getFunction()->getName() << '\n');
332 TRI = MF.getTarget().getRegisterInfo();
333 TII = MF.getTarget().getInstrInfo();
335 bool MadeChange = false;
337 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
338 mbbi != mbbe; ++mbbi) {
339 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
341 MachineBasicBlock::iterator nmi = llvm::next(mi);
342 MachineInstr *MI = mi;
343 if (MI->isExtractSubreg()) {
344 MadeChange |= LowerExtract(MI);
345 } else if (MI->isInsertSubreg()) {
346 MadeChange |= LowerInsert(MI);
347 } else if (MI->isSubregToReg()) {
348 MadeChange |= LowerSubregToReg(MI);