1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 /// runOnMachineFunction - pass entry point
34 bool runOnMachineFunction(MachineFunction&);
36 bool LowerExtract(MachineInstr *MI);
37 bool LowerInsert(MachineInstr *MI);
40 char LowerSubregsInstructionPass::ID = 0;
43 FunctionPass *llvm::createLowerSubregsPass() {
44 return new LowerSubregsInstructionPass();
47 // Returns the Register Class of a physical register.
48 static const TargetRegisterClass *getPhysicalRegisterRegClass(
49 const MRegisterInfo &MRI,
51 assert(MRegisterInfo::isPhysicalRegister(reg) &&
52 "reg must be a physical register");
53 // Pick the register class of the right type that contains this physreg.
54 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
55 E = MRI.regclass_end(); I != E; ++I)
56 if ((*I)->contains(reg))
58 assert(false && "Couldn't find the register class");
62 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
63 MachineBasicBlock *MBB = MI->getParent();
64 MachineFunction &MF = *MBB->getParent();
65 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
66 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
68 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
69 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
70 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
72 unsigned SuperReg = MI->getOperand(1).getReg();
73 unsigned SubIdx = MI->getOperand(2).getImm();
75 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
76 "Extract supperg source must be a physical register");
77 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
78 unsigned DstReg = MI->getOperand(0).getReg();
80 DOUT << "subreg: CONVERTING: " << *MI;
82 if (SrcReg != DstReg) {
83 const TargetRegisterClass *TRC = 0;
84 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
85 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
87 TRC = MF.getRegInfo().getRegClass(DstReg);
89 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
90 "Extract subreg and Dst must be of same register class");
92 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
93 MachineBasicBlock::iterator dMI = MI;
94 DOUT << "subreg: " << *(--dMI);
103 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
104 MachineBasicBlock *MBB = MI->getParent();
105 MachineFunction &MF = *MBB->getParent();
106 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
107 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
113 // If only have 3 operands, then the source superreg is undef
114 // and we can supress the copy from the undef value
115 if (MI->getNumOperands() == 3) {
116 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
117 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
118 MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
119 DstReg = MI->getOperand(0).getReg();
121 InsReg = MI->getOperand(1).getReg();
122 SubIdx = MI->getOperand(2).getImm();
123 } else if (MI->getNumOperands() == 4) {
124 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
125 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
126 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
127 MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
128 DstReg = MI->getOperand(0).getReg();
129 SrcReg = MI->getOperand(1).getReg();
130 InsReg = MI->getOperand(2).getReg();
131 SubIdx = MI->getOperand(3).getImm();
133 assert(0 && "Malformed extract_subreg");
135 assert(SubIdx != 0 && "Invalid index for extract_subreg");
136 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
138 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
139 "Insert superreg source must be in a physical register");
140 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
141 "Insert destination must be in a physical register");
142 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
143 "Inserted value must be in a physical register");
145 DOUT << "subreg: CONVERTING: " << *MI;
147 // If the inserted register is already allocated into a subregister
148 // of the destination, we copy the subreg into the source
149 // However, this is only safe if the insert instruction is the kill
150 // of the source register
151 bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg);
152 if (revCopyOrder && InsReg != DstSubReg) {
153 if (MI->getOperand(1).isKill()) {
154 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
155 // Insert sub-register copy
156 const TargetRegisterClass *TRC1 = 0;
157 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
158 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
160 TRC1 = MF.getRegInfo().getRegClass(InsReg);
162 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
165 MachineBasicBlock::iterator dMI = MI;
166 DOUT << "subreg: " << *(--dMI);
169 assert(0 && "Don't know how to convert this insert");
173 if (InsReg == DstSubReg) {
174 DOUT << "subreg: Eliminated subreg copy\n";
178 if (SrcReg != DstReg) {
179 // Insert super-register copy
180 const TargetRegisterClass *TRC0 = 0;
181 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
182 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
184 TRC0 = MF.getRegInfo().getRegClass(DstReg);
186 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
187 "Insert superreg and Dst must be of same register class");
189 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
192 MachineBasicBlock::iterator dMI = MI;
193 DOUT << "subreg: " << *(--dMI);
198 if (SrcReg == DstReg) {
199 DOUT << "subreg: Eliminated superreg copy\n";
203 if (!revCopyOrder && InsReg != DstSubReg) {
204 // Insert sub-register copy
205 const TargetRegisterClass *TRC1 = 0;
206 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
207 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
209 TRC1 = MF.getRegInfo().getRegClass(InsReg);
211 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
214 MachineBasicBlock::iterator dMI = MI;
215 DOUT << "subreg: " << *(--dMI);
224 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
227 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
228 DOUT << "Machine Function\n";
230 bool MadeChange = false;
232 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
233 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
235 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
236 mbbi != mbbe; ++mbbi) {
237 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
239 MachineInstr *MI = mi++;
241 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
242 MadeChange |= LowerExtract(MI);
243 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
244 MadeChange |= LowerInsert(MI);