1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
31 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
32 : public MachineFunctionPass {
33 static char ID; // Pass identification, replacement for typeid
34 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
36 const char *getPassName() const {
37 return "Subregister lowering instruction pass";
40 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
41 AU.addPreservedID(MachineLoopInfoID);
42 AU.addPreservedID(MachineDominatorsID);
43 MachineFunctionPass::getAnalysisUsage(AU);
46 /// runOnMachineFunction - pass entry point
47 bool runOnMachineFunction(MachineFunction&);
49 bool LowerExtract(MachineInstr *MI);
50 bool LowerInsert(MachineInstr *MI);
51 bool LowerSubregToReg(MachineInstr *MI);
54 char LowerSubregsInstructionPass::ID = 0;
57 FunctionPass *llvm::createLowerSubregsPass() {
58 return new LowerSubregsInstructionPass();
61 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
62 MachineBasicBlock *MBB = MI->getParent();
63 MachineFunction &MF = *MBB->getParent();
64 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
65 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
67 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
68 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
69 MI->getOperand(2).isImm() && "Malformed extract_subreg");
71 unsigned DstReg = MI->getOperand(0).getReg();
72 unsigned SuperReg = MI->getOperand(1).getReg();
73 unsigned SubIdx = MI->getOperand(2).getImm();
74 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
76 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
77 "Extract supperg source must be a physical register");
78 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
79 "Insert destination must be in a physical register");
81 DOUT << "subreg: CONVERTING: " << *MI;
83 if (SrcReg != DstReg) {
84 const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
85 assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
86 "Extract subreg and Dst must be of same register class");
87 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
90 MachineBasicBlock::iterator dMI = MI;
91 DOUT << "subreg: " << *(--dMI);
100 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
101 MachineBasicBlock *MBB = MI->getParent();
102 MachineFunction &MF = *MBB->getParent();
103 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
104 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
105 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
106 MI->getOperand(1).isImm() &&
107 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
108 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
110 unsigned DstReg = MI->getOperand(0).getReg();
111 unsigned InsReg = MI->getOperand(2).getReg();
112 unsigned SubIdx = MI->getOperand(3).getImm();
114 assert(SubIdx != 0 && "Invalid index for insert_subreg");
115 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
117 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
118 "Insert destination must be in a physical register");
119 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
120 "Inserted value must be in a physical register");
122 DOUT << "subreg: CONVERTING: " << *MI;
124 if (DstSubReg == InsReg) {
125 // No need to insert an identify copy instruction.
126 DOUT << "subreg: eliminated!";
128 // Insert sub-register copy
129 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
130 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
131 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
134 MachineBasicBlock::iterator dMI = MI;
135 DOUT << "subreg: " << *(--dMI);
144 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
145 MachineBasicBlock *MBB = MI->getParent();
146 MachineFunction &MF = *MBB->getParent();
147 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
148 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
149 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
150 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
151 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
152 MI->getOperand(3).isImm() && "Invalid insert_subreg");
154 unsigned DstReg = MI->getOperand(0).getReg();
155 unsigned SrcReg = MI->getOperand(1).getReg();
156 unsigned InsReg = MI->getOperand(2).getReg();
157 unsigned SubIdx = MI->getOperand(3).getImm();
159 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
160 assert(SubIdx != 0 && "Invalid index for insert_subreg");
161 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
163 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
164 "Insert superreg source must be in a physical register");
165 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
166 "Inserted value must be in a physical register");
168 DOUT << "subreg: CONVERTING: " << *MI;
170 if (DstSubReg == InsReg) {
171 // No need to insert an identify copy instruction.
172 DOUT << "subreg: eliminated!";
174 // Insert sub-register copy
175 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
176 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
177 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
179 MachineBasicBlock::iterator dMI = MI;
180 DOUT << "subreg: " << *(--dMI);
189 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
192 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
193 DOUT << "Machine Function\n";
195 bool MadeChange = false;
197 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
198 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
200 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
201 mbbi != mbbe; ++mbbi) {
202 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
204 MachineInstr *MI = mi++;
206 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
207 MadeChange |= LowerExtract(MI);
208 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
209 MadeChange |= LowerInsert(MI);
210 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
211 MadeChange |= LowerSubregToReg(MI);