1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/raw_ostream.h"
32 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
33 : public MachineFunctionPass {
34 static char ID; // Pass identification, replacement for typeid
35 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
37 const char *getPassName() const {
38 return "Subregister lowering instruction pass";
41 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
43 AU.addPreservedID(MachineLoopInfoID);
44 AU.addPreservedID(MachineDominatorsID);
45 MachineFunctionPass::getAnalysisUsage(AU);
48 /// runOnMachineFunction - pass entry point
49 bool runOnMachineFunction(MachineFunction&);
51 bool LowerExtract(MachineInstr *MI);
52 bool LowerInsert(MachineInstr *MI);
53 bool LowerSubregToReg(MachineInstr *MI);
55 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
56 const TargetRegisterInfo &TRI);
57 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
58 const TargetRegisterInfo &TRI);
61 char LowerSubregsInstructionPass::ID = 0;
64 FunctionPass *llvm::createLowerSubregsPass() {
65 return new LowerSubregsInstructionPass();
68 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
69 /// and the lowered replacement instructions immediately precede it.
70 /// Mark the replacement instructions with the dead flag.
72 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
74 const TargetRegisterInfo &TRI) {
75 for (MachineBasicBlock::iterator MII =
76 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
77 if (MII->addRegisterDead(DstReg, &TRI))
79 assert(MII != MI->getParent()->begin() &&
80 "copyRegToReg output doesn't reference destination register!");
84 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
85 /// and the lowered replacement instructions immediately precede it.
86 /// Mark the replacement instructions with the kill flag.
88 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
90 const TargetRegisterInfo &TRI) {
91 for (MachineBasicBlock::iterator MII =
92 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
93 if (MII->addRegisterKilled(SrcReg, &TRI))
95 assert(MII != MI->getParent()->begin() &&
96 "copyRegToReg output doesn't reference source register!");
100 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
101 MachineBasicBlock *MBB = MI->getParent();
102 MachineFunction &MF = *MBB->getParent();
103 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
104 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
106 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
107 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
108 MI->getOperand(2).isImm() && "Malformed extract_subreg");
110 unsigned DstReg = MI->getOperand(0).getReg();
111 unsigned SuperReg = MI->getOperand(1).getReg();
112 unsigned SubIdx = MI->getOperand(2).getImm();
113 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
115 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
116 "Extract supperg source must be a physical register");
117 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
118 "Extract destination must be in a physical register");
120 DOUT << "subreg: CONVERTING: " << *MI;
122 if (SrcReg == DstReg) {
123 // No need to insert an identify copy instruction.
124 DOUT << "subreg: eliminated!";
125 // Find the kill of the destination register's live range, and insert
126 // a kill of the source register at that point.
127 if (MI->getOperand(1).isKill() && !MI->getOperand(0).isDead())
128 for (MachineBasicBlock::iterator MII =
129 next(MachineBasicBlock::iterator(MI));
130 MII != MBB->end(); ++MII)
131 if (MII->killsRegister(DstReg, &TRI)) {
132 MII->addRegisterKilled(SuperReg, &TRI, /*AddIfNotFound=*/true);
137 const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
138 const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
139 bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
141 assert(Emitted && "Subreg and Dst must be of compatible register class");
142 // Transfer the kill/dead flags, if needed.
143 if (MI->getOperand(0).isDead())
144 TransferDeadFlag(MI, DstReg, TRI);
145 if (MI->getOperand(1).isKill())
146 TransferKillFlag(MI, SrcReg, TRI);
149 MachineBasicBlock::iterator dMI = MI;
150 DOUT << "subreg: " << *(--dMI);
159 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
160 MachineBasicBlock *MBB = MI->getParent();
161 MachineFunction &MF = *MBB->getParent();
162 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
163 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
164 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
165 MI->getOperand(1).isImm() &&
166 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
167 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
169 unsigned DstReg = MI->getOperand(0).getReg();
170 unsigned InsReg = MI->getOperand(2).getReg();
171 unsigned InsSIdx = MI->getOperand(2).getSubReg();
172 unsigned SubIdx = MI->getOperand(3).getImm();
174 assert(SubIdx != 0 && "Invalid index for insert_subreg");
175 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
177 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
178 "Insert destination must be in a physical register");
179 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
180 "Inserted value must be in a physical register");
182 DOUT << "subreg: CONVERTING: " << *MI;
184 if (DstSubReg == InsReg && InsSIdx == 0) {
185 // No need to insert an identify copy instruction.
186 // Watch out for case like this:
188 // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
189 // The first def is defining RAX, not EAX so the top bits were not
191 DOUT << "subreg: eliminated!";
193 // Insert sub-register copy
194 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
195 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
196 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
197 // Transfer the kill/dead flags, if needed.
198 if (MI->getOperand(0).isDead())
199 TransferDeadFlag(MI, DstSubReg, TRI);
200 if (MI->getOperand(2).isKill())
201 TransferKillFlag(MI, InsReg, TRI);
204 MachineBasicBlock::iterator dMI = MI;
205 DOUT << "subreg: " << *(--dMI);
214 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
215 MachineBasicBlock *MBB = MI->getParent();
216 MachineFunction &MF = *MBB->getParent();
217 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
218 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
219 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
220 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
221 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
222 MI->getOperand(3).isImm() && "Invalid insert_subreg");
224 unsigned DstReg = MI->getOperand(0).getReg();
226 unsigned SrcReg = MI->getOperand(1).getReg();
228 unsigned InsReg = MI->getOperand(2).getReg();
229 unsigned SubIdx = MI->getOperand(3).getImm();
231 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
232 assert(SubIdx != 0 && "Invalid index for insert_subreg");
233 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
235 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
236 "Insert superreg source must be in a physical register");
237 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
238 "Inserted value must be in a physical register");
240 DOUT << "subreg: CONVERTING: " << *MI;
242 if (DstSubReg == InsReg) {
243 // No need to insert an identify copy instruction.
244 DOUT << "subreg: eliminated!";
246 // Insert sub-register copy
247 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
248 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
249 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
250 // Transfer the kill/dead flags, if needed.
251 if (MI->getOperand(0).isDead())
252 TransferDeadFlag(MI, DstSubReg, TRI);
253 if (MI->getOperand(1).isKill())
254 TransferKillFlag(MI, InsReg, TRI);
257 MachineBasicBlock::iterator dMI = MI;
258 DOUT << "subreg: " << *(--dMI);
267 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
270 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
271 DOUT << "Machine Function\n";
273 bool MadeChange = false;
275 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
276 DEBUG(errs() << "********** Function: "
277 << MF.getFunction()->getName() << '\n');
279 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
280 mbbi != mbbe; ++mbbi) {
281 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
283 MachineInstr *MI = mi++;
285 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
286 MadeChange |= LowerExtract(MI);
287 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
288 MadeChange |= LowerInsert(MI);
289 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
290 MadeChange |= LowerSubregToReg(MI);