1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 /// runOnMachineFunction - pass entry point
34 bool runOnMachineFunction(MachineFunction&);
36 bool LowerExtract(MachineInstr *MI);
37 bool LowerInsert(MachineInstr *MI);
40 char LowerSubregsInstructionPass::ID = 0;
43 FunctionPass *llvm::createLowerSubregsPass() {
44 return new LowerSubregsInstructionPass();
47 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
48 MachineBasicBlock *MBB = MI->getParent();
49 MachineFunction &MF = *MBB->getParent();
50 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
51 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
53 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
54 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
55 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
57 unsigned SuperReg = MI->getOperand(1).getReg();
58 unsigned SubIdx = MI->getOperand(2).getImm();
60 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
61 "Extract supperg source must be a physical register");
62 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
63 unsigned DstReg = MI->getOperand(0).getReg();
65 DOUT << "subreg: CONVERTING: " << *MI;
67 if (SrcReg != DstReg) {
68 const TargetRegisterClass *TRC = 0;
69 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
70 TRC = TRI.getPhysicalRegisterRegClass(DstReg);
72 TRC = MF.getRegInfo().getRegClass(DstReg);
74 assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
75 "Extract subreg and Dst must be of same register class");
77 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
78 MachineBasicBlock::iterator dMI = MI;
79 DOUT << "subreg: " << *(--dMI);
88 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
89 MachineBasicBlock *MBB = MI->getParent();
90 MachineFunction &MF = *MBB->getParent();
91 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
92 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
93 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
94 ((MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) ||
95 MI->getOperand(1).isImmediate()) &&
96 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
97 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
99 // Check if we're inserting into an implicit undef value.
100 bool isImplicit = MI->getOperand(1).isImmediate();
101 unsigned DstReg = MI->getOperand(0).getReg();
102 unsigned SrcReg = isImplicit ? DstReg : MI->getOperand(1).getReg();
103 unsigned InsReg = MI->getOperand(2).getReg();
104 unsigned SubIdx = MI->getOperand(3).getImm();
106 assert(SubIdx != 0 && "Invalid index for extract_subreg");
107 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
109 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
110 "Insert superreg source must be in a physical register");
111 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
112 "Insert destination must be in a physical register");
113 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
114 "Inserted value must be in a physical register");
116 DOUT << "subreg: CONVERTING: " << *MI;
118 // Check whether the implict subreg copy has side affects or not. Only copies
119 // into an undef value have no side affects, that is they can be eliminated
120 // without changing the semantics of the program.
121 bool copyHasSideAffects = isImplicit?
122 MI->getOperand(1).getImm() != TargetInstrInfo::IMPL_VAL_UNDEF
125 // If the inserted register is already allocated into a subregister
126 // of the destination, we copy the subreg into the source
127 // However, this is only safe if the insert instruction is the kill
128 // of the source register
129 bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
130 if (revCopyOrder && (InsReg != DstSubReg || copyHasSideAffects)) {
131 if (isImplicit || MI->getOperand(1).isKill()) {
132 DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
133 // Insert sub-register copy
134 const TargetRegisterClass *TRC1 = 0;
135 if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
136 TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
138 TRC1 = MF.getRegInfo().getRegClass(InsReg);
140 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
143 MachineBasicBlock::iterator dMI = MI;
144 DOUT << "subreg: " << *(--dMI);
147 assert(0 && "Don't know how to convert this insert");
151 if (InsReg == DstSubReg && !copyHasSideAffects) {
152 DOUT << "subreg: Eliminated subreg copy\n";
156 if (SrcReg != DstReg) {
157 // Insert super-register copy
158 const TargetRegisterClass *TRC0 = 0;
159 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
160 TRC0 = TRI.getPhysicalRegisterRegClass(DstReg);
162 TRC0 = MF.getRegInfo().getRegClass(DstReg);
164 assert(TRC0 == TRI.getPhysicalRegisterRegClass(SrcReg) &&
165 "Insert superreg and Dst must be of same register class");
167 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
170 MachineBasicBlock::iterator dMI = MI;
171 DOUT << "subreg: " << *(--dMI);
176 if (SrcReg == DstReg) {
177 DOUT << "subreg: Eliminated superreg copy\n";
181 if (!revCopyOrder && (InsReg != DstSubReg || copyHasSideAffects)) {
182 // Insert sub-register copy
183 const TargetRegisterClass *TRC1 = 0;
184 if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
185 TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
187 TRC1 = MF.getRegInfo().getRegClass(InsReg);
189 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
192 MachineBasicBlock::iterator dMI = MI;
193 DOUT << "subreg: " << *(--dMI);
202 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
205 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
206 DOUT << "Machine Function\n";
208 bool MadeChange = false;
210 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
211 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
213 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
214 mbbi != mbbe; ++mbbi) {
215 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
217 MachineInstr *MI = mi++;
219 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
220 MadeChange |= LowerExtract(MI);
221 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
222 MadeChange |= LowerInsert(MI);