1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
31 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
32 : public MachineFunctionPass {
33 static char ID; // Pass identification, replacement for typeid
34 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
36 const char *getPassName() const {
37 return "Subregister lowering instruction pass";
40 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
41 AU.addPreservedID(MachineLoopInfoID);
42 AU.addPreservedID(MachineDominatorsID);
43 MachineFunctionPass::getAnalysisUsage(AU);
46 /// runOnMachineFunction - pass entry point
47 bool runOnMachineFunction(MachineFunction&);
49 bool LowerExtract(MachineInstr *MI);
50 bool LowerInsert(MachineInstr *MI);
51 bool LowerSubregToReg(MachineInstr *MI);
53 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
54 const TargetRegisterInfo &TRI);
55 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
56 const TargetRegisterInfo &TRI);
59 char LowerSubregsInstructionPass::ID = 0;
62 FunctionPass *llvm::createLowerSubregsPass() {
63 return new LowerSubregsInstructionPass();
66 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
67 /// and the lowered replacement instructions immediately precede it.
68 /// Mark the replacement instructions with the dead flag.
70 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
72 const TargetRegisterInfo &TRI) {
73 for (MachineBasicBlock::iterator MII =
74 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
75 if (MII->addRegisterDead(DstReg, &TRI))
77 assert(MII != MI->getParent()->begin() &&
78 "copyRegToReg output doesn't reference destination register!");
82 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
83 /// and the lowered replacement instructions immediately precede it.
84 /// Mark the replacement instructions with the kill flag.
86 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
88 const TargetRegisterInfo &TRI) {
89 for (MachineBasicBlock::iterator MII =
90 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
91 if (MII->addRegisterKilled(SrcReg, &TRI))
93 assert(MII != MI->getParent()->begin() &&
94 "copyRegToReg output doesn't reference source register!");
98 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
99 MachineBasicBlock *MBB = MI->getParent();
100 MachineFunction &MF = *MBB->getParent();
101 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
102 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
104 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
105 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
106 MI->getOperand(2).isImm() && "Malformed extract_subreg");
108 unsigned DstReg = MI->getOperand(0).getReg();
109 unsigned SuperReg = MI->getOperand(1).getReg();
110 unsigned SubIdx = MI->getOperand(2).getImm();
111 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
113 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
114 "Extract supperg source must be a physical register");
115 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
116 "Extract destination must be in a physical register");
118 DOUT << "subreg: CONVERTING: " << *MI;
120 if (SrcReg == DstReg) {
121 // No need to insert an identify copy instruction.
122 DOUT << "subreg: eliminated!";
123 // Find the kill of the destination register's live range, and insert
124 // a kill of the source register at that point.
125 if (MI->getOperand(1).isKill() && !MI->getOperand(0).isDead())
126 for (MachineBasicBlock::iterator MII =
127 next(MachineBasicBlock::iterator(MI));
128 MII != MBB->end(); ++MII)
129 if (MII->killsRegister(DstReg, &TRI)) {
130 MII->addRegisterKilled(SuperReg, &TRI, /*AddIfNotFound=*/true);
135 const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
136 assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
137 "Extract subreg and Dst must be of same register class");
138 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
139 // Transfer the kill/dead flags, if needed.
140 if (MI->getOperand(0).isDead())
141 TransferDeadFlag(MI, DstReg, TRI);
142 if (MI->getOperand(1).isKill())
143 TransferKillFlag(MI, SrcReg, TRI);
146 MachineBasicBlock::iterator dMI = MI;
147 DOUT << "subreg: " << *(--dMI);
156 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
157 MachineBasicBlock *MBB = MI->getParent();
158 MachineFunction &MF = *MBB->getParent();
159 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
160 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
161 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
162 MI->getOperand(1).isImm() &&
163 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
164 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
166 unsigned DstReg = MI->getOperand(0).getReg();
167 unsigned InsReg = MI->getOperand(2).getReg();
168 unsigned SubIdx = MI->getOperand(3).getImm();
170 assert(SubIdx != 0 && "Invalid index for insert_subreg");
171 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
173 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
174 "Insert destination must be in a physical register");
175 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
176 "Inserted value must be in a physical register");
178 DOUT << "subreg: CONVERTING: " << *MI;
180 if (DstSubReg == InsReg) {
181 // No need to insert an identify copy instruction.
182 DOUT << "subreg: eliminated!";
184 // Insert sub-register copy
185 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
186 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
187 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
188 // Transfer the kill/dead flags, if needed.
189 if (MI->getOperand(0).isDead())
190 TransferDeadFlag(MI, DstSubReg, TRI);
191 if (MI->getOperand(2).isKill())
192 TransferKillFlag(MI, InsReg, TRI);
195 MachineBasicBlock::iterator dMI = MI;
196 DOUT << "subreg: " << *(--dMI);
205 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
206 MachineBasicBlock *MBB = MI->getParent();
207 MachineFunction &MF = *MBB->getParent();
208 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
209 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
210 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
211 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
212 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
213 MI->getOperand(3).isImm() && "Invalid insert_subreg");
215 unsigned DstReg = MI->getOperand(0).getReg();
217 unsigned SrcReg = MI->getOperand(1).getReg();
219 unsigned InsReg = MI->getOperand(2).getReg();
220 unsigned SubIdx = MI->getOperand(3).getImm();
222 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
223 assert(SubIdx != 0 && "Invalid index for insert_subreg");
224 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
226 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
227 "Insert superreg source must be in a physical register");
228 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
229 "Inserted value must be in a physical register");
231 DOUT << "subreg: CONVERTING: " << *MI;
233 if (DstSubReg == InsReg) {
234 // No need to insert an identify copy instruction.
235 DOUT << "subreg: eliminated!";
237 // Insert sub-register copy
238 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
239 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
240 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
241 // Transfer the kill/dead flags, if needed.
242 if (MI->getOperand(0).isDead())
243 TransferDeadFlag(MI, DstSubReg, TRI);
244 if (MI->getOperand(1).isKill())
245 TransferKillFlag(MI, InsReg, TRI);
248 MachineBasicBlock::iterator dMI = MI;
249 DOUT << "subreg: " << *(--dMI);
258 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
261 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
262 DOUT << "Machine Function\n";
264 bool MadeChange = false;
266 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
267 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
269 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
270 mbbi != mbbe; ++mbbi) {
271 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
273 MachineInstr *MI = mi++;
275 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
276 MadeChange |= LowerExtract(MI);
277 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
278 MadeChange |= LowerInsert(MI);
279 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
280 MadeChange |= LowerSubregToReg(MI);