1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Christopher Lamb and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/SSARegMap.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 /// runOnMachineFunction - pass entry point
34 bool runOnMachineFunction(MachineFunction&);
36 bool LowerExtract(MachineInstr *MI);
37 bool LowerInsert(MachineInstr *MI);
40 char LowerSubregsInstructionPass::ID = 0;
43 FunctionPass *llvm::createLowerSubregsPass() {
44 return new LowerSubregsInstructionPass();
47 // Returns the Register Class of a physical register.
48 static const TargetRegisterClass *getPhysicalRegisterRegClass(
49 const MRegisterInfo &MRI,
51 assert(MRegisterInfo::isPhysicalRegister(reg) &&
52 "reg must be a physical register");
53 // Pick the register class of the right type that contains this physreg.
54 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
55 E = MRI.regclass_end(); I != E; ++I)
56 if ((*I)->contains(reg))
58 assert(false && "Couldn't find the register class");
62 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
63 MachineBasicBlock *MBB = MI->getParent();
64 MachineFunction &MF = *MBB->getParent();
65 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
67 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
68 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
69 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
71 unsigned SuperReg = MI->getOperand(1).getReg();
72 unsigned SubIdx = MI->getOperand(2).getImm();
74 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
75 "Extract supperg source must be a physical register");
76 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
77 unsigned DstReg = MI->getOperand(0).getReg();
79 DOUT << "subreg: CONVERTING: " << *MI;
81 if (SrcReg != DstReg) {
82 const TargetRegisterClass *TRC = 0;
83 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
84 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
86 TRC = MF.getSSARegMap()->getRegClass(DstReg);
88 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
89 "Extract subreg and Dst must be of same register class");
91 MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
92 MachineBasicBlock::iterator dMI = MI;
93 DOUT << "subreg: " << *(--dMI);
102 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
103 MachineBasicBlock *MBB = MI->getParent();
104 MachineFunction &MF = *MBB->getParent();
105 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
111 // If only have 3 operands, then the source superreg is undef
112 // and we can supress the copy from the undef value
113 if (MI->getNumOperands() == 3) {
114 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
115 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
116 MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
117 DstReg = MI->getOperand(0).getReg();
119 InsReg = MI->getOperand(1).getReg();
120 SubIdx = MI->getOperand(2).getImm();
121 } else if (MI->getNumOperands() == 4) {
122 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
123 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
124 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
125 MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
126 DstReg = MI->getOperand(0).getReg();
127 SrcReg = MI->getOperand(1).getReg();
128 InsReg = MI->getOperand(2).getReg();
129 SubIdx = MI->getOperand(3).getImm();
131 assert(0 && "Malformed extract_subreg");
133 assert(SubIdx != 0 && "Invalid index for extract_subreg");
134 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
136 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
137 "Insert superreg source must be in a physical register");
138 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
139 "Insert destination must be in a physical register");
140 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
141 "Inserted value must be in a physical register");
143 DOUT << "subreg: CONVERTING: " << *MI;
145 // If the inserted register is already allocated into a subregister
146 // of the destination, we copy the subreg into the source
147 // However, this is only safe if the insert instruction is the kill
148 // of the source register
149 bool revCopyOrder = MRI.isSubRegOf(InsReg, DstReg);
150 if (revCopyOrder && InsReg != DstSubReg) {
151 if (MI->getOperand(1).isKill()) {
152 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
153 // Insert sub-register copy
154 const TargetRegisterClass *TRC1 = 0;
155 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
156 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
158 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
160 MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
163 MachineBasicBlock::iterator dMI = MI;
164 DOUT << "subreg: " << *(--dMI);
167 assert(0 && "Don't know how to convert this insert");
171 if (InsReg == DstSubReg) {
172 DOUT << "subreg: Eliminated subreg copy\n";
176 if (SrcReg != DstReg) {
177 // Insert super-register copy
178 const TargetRegisterClass *TRC0 = 0;
179 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
180 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
182 TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
184 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
185 "Insert superreg and Dst must be of same register class");
187 MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
190 MachineBasicBlock::iterator dMI = MI;
191 DOUT << "subreg: " << *(--dMI);
196 if (SrcReg == DstReg) {
197 DOUT << "subreg: Eliminated superreg copy\n";
201 if (!revCopyOrder && InsReg != DstSubReg) {
202 // Insert sub-register copy
203 const TargetRegisterClass *TRC1 = 0;
204 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
205 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
207 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
209 MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
212 MachineBasicBlock::iterator dMI = MI;
213 DOUT << "subreg: " << *(--dMI);
222 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
225 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
226 DOUT << "Machine Function\n";
228 bool MadeChange = false;
230 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
231 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
233 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
234 mbbi != mbbe; ++mbbi) {
235 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
237 MachineInstr *MI = mi++;
239 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
240 MadeChange |= LowerExtract(MI);
241 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
242 MadeChange |= LowerInsert(MI);