1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/raw_ostream.h"
32 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
33 : public MachineFunctionPass {
34 static char ID; // Pass identification, replacement for typeid
35 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
37 const char *getPassName() const {
38 return "Subregister lowering instruction pass";
41 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
42 AU.addPreservedID(MachineLoopInfoID);
43 AU.addPreservedID(MachineDominatorsID);
44 MachineFunctionPass::getAnalysisUsage(AU);
47 /// runOnMachineFunction - pass entry point
48 bool runOnMachineFunction(MachineFunction&);
50 bool LowerExtract(MachineInstr *MI);
51 bool LowerInsert(MachineInstr *MI);
52 bool LowerSubregToReg(MachineInstr *MI);
54 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
55 const TargetRegisterInfo &TRI);
56 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
57 const TargetRegisterInfo &TRI);
60 char LowerSubregsInstructionPass::ID = 0;
63 FunctionPass *llvm::createLowerSubregsPass() {
64 return new LowerSubregsInstructionPass();
67 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
68 /// and the lowered replacement instructions immediately precede it.
69 /// Mark the replacement instructions with the dead flag.
71 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
73 const TargetRegisterInfo &TRI) {
74 for (MachineBasicBlock::iterator MII =
75 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
76 if (MII->addRegisterDead(DstReg, &TRI))
78 assert(MII != MI->getParent()->begin() &&
79 "copyRegToReg output doesn't reference destination register!");
83 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
84 /// and the lowered replacement instructions immediately precede it.
85 /// Mark the replacement instructions with the kill flag.
87 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
89 const TargetRegisterInfo &TRI) {
90 for (MachineBasicBlock::iterator MII =
91 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
92 if (MII->addRegisterKilled(SrcReg, &TRI))
94 assert(MII != MI->getParent()->begin() &&
95 "copyRegToReg output doesn't reference source register!");
99 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
100 MachineBasicBlock *MBB = MI->getParent();
101 MachineFunction &MF = *MBB->getParent();
102 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
103 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
105 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
106 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
107 MI->getOperand(2).isImm() && "Malformed extract_subreg");
109 unsigned DstReg = MI->getOperand(0).getReg();
110 unsigned SuperReg = MI->getOperand(1).getReg();
111 unsigned SubIdx = MI->getOperand(2).getImm();
112 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
114 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
115 "Extract supperg source must be a physical register");
116 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
117 "Extract destination must be in a physical register");
119 DOUT << "subreg: CONVERTING: " << *MI;
121 if (SrcReg == DstReg) {
122 // No need to insert an identify copy instruction.
123 DOUT << "subreg: eliminated!";
124 // Find the kill of the destination register's live range, and insert
125 // a kill of the source register at that point.
126 if (MI->getOperand(1).isKill() && !MI->getOperand(0).isDead())
127 for (MachineBasicBlock::iterator MII =
128 next(MachineBasicBlock::iterator(MI));
129 MII != MBB->end(); ++MII)
130 if (MII->killsRegister(DstReg, &TRI)) {
131 MII->addRegisterKilled(SuperReg, &TRI, /*AddIfNotFound=*/true);
136 const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
137 const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
138 bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
140 assert(Emitted && "Subreg and Dst must be of compatible register class");
141 // Transfer the kill/dead flags, if needed.
142 if (MI->getOperand(0).isDead())
143 TransferDeadFlag(MI, DstReg, TRI);
144 if (MI->getOperand(1).isKill())
145 TransferKillFlag(MI, SrcReg, TRI);
148 MachineBasicBlock::iterator dMI = MI;
149 DOUT << "subreg: " << *(--dMI);
158 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
159 MachineBasicBlock *MBB = MI->getParent();
160 MachineFunction &MF = *MBB->getParent();
161 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
162 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
163 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
164 MI->getOperand(1).isImm() &&
165 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
166 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
168 unsigned DstReg = MI->getOperand(0).getReg();
169 unsigned InsReg = MI->getOperand(2).getReg();
170 unsigned InsSIdx = MI->getOperand(2).getSubReg();
171 unsigned SubIdx = MI->getOperand(3).getImm();
173 assert(SubIdx != 0 && "Invalid index for insert_subreg");
174 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
176 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
177 "Insert destination must be in a physical register");
178 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
179 "Inserted value must be in a physical register");
181 DOUT << "subreg: CONVERTING: " << *MI;
183 if (DstSubReg == InsReg && InsSIdx == 0) {
184 // No need to insert an identify copy instruction.
185 // Watch out for case like this:
187 // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
188 // The first def is defining RAX, not EAX so the top bits were not
190 DOUT << "subreg: eliminated!";
192 // Insert sub-register copy
193 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
194 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
195 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
196 // Transfer the kill/dead flags, if needed.
197 if (MI->getOperand(0).isDead())
198 TransferDeadFlag(MI, DstSubReg, TRI);
199 if (MI->getOperand(2).isKill())
200 TransferKillFlag(MI, InsReg, TRI);
203 MachineBasicBlock::iterator dMI = MI;
204 DOUT << "subreg: " << *(--dMI);
213 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
214 MachineBasicBlock *MBB = MI->getParent();
215 MachineFunction &MF = *MBB->getParent();
216 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
217 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
218 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
219 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
220 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
221 MI->getOperand(3).isImm() && "Invalid insert_subreg");
223 unsigned DstReg = MI->getOperand(0).getReg();
225 unsigned SrcReg = MI->getOperand(1).getReg();
227 unsigned InsReg = MI->getOperand(2).getReg();
228 unsigned SubIdx = MI->getOperand(3).getImm();
230 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
231 assert(SubIdx != 0 && "Invalid index for insert_subreg");
232 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
234 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
235 "Insert superreg source must be in a physical register");
236 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
237 "Inserted value must be in a physical register");
239 DOUT << "subreg: CONVERTING: " << *MI;
241 if (DstSubReg == InsReg) {
242 // No need to insert an identify copy instruction.
243 DOUT << "subreg: eliminated!";
245 // Insert sub-register copy
246 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
247 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
248 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
249 // Transfer the kill/dead flags, if needed.
250 if (MI->getOperand(0).isDead())
251 TransferDeadFlag(MI, DstSubReg, TRI);
252 if (MI->getOperand(1).isKill())
253 TransferKillFlag(MI, InsReg, TRI);
256 MachineBasicBlock::iterator dMI = MI;
257 DOUT << "subreg: " << *(--dMI);
266 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
269 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
270 DOUT << "Machine Function\n";
272 bool MadeChange = false;
274 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
275 DEBUG(errs() << "********** Function: "
276 << MF.getFunction()->getName() << '\n');
278 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
279 mbbi != mbbe; ++mbbi) {
280 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
282 MachineInstr *MI = mi++;
284 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
285 MadeChange |= LowerExtract(MI);
286 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
287 MadeChange |= LowerInsert(MI);
288 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
289 MadeChange |= LowerSubregToReg(MI);