1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 /// runOnMachineFunction - pass entry point
34 bool runOnMachineFunction(MachineFunction&);
36 bool LowerExtract(MachineInstr *MI);
37 bool LowerInsert(MachineInstr *MI);
40 char LowerSubregsInstructionPass::ID = 0;
43 FunctionPass *llvm::createLowerSubregsPass() {
44 return new LowerSubregsInstructionPass();
47 // Returns the Register Class of a physical register.
48 static const TargetRegisterClass *getPhysicalRegisterRegClass(
49 const TargetRegisterInfo &TRI,
51 assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
52 "reg must be a physical register");
53 // Pick the register class of the right type that contains this physreg.
54 for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
55 E = TRI.regclass_end(); I != E; ++I)
56 if ((*I)->contains(reg))
58 assert(false && "Couldn't find the register class");
62 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
63 MachineBasicBlock *MBB = MI->getParent();
64 MachineFunction &MF = *MBB->getParent();
65 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
66 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
68 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
69 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
70 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
72 unsigned SuperReg = MI->getOperand(1).getReg();
73 unsigned SubIdx = MI->getOperand(2).getImm();
75 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
76 "Extract supperg source must be a physical register");
77 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
78 unsigned DstReg = MI->getOperand(0).getReg();
80 DOUT << "subreg: CONVERTING: " << *MI;
82 if (SrcReg != DstReg) {
83 const TargetRegisterClass *TRC = 0;
84 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
85 TRC = getPhysicalRegisterRegClass(TRI, DstReg);
87 TRC = MF.getRegInfo().getRegClass(DstReg);
89 assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
90 "Extract subreg and Dst must be of same register class");
92 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
93 MachineBasicBlock::iterator dMI = MI;
94 DOUT << "subreg: " << *(--dMI);
103 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
104 MachineBasicBlock *MBB = MI->getParent();
105 MachineFunction &MF = *MBB->getParent();
106 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
107 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
108 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
109 ((MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) ||
110 MI->getOperand(1).isImmediate()) &&
111 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
112 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
114 unsigned DstReg = MI->getOperand(0).getReg();
116 // Check if we're inserting into an implicit value.
117 if (MI->getOperand(1).isImmediate())
120 SrcReg = MI->getOperand(1).getReg();
121 unsigned InsReg = MI->getOperand(2).getReg();
122 unsigned SubIdx = MI->getOperand(3).getImm();
124 assert(SubIdx != 0 && "Invalid index for extract_subreg");
125 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
127 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
128 "Insert superreg source must be in a physical register");
129 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
130 "Insert destination must be in a physical register");
131 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
132 "Inserted value must be in a physical register");
134 DOUT << "subreg: CONVERTING: " << *MI;
136 // If the inserted register is already allocated into a subregister
137 // of the destination, we copy the subreg into the source
138 // However, this is only safe if the insert instruction is the kill
139 // of the source register
140 bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
141 if (revCopyOrder && InsReg != DstSubReg) {
142 if (MI->getOperand(1).isKill()) {
143 DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
144 // Insert sub-register copy
145 const TargetRegisterClass *TRC1 = 0;
146 if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
147 TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
149 TRC1 = MF.getRegInfo().getRegClass(InsReg);
151 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
154 MachineBasicBlock::iterator dMI = MI;
155 DOUT << "subreg: " << *(--dMI);
158 assert(0 && "Don't know how to convert this insert");
162 if (InsReg == DstSubReg) {
163 DOUT << "subreg: Eliminated subreg copy\n";
167 if (SrcReg != DstReg) {
168 // Insert super-register copy
169 const TargetRegisterClass *TRC0 = 0;
170 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
171 TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
173 TRC0 = MF.getRegInfo().getRegClass(DstReg);
175 assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
176 "Insert superreg and Dst must be of same register class");
178 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
181 MachineBasicBlock::iterator dMI = MI;
182 DOUT << "subreg: " << *(--dMI);
187 if (SrcReg == DstReg) {
188 DOUT << "subreg: Eliminated superreg copy\n";
192 if (!revCopyOrder && InsReg != DstSubReg) {
193 // Insert sub-register copy
194 const TargetRegisterClass *TRC1 = 0;
195 if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
196 TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
198 TRC1 = MF.getRegInfo().getRegClass(InsReg);
200 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
203 MachineBasicBlock::iterator dMI = MI;
204 DOUT << "subreg: " << *(--dMI);
213 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
216 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
217 DOUT << "Machine Function\n";
219 bool MadeChange = false;
221 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
222 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
224 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
225 mbbi != mbbe; ++mbbi) {
226 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
228 MachineInstr *MI = mi++;
230 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
231 MadeChange |= LowerExtract(MI);
232 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
233 MadeChange |= LowerInsert(MI);