1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
34 AU.addPreservedID(MachineLoopInfoID);
35 AU.addPreservedID(MachineDominatorsID);
36 MachineFunctionPass::getAnalysisUsage(AU);
39 /// runOnMachineFunction - pass entry point
40 bool runOnMachineFunction(MachineFunction&);
42 bool LowerExtract(MachineInstr *MI);
43 bool LowerInsert(MachineInstr *MI);
44 bool LowerSubregToReg(MachineInstr *MI);
47 char LowerSubregsInstructionPass::ID = 0;
50 FunctionPass *llvm::createLowerSubregsPass() {
51 return new LowerSubregsInstructionPass();
54 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
55 MachineBasicBlock *MBB = MI->getParent();
56 MachineFunction &MF = *MBB->getParent();
57 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
58 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
60 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
61 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
62 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
64 unsigned DstReg = MI->getOperand(0).getReg();
65 unsigned SuperReg = MI->getOperand(1).getReg();
66 unsigned SubIdx = MI->getOperand(2).getImm();
67 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
69 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
70 "Extract supperg source must be a physical register");
71 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
72 "Insert destination must be in a physical register");
74 DOUT << "subreg: CONVERTING: " << *MI;
76 if (SrcReg != DstReg) {
77 const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
78 assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
79 "Extract subreg and Dst must be of same register class");
80 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
83 MachineBasicBlock::iterator dMI = MI;
84 DOUT << "subreg: " << *(--dMI);
93 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
94 MachineBasicBlock *MBB = MI->getParent();
95 MachineFunction &MF = *MBB->getParent();
96 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
97 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
98 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
99 MI->getOperand(1).isImmediate() &&
100 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
101 MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg");
103 unsigned DstReg = MI->getOperand(0).getReg();
104 unsigned InsReg = MI->getOperand(2).getReg();
105 unsigned SubIdx = MI->getOperand(3).getImm();
107 assert(SubIdx != 0 && "Invalid index for insert_subreg");
108 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
110 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
111 "Insert destination must be in a physical register");
112 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
113 "Inserted value must be in a physical register");
115 DOUT << "subreg: CONVERTING: " << *MI;
117 if (DstSubReg == InsReg) {
118 // No need to insert an identify copy instruction.
119 DOUT << "subreg: eliminated!";
121 // Insert sub-register copy
122 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
123 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
124 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
127 MachineBasicBlock::iterator dMI = MI;
128 DOUT << "subreg: " << *(--dMI);
137 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
138 MachineBasicBlock *MBB = MI->getParent();
139 MachineFunction &MF = *MBB->getParent();
140 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
141 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
142 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
143 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
144 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
145 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
147 unsigned DstReg = MI->getOperand(0).getReg();
148 unsigned SrcReg = MI->getOperand(1).getReg();
149 unsigned InsReg = MI->getOperand(2).getReg();
150 unsigned SubIdx = MI->getOperand(3).getImm();
152 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
153 assert(SubIdx != 0 && "Invalid index for insert_subreg");
154 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
156 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
157 "Insert superreg source must be in a physical register");
158 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
159 "Inserted value must be in a physical register");
161 DOUT << "subreg: CONVERTING: " << *MI;
163 if (DstSubReg == InsReg) {
164 // No need to insert an identify copy instruction.
165 DOUT << "subreg: eliminated!";
167 // Insert sub-register copy
168 const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
169 const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
170 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
172 MachineBasicBlock::iterator dMI = MI;
173 DOUT << "subreg: " << *(--dMI);
182 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
185 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
186 DOUT << "Machine Function\n";
188 bool MadeChange = false;
190 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
191 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
193 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
194 mbbi != mbbe; ++mbbi) {
195 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
197 MachineInstr *MI = mi++;
199 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
200 MadeChange |= LowerExtract(MI);
201 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
202 MadeChange |= LowerInsert(MI);
203 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
204 MadeChange |= LowerSubregToReg(MI);