1 //===- MIParser.cpp - Machine instructions parser implementation ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the parsing of machine instructions.
12 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/StringMap.h"
17 #include "llvm/AsmParser/SlotMapping.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/SourceMgr.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 #include "llvm/Target/TargetInstrInfo.h"
32 /// A wrapper struct around the 'MachineOperand' struct that includes a source
34 struct MachineOperandWithLocation {
35 MachineOperand Operand;
36 StringRef::iterator Begin;
37 StringRef::iterator End;
39 MachineOperandWithLocation(const MachineOperand &Operand,
40 StringRef::iterator Begin, StringRef::iterator End)
41 : Operand(Operand), Begin(Begin), End(End) {}
48 StringRef Source, CurrentSource;
50 const PerFunctionMIParsingState &PFS;
51 /// Maps from indices to unnamed global values and metadata nodes.
52 const SlotMapping &IRSlots;
53 /// Maps from instruction names to op codes.
54 StringMap<unsigned> Names2InstrOpCodes;
55 /// Maps from register names to registers.
56 StringMap<unsigned> Names2Regs;
57 /// Maps from register mask names to register masks.
58 StringMap<const uint32_t *> Names2RegMasks;
61 MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
62 StringRef Source, const PerFunctionMIParsingState &PFS,
63 const SlotMapping &IRSlots);
67 /// Report an error at the current location with the given message.
69 /// This function always return true.
70 bool error(const Twine &Msg);
72 /// Report an error at the given location with the given message.
74 /// This function always return true.
75 bool error(StringRef::iterator Loc, const Twine &Msg);
77 bool parse(MachineInstr *&MI);
78 bool parseMBB(MachineBasicBlock *&MBB);
80 bool parseRegister(unsigned &Reg);
81 bool parseRegisterFlag(unsigned &Flags);
82 bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
83 bool parseImmediateOperand(MachineOperand &Dest);
84 bool parseMBBReference(MachineBasicBlock *&MBB);
85 bool parseMBBOperand(MachineOperand &Dest);
86 bool parseGlobalAddressOperand(MachineOperand &Dest);
87 bool parseMachineOperand(MachineOperand &Dest);
90 /// Convert the integer literal in the current token into an unsigned integer.
92 /// Return true if an error occurred.
93 bool getUnsigned(unsigned &Result);
95 void initNames2InstrOpCodes();
97 /// Try to convert an instruction name to an opcode. Return true if the
98 /// instruction name is invalid.
99 bool parseInstrName(StringRef InstrName, unsigned &OpCode);
101 bool parseInstruction(unsigned &OpCode);
103 bool verifyImplicitOperands(ArrayRef<MachineOperandWithLocation> Operands,
104 const MCInstrDesc &MCID);
106 void initNames2Regs();
108 /// Try to convert a register name to a register number. Return true if the
109 /// register name is invalid.
110 bool getRegisterByName(StringRef RegName, unsigned &Reg);
112 void initNames2RegMasks();
114 /// Check if the given identifier is a name of a register mask.
116 /// Return null if the identifier isn't a register mask.
117 const uint32_t *getRegMask(StringRef Identifier);
120 } // end anonymous namespace
122 MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
123 StringRef Source, const PerFunctionMIParsingState &PFS,
124 const SlotMapping &IRSlots)
125 : SM(SM), MF(MF), Error(Error), Source(Source), CurrentSource(Source),
126 Token(MIToken::Error, StringRef()), PFS(PFS), IRSlots(IRSlots) {}
128 void MIParser::lex() {
129 CurrentSource = lexMIToken(
130 CurrentSource, Token,
131 [this](StringRef::iterator Loc, const Twine &Msg) { error(Loc, Msg); });
134 bool MIParser::error(const Twine &Msg) { return error(Token.location(), Msg); }
136 bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
137 // TODO: Get the proper location in the MIR file, not just a location inside
139 assert(Loc >= Source.data() && Loc <= (Source.data() + Source.size()));
140 Error = SMDiagnostic(
142 SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,
143 Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), Source, None, None);
147 bool MIParser::parse(MachineInstr *&MI) {
150 // Parse any register operands before '='
151 // TODO: Allow parsing of multiple operands before '='
152 MachineOperand MO = MachineOperand::CreateImm(0);
153 SmallVector<MachineOperandWithLocation, 8> Operands;
154 if (Token.isRegister() || Token.isRegisterFlag()) {
155 auto Loc = Token.location();
156 if (parseRegisterOperand(MO, /*IsDef=*/true))
158 Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
159 if (Token.isNot(MIToken::equal))
160 return error("expected '='");
165 if (Token.isError() || parseInstruction(OpCode))
168 // TODO: Parse the instruction flags and memory operands.
170 // Parse the remaining machine operands.
171 while (Token.isNot(MIToken::Eof)) {
172 auto Loc = Token.location();
173 if (parseMachineOperand(MO))
175 Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
176 if (Token.is(MIToken::Eof))
178 if (Token.isNot(MIToken::comma))
179 return error("expected ',' before the next machine operand");
183 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
184 if (!MCID.isVariadic()) {
185 // FIXME: Move the implicit operand verification to the machine verifier.
186 if (verifyImplicitOperands(Operands, MCID))
190 // TODO: Check for extraneous machine operands.
191 MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
192 for (const auto &Operand : Operands)
193 MI->addOperand(MF, Operand.Operand);
197 bool MIParser::parseMBB(MachineBasicBlock *&MBB) {
199 if (Token.isNot(MIToken::MachineBasicBlock))
200 return error("expected a machine basic block reference");
201 if (parseMBBReference(MBB))
204 if (Token.isNot(MIToken::Eof))
206 "expected end of string after the machine basic block reference");
210 static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
211 assert(MO.isImplicit());
212 return MO.isDef() ? "implicit-def" : "implicit";
215 static std::string getRegisterName(const TargetRegisterInfo *TRI,
217 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "expected phys reg");
218 return StringRef(TRI->getName(Reg)).lower();
221 bool MIParser::verifyImplicitOperands(
222 ArrayRef<MachineOperandWithLocation> Operands, const MCInstrDesc &MCID) {
224 // We can't verify call instructions as they can contain arbitrary implicit
225 // register and register mask operands.
228 // Gather all the expected implicit operands.
229 SmallVector<MachineOperand, 4> ImplicitOperands;
230 if (MCID.ImplicitDefs)
231 for (const uint16_t *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
232 ImplicitOperands.push_back(
233 MachineOperand::CreateReg(*ImpDefs, true, true));
234 if (MCID.ImplicitUses)
235 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
236 ImplicitOperands.push_back(
237 MachineOperand::CreateReg(*ImpUses, false, true));
239 const auto *TRI = MF.getSubtarget().getRegisterInfo();
240 assert(TRI && "Expected target register info");
241 size_t I = ImplicitOperands.size(), J = Operands.size();
246 const auto &ImplicitOperand = ImplicitOperands[I];
247 const auto &Operand = Operands[J].Operand;
248 if (ImplicitOperand.isIdenticalTo(Operand))
250 if (Operand.isReg() && Operand.isImplicit()) {
251 return error(Operands[J].Begin,
252 Twine("expected an implicit register operand '") +
253 printImplicitRegisterFlag(ImplicitOperand) + " %" +
254 getRegisterName(TRI, ImplicitOperand.getReg()) + "'");
257 // TODO: Fix source location when Operands[J].end is right before '=', i.e:
258 // insead of reporting an error at this location:
261 // report the error at the following location:
264 return error(J < Operands.size() ? Operands[J].End : Token.location(),
265 Twine("missing implicit register operand '") +
266 printImplicitRegisterFlag(ImplicitOperands[I]) + " %" +
267 getRegisterName(TRI, ImplicitOperands[I].getReg()) + "'");
272 bool MIParser::parseInstruction(unsigned &OpCode) {
273 if (Token.isNot(MIToken::Identifier))
274 return error("expected a machine instruction");
275 StringRef InstrName = Token.stringValue();
276 if (parseInstrName(InstrName, OpCode))
277 return error(Twine("unknown machine instruction name '") + InstrName + "'");
282 bool MIParser::parseRegister(unsigned &Reg) {
283 switch (Token.kind()) {
284 case MIToken::underscore:
287 case MIToken::NamedRegister: {
288 StringRef Name = Token.stringValue();
289 if (getRegisterByName(Name, Reg))
290 return error(Twine("unknown register name '") + Name + "'");
293 // TODO: Parse other register kinds.
295 llvm_unreachable("The current token should be a register");
300 bool MIParser::parseRegisterFlag(unsigned &Flags) {
301 switch (Token.kind()) {
302 case MIToken::kw_implicit:
303 Flags |= RegState::Implicit;
305 case MIToken::kw_implicit_define:
306 Flags |= RegState::ImplicitDefine;
308 case MIToken::kw_dead:
309 Flags |= RegState::Dead;
311 // TODO: report an error when we specify the same flag more than once.
312 // TODO: parse the other register flags.
314 llvm_unreachable("The current token should be a register flag");
320 bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
322 unsigned Flags = IsDef ? RegState::Define : 0;
323 while (Token.isRegisterFlag()) {
324 if (parseRegisterFlag(Flags))
327 if (!Token.isRegister())
328 return error("expected a register after register flags");
329 if (parseRegister(Reg))
332 // TODO: Parse subregister.
333 Dest = MachineOperand::CreateReg(Reg, Flags & RegState::Define,
334 Flags & RegState::Implicit, /*IsKill=*/false,
335 Flags & RegState::Dead);
339 bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
340 assert(Token.is(MIToken::IntegerLiteral));
341 const APSInt &Int = Token.integerValue();
342 if (Int.getMinSignedBits() > 64)
343 // TODO: Replace this with an error when we can parse CIMM Machine Operands.
344 llvm_unreachable("Can't parse large integer literals yet!");
345 Dest = MachineOperand::CreateImm(Int.getExtValue());
350 bool MIParser::getUnsigned(unsigned &Result) {
351 assert(Token.hasIntegerValue() && "Expected a token with an integer value");
352 const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1;
353 uint64_t Val64 = Token.integerValue().getLimitedValue(Limit);
355 return error("expected 32-bit integer (too large)");
360 bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) {
361 assert(Token.is(MIToken::MachineBasicBlock));
363 if (getUnsigned(Number))
365 auto MBBInfo = PFS.MBBSlots.find(Number);
366 if (MBBInfo == PFS.MBBSlots.end())
367 return error(Twine("use of undefined machine basic block #") +
369 MBB = MBBInfo->second;
370 if (!Token.stringValue().empty() && Token.stringValue() != MBB->getName())
371 return error(Twine("the name of machine basic block #") + Twine(Number) +
372 " isn't '" + Token.stringValue() + "'");
376 bool MIParser::parseMBBOperand(MachineOperand &Dest) {
377 MachineBasicBlock *MBB;
378 if (parseMBBReference(MBB))
380 Dest = MachineOperand::CreateMBB(MBB);
385 bool MIParser::parseGlobalAddressOperand(MachineOperand &Dest) {
386 switch (Token.kind()) {
387 case MIToken::NamedGlobalValue: {
388 auto Name = Token.stringValue();
389 const Module *M = MF.getFunction()->getParent();
390 if (const auto *GV = M->getNamedValue(Name)) {
391 Dest = MachineOperand::CreateGA(GV, /*Offset=*/0);
394 return error(Twine("use of undefined global value '@") + Name + "'");
396 case MIToken::GlobalValue: {
398 if (getUnsigned(GVIdx))
400 if (GVIdx >= IRSlots.GlobalValues.size())
401 return error(Twine("use of undefined global value '@") + Twine(GVIdx) +
403 Dest = MachineOperand::CreateGA(IRSlots.GlobalValues[GVIdx],
408 llvm_unreachable("The current token should be a global value");
410 // TODO: Parse offset and target flags.
415 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
416 switch (Token.kind()) {
417 case MIToken::kw_implicit:
418 case MIToken::kw_implicit_define:
419 case MIToken::kw_dead:
420 case MIToken::underscore:
421 case MIToken::NamedRegister:
422 return parseRegisterOperand(Dest);
423 case MIToken::IntegerLiteral:
424 return parseImmediateOperand(Dest);
425 case MIToken::MachineBasicBlock:
426 return parseMBBOperand(Dest);
427 case MIToken::GlobalValue:
428 case MIToken::NamedGlobalValue:
429 return parseGlobalAddressOperand(Dest);
432 case MIToken::Identifier:
433 if (const auto *RegMask = getRegMask(Token.stringValue())) {
434 Dest = MachineOperand::CreateRegMask(RegMask);
440 // TODO: parse the other machine operands.
441 return error("expected a machine operand");
446 void MIParser::initNames2InstrOpCodes() {
447 if (!Names2InstrOpCodes.empty())
449 const auto *TII = MF.getSubtarget().getInstrInfo();
450 assert(TII && "Expected target instruction info");
451 for (unsigned I = 0, E = TII->getNumOpcodes(); I < E; ++I)
452 Names2InstrOpCodes.insert(std::make_pair(StringRef(TII->getName(I)), I));
455 bool MIParser::parseInstrName(StringRef InstrName, unsigned &OpCode) {
456 initNames2InstrOpCodes();
457 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
458 if (InstrInfo == Names2InstrOpCodes.end())
460 OpCode = InstrInfo->getValue();
464 void MIParser::initNames2Regs() {
465 if (!Names2Regs.empty())
467 // The '%noreg' register is the register 0.
468 Names2Regs.insert(std::make_pair("noreg", 0));
469 const auto *TRI = MF.getSubtarget().getRegisterInfo();
470 assert(TRI && "Expected target register info");
471 for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
473 Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
476 assert(WasInserted && "Expected registers to be unique case-insensitively");
480 bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
482 auto RegInfo = Names2Regs.find(RegName);
483 if (RegInfo == Names2Regs.end())
485 Reg = RegInfo->getValue();
489 void MIParser::initNames2RegMasks() {
490 if (!Names2RegMasks.empty())
492 const auto *TRI = MF.getSubtarget().getRegisterInfo();
493 assert(TRI && "Expected target register info");
494 ArrayRef<const uint32_t *> RegMasks = TRI->getRegMasks();
495 ArrayRef<const char *> RegMaskNames = TRI->getRegMaskNames();
496 assert(RegMasks.size() == RegMaskNames.size());
497 for (size_t I = 0, E = RegMasks.size(); I < E; ++I)
498 Names2RegMasks.insert(
499 std::make_pair(StringRef(RegMaskNames[I]).lower(), RegMasks[I]));
502 const uint32_t *MIParser::getRegMask(StringRef Identifier) {
503 initNames2RegMasks();
504 auto RegMaskInfo = Names2RegMasks.find(Identifier);
505 if (RegMaskInfo == Names2RegMasks.end())
507 return RegMaskInfo->getValue();
510 bool llvm::parseMachineInstr(MachineInstr *&MI, SourceMgr &SM,
511 MachineFunction &MF, StringRef Src,
512 const PerFunctionMIParsingState &PFS,
513 const SlotMapping &IRSlots, SMDiagnostic &Error) {
514 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parse(MI);
517 bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
518 MachineFunction &MF, StringRef Src,
519 const PerFunctionMIParsingState &PFS,
520 const SlotMapping &IRSlots, SMDiagnostic &Error) {
521 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);