1 //===- MIParser.cpp - Machine instructions parser implementation ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the parsing of machine instructions.
12 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/StringMap.h"
17 #include "llvm/AsmParser/SlotMapping.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/SourceMgr.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 #include "llvm/Target/TargetInstrInfo.h"
32 /// A wrapper struct around the 'MachineOperand' struct that includes a source
34 struct MachineOperandWithLocation {
35 MachineOperand Operand;
36 StringRef::iterator Begin;
37 StringRef::iterator End;
39 MachineOperandWithLocation(const MachineOperand &Operand,
40 StringRef::iterator Begin, StringRef::iterator End)
41 : Operand(Operand), Begin(Begin), End(End) {}
48 StringRef Source, CurrentSource;
50 const PerFunctionMIParsingState &PFS;
51 /// Maps from indices to unnamed global values and metadata nodes.
52 const SlotMapping &IRSlots;
53 /// Maps from instruction names to op codes.
54 StringMap<unsigned> Names2InstrOpCodes;
55 /// Maps from register names to registers.
56 StringMap<unsigned> Names2Regs;
57 /// Maps from register mask names to register masks.
58 StringMap<const uint32_t *> Names2RegMasks;
59 /// Maps from subregister names to subregister indices.
60 StringMap<unsigned> Names2SubRegIndices;
63 MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
64 StringRef Source, const PerFunctionMIParsingState &PFS,
65 const SlotMapping &IRSlots);
69 /// Report an error at the current location with the given message.
71 /// This function always return true.
72 bool error(const Twine &Msg);
74 /// Report an error at the given location with the given message.
76 /// This function always return true.
77 bool error(StringRef::iterator Loc, const Twine &Msg);
79 bool parse(MachineInstr *&MI);
80 bool parseMBB(MachineBasicBlock *&MBB);
82 bool parseRegister(unsigned &Reg);
83 bool parseRegisterFlag(unsigned &Flags);
84 bool parseSubRegisterIndex(unsigned &SubReg);
85 bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
86 bool parseImmediateOperand(MachineOperand &Dest);
87 bool parseMBBReference(MachineBasicBlock *&MBB);
88 bool parseMBBOperand(MachineOperand &Dest);
89 bool parseGlobalAddressOperand(MachineOperand &Dest);
90 bool parseMachineOperand(MachineOperand &Dest);
93 /// Convert the integer literal in the current token into an unsigned integer.
95 /// Return true if an error occurred.
96 bool getUnsigned(unsigned &Result);
98 void initNames2InstrOpCodes();
100 /// Try to convert an instruction name to an opcode. Return true if the
101 /// instruction name is invalid.
102 bool parseInstrName(StringRef InstrName, unsigned &OpCode);
104 bool parseInstruction(unsigned &OpCode);
106 bool verifyImplicitOperands(ArrayRef<MachineOperandWithLocation> Operands,
107 const MCInstrDesc &MCID);
109 void initNames2Regs();
111 /// Try to convert a register name to a register number. Return true if the
112 /// register name is invalid.
113 bool getRegisterByName(StringRef RegName, unsigned &Reg);
115 void initNames2RegMasks();
117 /// Check if the given identifier is a name of a register mask.
119 /// Return null if the identifier isn't a register mask.
120 const uint32_t *getRegMask(StringRef Identifier);
122 void initNames2SubRegIndices();
124 /// Check if the given identifier is a name of a subregister index.
126 /// Return 0 if the name isn't a subregister index class.
127 unsigned getSubRegIndex(StringRef Name);
130 } // end anonymous namespace
132 MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
133 StringRef Source, const PerFunctionMIParsingState &PFS,
134 const SlotMapping &IRSlots)
135 : SM(SM), MF(MF), Error(Error), Source(Source), CurrentSource(Source),
136 Token(MIToken::Error, StringRef()), PFS(PFS), IRSlots(IRSlots) {}
138 void MIParser::lex() {
139 CurrentSource = lexMIToken(
140 CurrentSource, Token,
141 [this](StringRef::iterator Loc, const Twine &Msg) { error(Loc, Msg); });
144 bool MIParser::error(const Twine &Msg) { return error(Token.location(), Msg); }
146 bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
147 assert(Loc >= Source.data() && Loc <= (Source.data() + Source.size()));
148 Error = SMDiagnostic(
150 SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,
151 Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), Source, None, None);
155 bool MIParser::parse(MachineInstr *&MI) {
158 // Parse any register operands before '='
159 // TODO: Allow parsing of multiple operands before '='
160 MachineOperand MO = MachineOperand::CreateImm(0);
161 SmallVector<MachineOperandWithLocation, 8> Operands;
162 if (Token.isRegister() || Token.isRegisterFlag()) {
163 auto Loc = Token.location();
164 if (parseRegisterOperand(MO, /*IsDef=*/true))
166 Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
167 if (Token.isNot(MIToken::equal))
168 return error("expected '='");
173 if (Token.isError() || parseInstruction(OpCode))
176 // TODO: Parse the instruction flags and memory operands.
178 // Parse the remaining machine operands.
179 while (Token.isNot(MIToken::Eof)) {
180 auto Loc = Token.location();
181 if (parseMachineOperand(MO))
183 Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
184 if (Token.is(MIToken::Eof))
186 if (Token.isNot(MIToken::comma))
187 return error("expected ',' before the next machine operand");
191 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
192 if (!MCID.isVariadic()) {
193 // FIXME: Move the implicit operand verification to the machine verifier.
194 if (verifyImplicitOperands(Operands, MCID))
198 // TODO: Check for extraneous machine operands.
199 MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
200 for (const auto &Operand : Operands)
201 MI->addOperand(MF, Operand.Operand);
205 bool MIParser::parseMBB(MachineBasicBlock *&MBB) {
207 if (Token.isNot(MIToken::MachineBasicBlock))
208 return error("expected a machine basic block reference");
209 if (parseMBBReference(MBB))
212 if (Token.isNot(MIToken::Eof))
214 "expected end of string after the machine basic block reference");
218 static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
219 assert(MO.isImplicit());
220 return MO.isDef() ? "implicit-def" : "implicit";
223 static std::string getRegisterName(const TargetRegisterInfo *TRI,
225 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "expected phys reg");
226 return StringRef(TRI->getName(Reg)).lower();
229 bool MIParser::verifyImplicitOperands(
230 ArrayRef<MachineOperandWithLocation> Operands, const MCInstrDesc &MCID) {
232 // We can't verify call instructions as they can contain arbitrary implicit
233 // register and register mask operands.
236 // Gather all the expected implicit operands.
237 SmallVector<MachineOperand, 4> ImplicitOperands;
238 if (MCID.ImplicitDefs)
239 for (const uint16_t *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
240 ImplicitOperands.push_back(
241 MachineOperand::CreateReg(*ImpDefs, true, true));
242 if (MCID.ImplicitUses)
243 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
244 ImplicitOperands.push_back(
245 MachineOperand::CreateReg(*ImpUses, false, true));
247 const auto *TRI = MF.getSubtarget().getRegisterInfo();
248 assert(TRI && "Expected target register info");
249 size_t I = ImplicitOperands.size(), J = Operands.size();
254 const auto &ImplicitOperand = ImplicitOperands[I];
255 const auto &Operand = Operands[J].Operand;
256 if (ImplicitOperand.isIdenticalTo(Operand))
258 if (Operand.isReg() && Operand.isImplicit()) {
259 return error(Operands[J].Begin,
260 Twine("expected an implicit register operand '") +
261 printImplicitRegisterFlag(ImplicitOperand) + " %" +
262 getRegisterName(TRI, ImplicitOperand.getReg()) + "'");
265 // TODO: Fix source location when Operands[J].end is right before '=', i.e:
266 // insead of reporting an error at this location:
269 // report the error at the following location:
272 return error(J < Operands.size() ? Operands[J].End : Token.location(),
273 Twine("missing implicit register operand '") +
274 printImplicitRegisterFlag(ImplicitOperands[I]) + " %" +
275 getRegisterName(TRI, ImplicitOperands[I].getReg()) + "'");
280 bool MIParser::parseInstruction(unsigned &OpCode) {
281 if (Token.isNot(MIToken::Identifier))
282 return error("expected a machine instruction");
283 StringRef InstrName = Token.stringValue();
284 if (parseInstrName(InstrName, OpCode))
285 return error(Twine("unknown machine instruction name '") + InstrName + "'");
290 bool MIParser::parseRegister(unsigned &Reg) {
291 switch (Token.kind()) {
292 case MIToken::underscore:
295 case MIToken::NamedRegister: {
296 StringRef Name = Token.stringValue();
297 if (getRegisterByName(Name, Reg))
298 return error(Twine("unknown register name '") + Name + "'");
301 case MIToken::VirtualRegister: {
305 const auto RegInfo = PFS.VirtualRegisterSlots.find(ID);
306 if (RegInfo == PFS.VirtualRegisterSlots.end())
307 return error(Twine("use of undefined virtual register '%") + Twine(ID) +
309 Reg = RegInfo->second;
312 // TODO: Parse other register kinds.
314 llvm_unreachable("The current token should be a register");
319 bool MIParser::parseRegisterFlag(unsigned &Flags) {
320 switch (Token.kind()) {
321 case MIToken::kw_implicit:
322 Flags |= RegState::Implicit;
324 case MIToken::kw_implicit_define:
325 Flags |= RegState::ImplicitDefine;
327 case MIToken::kw_dead:
328 Flags |= RegState::Dead;
330 case MIToken::kw_killed:
331 Flags |= RegState::Kill;
333 case MIToken::kw_undef:
334 Flags |= RegState::Undef;
336 // TODO: report an error when we specify the same flag more than once.
337 // TODO: parse the other register flags.
339 llvm_unreachable("The current token should be a register flag");
345 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
346 assert(Token.is(MIToken::colon));
348 if (Token.isNot(MIToken::Identifier))
349 return error("expected a subregister index after ':'");
350 auto Name = Token.stringValue();
351 SubReg = getSubRegIndex(Name);
353 return error(Twine("use of unknown subregister index '") + Name + "'");
358 bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
360 unsigned Flags = IsDef ? RegState::Define : 0;
361 while (Token.isRegisterFlag()) {
362 if (parseRegisterFlag(Flags))
365 if (!Token.isRegister())
366 return error("expected a register after register flags");
367 if (parseRegister(Reg))
371 if (Token.is(MIToken::colon)) {
372 if (parseSubRegisterIndex(SubReg))
375 Dest = MachineOperand::CreateReg(
376 Reg, Flags & RegState::Define, Flags & RegState::Implicit,
377 Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
378 /*isEarlyClobber=*/false, SubReg);
382 bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
383 assert(Token.is(MIToken::IntegerLiteral));
384 const APSInt &Int = Token.integerValue();
385 if (Int.getMinSignedBits() > 64)
386 // TODO: Replace this with an error when we can parse CIMM Machine Operands.
387 llvm_unreachable("Can't parse large integer literals yet!");
388 Dest = MachineOperand::CreateImm(Int.getExtValue());
393 bool MIParser::getUnsigned(unsigned &Result) {
394 assert(Token.hasIntegerValue() && "Expected a token with an integer value");
395 const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1;
396 uint64_t Val64 = Token.integerValue().getLimitedValue(Limit);
398 return error("expected 32-bit integer (too large)");
403 bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) {
404 assert(Token.is(MIToken::MachineBasicBlock));
406 if (getUnsigned(Number))
408 auto MBBInfo = PFS.MBBSlots.find(Number);
409 if (MBBInfo == PFS.MBBSlots.end())
410 return error(Twine("use of undefined machine basic block #") +
412 MBB = MBBInfo->second;
413 if (!Token.stringValue().empty() && Token.stringValue() != MBB->getName())
414 return error(Twine("the name of machine basic block #") + Twine(Number) +
415 " isn't '" + Token.stringValue() + "'");
419 bool MIParser::parseMBBOperand(MachineOperand &Dest) {
420 MachineBasicBlock *MBB;
421 if (parseMBBReference(MBB))
423 Dest = MachineOperand::CreateMBB(MBB);
428 bool MIParser::parseGlobalAddressOperand(MachineOperand &Dest) {
429 switch (Token.kind()) {
430 case MIToken::NamedGlobalValue: {
431 auto Name = Token.stringValue();
432 const Module *M = MF.getFunction()->getParent();
433 if (const auto *GV = M->getNamedValue(Name)) {
434 Dest = MachineOperand::CreateGA(GV, /*Offset=*/0);
437 return error(Twine("use of undefined global value '@") + Name + "'");
439 case MIToken::GlobalValue: {
441 if (getUnsigned(GVIdx))
443 if (GVIdx >= IRSlots.GlobalValues.size())
444 return error(Twine("use of undefined global value '@") + Twine(GVIdx) +
446 Dest = MachineOperand::CreateGA(IRSlots.GlobalValues[GVIdx],
451 llvm_unreachable("The current token should be a global value");
453 // TODO: Parse offset and target flags.
458 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
459 switch (Token.kind()) {
460 case MIToken::kw_implicit:
461 case MIToken::kw_implicit_define:
462 case MIToken::kw_dead:
463 case MIToken::kw_killed:
464 case MIToken::kw_undef:
465 case MIToken::underscore:
466 case MIToken::NamedRegister:
467 case MIToken::VirtualRegister:
468 return parseRegisterOperand(Dest);
469 case MIToken::IntegerLiteral:
470 return parseImmediateOperand(Dest);
471 case MIToken::MachineBasicBlock:
472 return parseMBBOperand(Dest);
473 case MIToken::GlobalValue:
474 case MIToken::NamedGlobalValue:
475 return parseGlobalAddressOperand(Dest);
478 case MIToken::Identifier:
479 if (const auto *RegMask = getRegMask(Token.stringValue())) {
480 Dest = MachineOperand::CreateRegMask(RegMask);
486 // TODO: parse the other machine operands.
487 return error("expected a machine operand");
492 void MIParser::initNames2InstrOpCodes() {
493 if (!Names2InstrOpCodes.empty())
495 const auto *TII = MF.getSubtarget().getInstrInfo();
496 assert(TII && "Expected target instruction info");
497 for (unsigned I = 0, E = TII->getNumOpcodes(); I < E; ++I)
498 Names2InstrOpCodes.insert(std::make_pair(StringRef(TII->getName(I)), I));
501 bool MIParser::parseInstrName(StringRef InstrName, unsigned &OpCode) {
502 initNames2InstrOpCodes();
503 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
504 if (InstrInfo == Names2InstrOpCodes.end())
506 OpCode = InstrInfo->getValue();
510 void MIParser::initNames2Regs() {
511 if (!Names2Regs.empty())
513 // The '%noreg' register is the register 0.
514 Names2Regs.insert(std::make_pair("noreg", 0));
515 const auto *TRI = MF.getSubtarget().getRegisterInfo();
516 assert(TRI && "Expected target register info");
517 for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
519 Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
522 assert(WasInserted && "Expected registers to be unique case-insensitively");
526 bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
528 auto RegInfo = Names2Regs.find(RegName);
529 if (RegInfo == Names2Regs.end())
531 Reg = RegInfo->getValue();
535 void MIParser::initNames2RegMasks() {
536 if (!Names2RegMasks.empty())
538 const auto *TRI = MF.getSubtarget().getRegisterInfo();
539 assert(TRI && "Expected target register info");
540 ArrayRef<const uint32_t *> RegMasks = TRI->getRegMasks();
541 ArrayRef<const char *> RegMaskNames = TRI->getRegMaskNames();
542 assert(RegMasks.size() == RegMaskNames.size());
543 for (size_t I = 0, E = RegMasks.size(); I < E; ++I)
544 Names2RegMasks.insert(
545 std::make_pair(StringRef(RegMaskNames[I]).lower(), RegMasks[I]));
548 const uint32_t *MIParser::getRegMask(StringRef Identifier) {
549 initNames2RegMasks();
550 auto RegMaskInfo = Names2RegMasks.find(Identifier);
551 if (RegMaskInfo == Names2RegMasks.end())
553 return RegMaskInfo->getValue();
556 void MIParser::initNames2SubRegIndices() {
557 if (!Names2SubRegIndices.empty())
559 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
560 for (unsigned I = 1, E = TRI->getNumSubRegIndices(); I < E; ++I)
561 Names2SubRegIndices.insert(
562 std::make_pair(StringRef(TRI->getSubRegIndexName(I)).lower(), I));
565 unsigned MIParser::getSubRegIndex(StringRef Name) {
566 initNames2SubRegIndices();
567 auto SubRegInfo = Names2SubRegIndices.find(Name);
568 if (SubRegInfo == Names2SubRegIndices.end())
570 return SubRegInfo->getValue();
573 bool llvm::parseMachineInstr(MachineInstr *&MI, SourceMgr &SM,
574 MachineFunction &MF, StringRef Src,
575 const PerFunctionMIParsingState &PFS,
576 const SlotMapping &IRSlots, SMDiagnostic &Error) {
577 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parse(MI);
580 bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
581 MachineFunction &MF, StringRef Src,
582 const PerFunctionMIParsingState &PFS,
583 const SlotMapping &IRSlots, SMDiagnostic &Error) {
584 return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);