1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MIRYamlMapping.h"
19 #include "llvm/IR/BasicBlock.h"
20 #include "llvm/IR/Module.h"
21 #include "llvm/Support/MemoryBuffer.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Support/YAMLTraits.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
31 /// This class prints out the machine functions using the MIR serialization
37 MIRPrinter(raw_ostream &OS) : OS(OS) {}
39 void print(const MachineFunction &MF);
41 void convert(yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB);
44 /// This class prints out the machine instructions using the MIR serialization
50 MIPrinter(raw_ostream &OS) : OS(OS) {}
52 void print(const MachineInstr &MI);
53 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
56 } // end anonymous namespace
61 /// This struct serializes the LLVM IR module.
62 template <> struct BlockScalarTraits<Module> {
63 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
64 Mod.print(OS, nullptr);
66 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
67 llvm_unreachable("LLVM Module is supposed to be parsed separately");
72 } // end namespace yaml
73 } // end namespace llvm
75 void MIRPrinter::print(const MachineFunction &MF) {
76 yaml::MachineFunction YamlMF;
77 YamlMF.Name = MF.getName();
78 YamlMF.Alignment = MF.getAlignment();
79 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
80 YamlMF.HasInlineAsm = MF.hasInlineAsm();
81 for (const auto &MBB : MF) {
82 yaml::MachineBasicBlock YamlMBB;
83 convert(YamlMBB, MBB);
84 YamlMF.BasicBlocks.push_back(YamlMBB);
90 void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
91 const MachineBasicBlock &MBB) {
92 // TODO: Serialize unnamed BB references.
93 if (const auto *BB = MBB.getBasicBlock())
94 YamlMBB.Name = BB->hasName() ? BB->getName() : "<unnamed bb>";
97 YamlMBB.Alignment = MBB.getAlignment();
98 YamlMBB.AddressTaken = MBB.hasAddressTaken();
99 YamlMBB.IsLandingPad = MBB.isLandingPad();
101 // Print the machine instructions.
102 YamlMBB.Instructions.reserve(MBB.size());
104 for (const auto &MI : MBB) {
105 raw_string_ostream StrOS(Str);
106 MIPrinter(StrOS).print(MI);
107 YamlMBB.Instructions.push_back(StrOS.str());
112 void MIPrinter::print(const MachineInstr &MI) {
113 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
114 const auto *TRI = SubTarget.getRegisterInfo();
115 assert(TRI && "Expected target register info");
116 const auto *TII = SubTarget.getInstrInfo();
117 assert(TII && "Expected target instruction info");
119 unsigned I = 0, E = MI.getNumOperands();
120 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
121 !MI.getOperand(I).isImplicit();
125 print(MI.getOperand(I), TRI);
130 OS << TII->getName(MI.getOpcode());
131 // TODO: Print the instruction flags, machine mem operands.
135 bool NeedComma = false;
139 print(MI.getOperand(I), TRI);
144 static void printReg(unsigned Reg, raw_ostream &OS,
145 const TargetRegisterInfo *TRI) {
146 // TODO: Print Stack Slots.
147 // TODO: Print virtual registers.
150 else if (Reg < TRI->getNumRegs())
151 OS << '%' << StringRef(TRI->getName(Reg)).lower();
153 llvm_unreachable("Can't print this kind of register yet");
156 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
157 switch (Op.getType()) {
158 case MachineOperand::MO_Register:
159 // TODO: Print register flags.
160 printReg(Op.getReg(), OS, TRI);
161 // TODO: Print sub register.
163 case MachineOperand::MO_Immediate:
167 // TODO: Print the other machine operands.
168 llvm_unreachable("Can't print this machine operand at the moment");
172 void llvm::printMIR(raw_ostream &OS, const Module &M) {
173 yaml::Output Out(OS);
174 Out << const_cast<Module &>(M);
177 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
178 MIRPrinter Printer(OS);