1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/Support/MemoryBuffer.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/YAMLTraits.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
40 /// This structure describes how to print out stack object references.
41 struct FrameIndexOperand {
46 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
47 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
49 /// Return an ordinary stack object reference.
50 static FrameIndexOperand create(StringRef Name, unsigned ID) {
51 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
54 /// Return a fixed stack object reference.
55 static FrameIndexOperand createFixed(unsigned ID) {
56 return FrameIndexOperand("", ID, /*IsFixed=*/true);
60 } // end anonymous namespace
64 /// This class prints out the machine functions using the MIR serialization
68 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
69 /// Maps from stack object indices to operand indices which will be used when
70 /// printing frame index machine operands.
71 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
74 MIRPrinter(raw_ostream &OS) : OS(OS) {}
76 void print(const MachineFunction &MF);
78 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
79 const TargetRegisterInfo *TRI);
80 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
81 const MachineFrameInfo &MFI);
82 void convert(yaml::MachineFunction &MF,
83 const MachineConstantPool &ConstantPool);
84 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
85 const MachineJumpTableInfo &JTI);
86 void convertStackObjects(yaml::MachineFunction &MF,
87 const MachineFrameInfo &MFI, ModuleSlotTracker &MST,
88 const TargetRegisterInfo *TRI);
91 void initRegisterMaskIds(const MachineFunction &MF);
94 /// This class prints out the machine instructions using the MIR serialization
98 ModuleSlotTracker &MST;
99 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
100 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
103 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
104 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
105 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
106 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
107 StackObjectOperandMapping(StackObjectOperandMapping) {}
109 void print(const MachineBasicBlock &MBB);
111 void print(const MachineInstr &MI);
112 void printMBBReference(const MachineBasicBlock &MBB);
113 void printIRBlockReference(const BasicBlock &BB);
114 void printIRValueReference(const Value &V);
115 void printStackObjectReference(int FrameIndex);
116 void printOffset(int64_t Offset);
117 void printTargetFlags(const MachineOperand &Op);
118 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
119 void print(const MachineMemOperand &Op);
121 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
124 } // end namespace llvm
129 /// This struct serializes the LLVM IR module.
130 template <> struct BlockScalarTraits<Module> {
131 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
132 Mod.print(OS, nullptr);
134 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
135 llvm_unreachable("LLVM Module is supposed to be parsed separately");
140 } // end namespace yaml
141 } // end namespace llvm
143 static void printReg(unsigned Reg, raw_ostream &OS,
144 const TargetRegisterInfo *TRI) {
145 // TODO: Print Stack Slots.
148 else if (TargetRegisterInfo::isVirtualRegister(Reg))
149 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
150 else if (Reg < TRI->getNumRegs())
151 OS << '%' << StringRef(TRI->getName(Reg)).lower();
153 llvm_unreachable("Can't print this kind of register yet");
156 static void printReg(unsigned Reg, yaml::StringValue &Dest,
157 const TargetRegisterInfo *TRI) {
158 raw_string_ostream OS(Dest.Value);
159 printReg(Reg, OS, TRI);
162 void MIRPrinter::print(const MachineFunction &MF) {
163 initRegisterMaskIds(MF);
165 yaml::MachineFunction YamlMF;
166 YamlMF.Name = MF.getName();
167 YamlMF.Alignment = MF.getAlignment();
168 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
169 YamlMF.HasInlineAsm = MF.hasInlineAsm();
170 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
171 ModuleSlotTracker MST(MF.getFunction()->getParent());
172 MST.incorporateFunction(*MF.getFunction());
173 convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
174 convertStackObjects(YamlMF, *MF.getFrameInfo(), MST,
175 MF.getSubtarget().getRegisterInfo());
176 if (const auto *ConstantPool = MF.getConstantPool())
177 convert(YamlMF, *ConstantPool);
178 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
179 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
180 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
181 bool IsNewlineNeeded = false;
182 for (const auto &MBB : MF) {
185 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
187 IsNewlineNeeded = true;
190 yaml::Output Out(OS);
194 void MIRPrinter::convert(yaml::MachineFunction &MF,
195 const MachineRegisterInfo &RegInfo,
196 const TargetRegisterInfo *TRI) {
197 MF.IsSSA = RegInfo.isSSA();
198 MF.TracksRegLiveness = RegInfo.tracksLiveness();
199 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
201 // Print the virtual register definitions.
202 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
203 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
204 yaml::VirtualRegisterDefinition VReg;
207 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
208 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
210 printReg(PreferredReg, VReg.PreferredRegister, TRI);
211 MF.VirtualRegisters.push_back(VReg);
214 // Print the live ins.
215 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
216 yaml::MachineFunctionLiveIn LiveIn;
217 printReg(I->first, LiveIn.Register, TRI);
219 printReg(I->second, LiveIn.VirtualRegister, TRI);
220 MF.LiveIns.push_back(LiveIn);
222 // The used physical register mask is printed as an inverted callee saved
224 const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
225 if (UsedPhysRegMask.none())
227 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
228 for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
229 if (!UsedPhysRegMask[I]) {
230 yaml::FlowStringValue Reg;
231 printReg(I, Reg, TRI);
232 CalleeSavedRegisters.push_back(Reg);
235 MF.CalleeSavedRegisters = CalleeSavedRegisters;
238 void MIRPrinter::convert(ModuleSlotTracker &MST,
239 yaml::MachineFrameInfo &YamlMFI,
240 const MachineFrameInfo &MFI) {
241 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
242 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
243 YamlMFI.HasStackMap = MFI.hasStackMap();
244 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
245 YamlMFI.StackSize = MFI.getStackSize();
246 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
247 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
248 YamlMFI.AdjustsStack = MFI.adjustsStack();
249 YamlMFI.HasCalls = MFI.hasCalls();
250 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
251 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
252 YamlMFI.HasVAStart = MFI.hasVAStart();
253 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
254 if (MFI.getSavePoint()) {
255 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
256 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
257 .printMBBReference(*MFI.getSavePoint());
259 if (MFI.getRestorePoint()) {
260 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
261 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
262 .printMBBReference(*MFI.getRestorePoint());
266 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
267 const MachineFrameInfo &MFI,
268 ModuleSlotTracker &MST,
269 const TargetRegisterInfo *TRI) {
270 // Process fixed stack objects.
272 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
273 if (MFI.isDeadObjectIndex(I))
276 yaml::FixedMachineStackObject YamlObject;
278 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
279 ? yaml::FixedMachineStackObject::SpillSlot
280 : yaml::FixedMachineStackObject::DefaultType;
281 YamlObject.Offset = MFI.getObjectOffset(I);
282 YamlObject.Size = MFI.getObjectSize(I);
283 YamlObject.Alignment = MFI.getObjectAlignment(I);
284 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
285 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
286 MF.FixedStackObjects.push_back(YamlObject);
287 StackObjectOperandMapping.insert(
288 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
291 // Process ordinary stack objects.
293 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
294 if (MFI.isDeadObjectIndex(I))
297 yaml::MachineStackObject YamlObject;
299 if (const auto *Alloca = MFI.getObjectAllocation(I))
300 YamlObject.Name.Value =
301 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
302 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
303 ? yaml::MachineStackObject::SpillSlot
304 : MFI.isVariableSizedObjectIndex(I)
305 ? yaml::MachineStackObject::VariableSized
306 : yaml::MachineStackObject::DefaultType;
307 YamlObject.Offset = MFI.getObjectOffset(I);
308 YamlObject.Size = MFI.getObjectSize(I);
309 YamlObject.Alignment = MFI.getObjectAlignment(I);
311 MF.StackObjects.push_back(YamlObject);
312 StackObjectOperandMapping.insert(std::make_pair(
313 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
316 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
317 yaml::StringValue Reg;
318 printReg(CSInfo.getReg(), Reg, TRI);
319 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
320 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
321 "Invalid stack object index");
322 const FrameIndexOperand &StackObject = StackObjectInfo->second;
323 if (StackObject.IsFixed)
324 MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
326 MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
328 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
329 auto LocalObject = MFI.getLocalFrameObjectMap(I);
330 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
331 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
332 "Invalid stack object index");
333 const FrameIndexOperand &StackObject = StackObjectInfo->second;
334 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
335 MF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
338 // Print the stack object references in the frame information class after
339 // converting the stack objects.
340 if (MFI.hasStackProtectorIndex()) {
341 raw_string_ostream StrOS(MF.FrameInfo.StackProtector.Value);
342 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
343 .printStackObjectReference(MFI.getStackProtectorIndex());
347 void MIRPrinter::convert(yaml::MachineFunction &MF,
348 const MachineConstantPool &ConstantPool) {
350 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
351 // TODO: Serialize target specific constant pool entries.
352 if (Constant.isMachineConstantPoolEntry())
353 llvm_unreachable("Can't print target specific constant pool entries yet");
355 yaml::MachineConstantPoolValue YamlConstant;
357 raw_string_ostream StrOS(Str);
358 Constant.Val.ConstVal->printAsOperand(StrOS);
359 YamlConstant.ID = ID++;
360 YamlConstant.Value = StrOS.str();
361 YamlConstant.Alignment = Constant.getAlignment();
362 MF.Constants.push_back(YamlConstant);
366 void MIRPrinter::convert(ModuleSlotTracker &MST,
367 yaml::MachineJumpTable &YamlJTI,
368 const MachineJumpTableInfo &JTI) {
369 YamlJTI.Kind = JTI.getEntryKind();
371 for (const auto &Table : JTI.getJumpTables()) {
373 yaml::MachineJumpTable::Entry Entry;
375 for (const auto *MBB : Table.MBBs) {
376 raw_string_ostream StrOS(Str);
377 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
378 .printMBBReference(*MBB);
379 Entry.Blocks.push_back(StrOS.str());
382 YamlJTI.Entries.push_back(Entry);
386 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
387 const auto *TRI = MF.getSubtarget().getRegisterInfo();
389 for (const uint32_t *Mask : TRI->getRegMasks())
390 RegisterMaskIds.insert(std::make_pair(Mask, I++));
393 void MIPrinter::print(const MachineBasicBlock &MBB) {
394 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
395 OS << "bb." << MBB.getNumber();
396 bool HasAttributes = false;
397 if (const auto *BB = MBB.getBasicBlock()) {
399 OS << "." << BB->getName();
401 HasAttributes = true;
403 int Slot = MST.getLocalSlot(BB);
405 OS << "<ir-block badref>";
407 OS << (Twine("%ir-block.") + Twine(Slot)).str();
410 if (MBB.hasAddressTaken()) {
411 OS << (HasAttributes ? ", " : " (");
412 OS << "address-taken";
413 HasAttributes = true;
415 if (MBB.isLandingPad()) {
416 OS << (HasAttributes ? ", " : " (");
418 HasAttributes = true;
420 if (MBB.getAlignment()) {
421 OS << (HasAttributes ? ", " : " (");
422 OS << "align " << MBB.getAlignment();
423 HasAttributes = true;
429 bool HasLineAttributes = false;
430 // Print the successors
431 if (!MBB.succ_empty()) {
432 OS.indent(2) << "successors: ";
433 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
434 if (I != MBB.succ_begin())
436 printMBBReference(**I);
437 if (MBB.hasSuccessorWeights())
438 OS << '(' << MBB.getSuccWeight(I) << ')';
441 HasLineAttributes = true;
444 // Print the live in registers.
445 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
446 assert(TRI && "Expected target register info");
447 if (!MBB.livein_empty()) {
448 OS.indent(2) << "liveins: ";
449 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
450 if (I != MBB.livein_begin())
452 printReg(*I, OS, TRI);
455 HasLineAttributes = true;
458 if (HasLineAttributes)
460 bool IsInBundle = false;
461 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
462 const MachineInstr &MI = *I;
463 if (IsInBundle && !MI.isInsideBundle()) {
464 OS.indent(2) << "}\n";
467 OS.indent(IsInBundle ? 4 : 2);
469 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
476 OS.indent(2) << "}\n";
479 void MIPrinter::print(const MachineInstr &MI) {
480 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
481 const auto *TRI = SubTarget.getRegisterInfo();
482 assert(TRI && "Expected target register info");
483 const auto *TII = SubTarget.getInstrInfo();
484 assert(TII && "Expected target instruction info");
485 if (MI.isCFIInstruction())
486 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
488 unsigned I = 0, E = MI.getNumOperands();
489 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
490 !MI.getOperand(I).isImplicit();
494 print(MI.getOperand(I), TRI);
499 if (MI.getFlag(MachineInstr::FrameSetup))
500 OS << "frame-setup ";
501 OS << TII->getName(MI.getOpcode());
505 bool NeedComma = false;
509 print(MI.getOperand(I), TRI);
513 if (MI.getDebugLoc()) {
516 OS << " debug-location ";
517 MI.getDebugLoc()->printAsOperand(OS, MST);
520 if (!MI.memoperands_empty()) {
522 bool NeedComma = false;
523 for (const auto *Op : MI.memoperands()) {
532 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
533 OS << "%bb." << MBB.getNumber();
534 if (const auto *BB = MBB.getBasicBlock()) {
536 OS << '.' << BB->getName();
540 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
543 printLLVMNameWithoutPrefix(OS, BB.getName());
546 const Function *F = BB.getParent();
548 if (F == MST.getCurrentFunction()) {
549 Slot = MST.getLocalSlot(&BB);
551 ModuleSlotTracker CustomMST(F->getParent(),
552 /*ShouldInitializeAllMetadata=*/false);
553 CustomMST.incorporateFunction(*F);
554 Slot = CustomMST.getLocalSlot(&BB);
562 void MIPrinter::printIRValueReference(const Value &V) {
565 printLLVMNameWithoutPrefix(OS, V.getName());
568 // TODO: Serialize the unnamed IR value references.
569 OS << "<unserializable ir value>";
572 void MIPrinter::printStackObjectReference(int FrameIndex) {
573 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
574 assert(ObjectInfo != StackObjectOperandMapping.end() &&
575 "Invalid frame index");
576 const FrameIndexOperand &Operand = ObjectInfo->second;
577 if (Operand.IsFixed) {
578 OS << "%fixed-stack." << Operand.ID;
581 OS << "%stack." << Operand.ID;
582 if (!Operand.Name.empty())
583 OS << '.' << Operand.Name;
586 void MIPrinter::printOffset(int64_t Offset) {
590 OS << " - " << -Offset;
593 OS << " + " << Offset;
596 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
597 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
598 for (const auto &I : Flags) {
606 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
607 if (!Op.getTargetFlags())
610 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
611 assert(TII && "expected instruction info");
612 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
613 OS << "target-flags(";
614 if (const auto *Name = getTargetFlagName(TII, Flags.first))
617 OS << "<unknown target flag>";
618 // TODO: Print the target's bit flags.
622 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
623 const auto *TII = MF.getSubtarget().getInstrInfo();
624 assert(TII && "expected instruction info");
625 auto Indices = TII->getSerializableTargetIndices();
626 for (const auto &I : Indices) {
627 if (I.first == Index) {
634 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
635 printTargetFlags(Op);
636 switch (Op.getType()) {
637 case MachineOperand::MO_Register:
638 // FIXME: Serialize the tied register.
640 OS << (Op.isDef() ? "implicit-def " : "implicit ");
641 if (Op.isInternalRead())
649 if (Op.isEarlyClobber())
650 OS << "early-clobber ";
653 printReg(Op.getReg(), OS, TRI);
654 // Print the sub register.
655 if (Op.getSubReg() != 0)
656 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
658 case MachineOperand::MO_Immediate:
661 case MachineOperand::MO_CImmediate:
662 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
664 case MachineOperand::MO_FPImmediate:
665 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
667 case MachineOperand::MO_MachineBasicBlock:
668 printMBBReference(*Op.getMBB());
670 case MachineOperand::MO_FrameIndex:
671 printStackObjectReference(Op.getIndex());
673 case MachineOperand::MO_ConstantPoolIndex:
674 OS << "%const." << Op.getIndex();
675 printOffset(Op.getOffset());
677 case MachineOperand::MO_TargetIndex: {
678 OS << "target-index(";
679 if (const auto *Name = getTargetIndexName(
680 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
685 printOffset(Op.getOffset());
688 case MachineOperand::MO_JumpTableIndex:
689 OS << "%jump-table." << Op.getIndex();
691 case MachineOperand::MO_ExternalSymbol:
693 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
694 printOffset(Op.getOffset());
696 case MachineOperand::MO_GlobalAddress:
697 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
698 printOffset(Op.getOffset());
700 case MachineOperand::MO_BlockAddress:
701 OS << "blockaddress(";
702 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
705 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
707 printOffset(Op.getOffset());
709 case MachineOperand::MO_RegisterMask: {
710 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
711 if (RegMaskInfo != RegisterMaskIds.end())
712 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
714 llvm_unreachable("Can't print this machine register mask yet.");
717 case MachineOperand::MO_RegisterLiveOut: {
718 const uint32_t *RegMask = Op.getRegLiveOut();
720 bool IsCommaNeeded = false;
721 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
722 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
725 printReg(Reg, OS, TRI);
726 IsCommaNeeded = true;
732 case MachineOperand::MO_Metadata:
733 Op.getMetadata()->printAsOperand(OS, MST);
735 case MachineOperand::MO_CFIIndex: {
736 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
737 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
741 // TODO: Print the other machine operands.
742 llvm_unreachable("Can't print this machine operand at the moment");
746 void MIPrinter::print(const MachineMemOperand &Op) {
748 // TODO: Print operand's target specific flags.
751 if (Op.isNonTemporal())
752 OS << "non-temporal ";
753 if (Op.isInvariant())
758 assert(Op.isStore() && "Non load machine operand must be a store");
761 OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
762 if (const Value *Val = Op.getValue()) {
763 printIRValueReference(*Val);
765 const PseudoSourceValue *PVal = Op.getPseudoValue();
766 assert(PVal && "Expected a pseudo source value");
767 switch (PVal->kind()) {
768 case PseudoSourceValue::Stack:
771 case PseudoSourceValue::GOT:
774 case PseudoSourceValue::JumpTable:
777 case PseudoSourceValue::ConstantPool:
778 OS << "constant-pool";
780 case PseudoSourceValue::FixedStack:
781 printStackObjectReference(
782 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
784 case PseudoSourceValue::GlobalValueCallEntry:
785 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
786 OS, /*PrintType=*/false, MST);
788 case PseudoSourceValue::ExternalSymbolCallEntry:
790 printLLVMNameWithoutPrefix(
791 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
795 printOffset(Op.getOffset());
796 if (Op.getBaseAlignment() != Op.getSize())
797 OS << ", align " << Op.getBaseAlignment();
798 auto AAInfo = Op.getAAInfo();
801 AAInfo.TBAA->printAsOperand(OS, MST);
804 OS << ", !alias.scope ";
805 AAInfo.Scope->printAsOperand(OS, MST);
807 if (AAInfo.NoAlias) {
809 AAInfo.NoAlias->printAsOperand(OS, MST);
811 if (Op.getRanges()) {
813 Op.getRanges()->printAsOperand(OS, MST);
818 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
819 const TargetRegisterInfo *TRI) {
820 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
825 printReg(Reg, OS, TRI);
828 void MIPrinter::print(const MCCFIInstruction &CFI,
829 const TargetRegisterInfo *TRI) {
830 switch (CFI.getOperation()) {
831 case MCCFIInstruction::OpSameValue:
832 OS << ".cfi_same_value ";
835 printCFIRegister(CFI.getRegister(), OS, TRI);
837 case MCCFIInstruction::OpOffset:
838 OS << ".cfi_offset ";
841 printCFIRegister(CFI.getRegister(), OS, TRI);
842 OS << ", " << CFI.getOffset();
844 case MCCFIInstruction::OpDefCfaRegister:
845 OS << ".cfi_def_cfa_register ";
848 printCFIRegister(CFI.getRegister(), OS, TRI);
850 case MCCFIInstruction::OpDefCfaOffset:
851 OS << ".cfi_def_cfa_offset ";
854 OS << CFI.getOffset();
856 case MCCFIInstruction::OpDefCfa:
857 OS << ".cfi_def_cfa ";
860 printCFIRegister(CFI.getRegister(), OS, TRI);
861 OS << ", " << CFI.getOffset();
864 // TODO: Print the other CFI Operations.
865 OS << "<unserializable cfi operation>";
870 void llvm::printMIR(raw_ostream &OS, const Module &M) {
871 yaml::Output Out(OS);
872 Out << const_cast<Module &>(M);
875 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
876 MIRPrinter Printer(OS);